remote global alignment error for pad inductor layer to improve...

Proceedings of the 2016 International Conference on Industrial Engineering and Operations Management Kuala Lumpur, Malaysia, March 8-10, 2016

Remote Global Alignment Error for Pad Inductor Layer To Improve Cycle Time

Saandilian Devadas Department of Manufacturing Design

Faculty of Manufacturing Engineering, Universiti Teknikal Malaysia Melaka,

76100, Durian Tunggal, Melaka, Malaysia [email protected]

Shajahan Bin Maidin Department of Manufacturing Design

Faculty of Manufacturing Engineering, Universiti Teknikal Malaysia Melaka,

76100, Durian Tunggal, Melaka, Malaysia [email protected]

Tritham Wara Department of Photo Lithography

Silterra Malaysia Sdn. Bhd, 09000, Kulim, Kedah, Malaysia

[email protected]

Nurul Ayu Binti Hashim Department of Photo Lithography


[email protected]

Leng Kok Hong Department of CIM - ES


[email protected]

Abstract— Lithography is the key process which transfers the pattern on one mask (reticle) to the resist layer and pad inductor layer is the last layer in photo masking. This cause the cycle time for pad inductor layer increase due to having 32% of Global Alignment (GA) error per month currently at Silterra Malaysia Sdn Bhd. This induce success rate goes down as low as 50%. In the same time, long engineering time is taken to dispose the lot (Exp-Dev-Only) due to tool time availability since this activity needs to be performed by a Process Engineer in manually while few marks were required to be tested to align the wafer. Most of the lots send for rework causing the cost per wafer to increase. The goal of this project is to reduce the cycle time for pad inductor layers by introducing the “Remote Global Alignment Error Method” (RGAE) method with alternative flow. This would avoid the pad inductor layers to be send to rework if it encountered any global alignment error. The experimental result shows that the RGAE method provides fast solution to reduce cycle time for pad inductor layers. This is due when encounter global alignment error, the lot will automatically track in using RGAE script method by selecting the rejected wafers for expose and develop process. This has eventually save more time for split wafers and send for rework or run the lot manually and furthermore, the rework rate falls to 0%.

Keywords—Lithography, Pad Inductor Layer, Remote Global Alignment Error, Rework

Sponsor: Kementerian Pendidikan Malaysia

2061© IEOM Society International


I. INTRODUCTION

Photolithography is a tool that allows the integrated circuit engineer build electronic devices such as transistors, resistors and capacitors directly in the silicon itself and interconnect them to create a working electronic circuit [1]. Photolithography is often referred to as “photo” in laboratory conversation. An interconnected device forming a circuit that does a particular job is an integrated circuit (IC).

Photolithography is a process used in semiconductor device fabrication to transfer a pattern from a photo mask (also called reticle) to the surface of a wafer or substrate. Table 1 shows that the process is repeated for up to 30 times for one devices that transforming patterns from reticles to wafers. The repetition of this process normally require different reticles which having different chrome pattern on it. However some layers like some implant layers share the same reticle. Reticles or Masks are made of thin patterned chromium on a transparent quartz glass plate. Patterns are transferred from reticle to the wafer surface by:

• Spreading photo resist out onto a substrate,

• Exposed with a desired pattern,

• Developed into a selective pattern for subsequent processing.

Fig 1. Photo Process Sequence

Since many layers make up a completed wafer, each additional layer must be aligned precisely and accurately with the previous one. Critical dimensions may be less than 1 micron which places a great burden on the alignment process. Alignment is done with patterns placed in the scribe lines during the resist development. When subsequent layers are put down, the layer patterns are aligned by adjusting the position of the projection with the alignment marks on the wafer. The specific markings vary from one manufacturer to another, but the objective is always the same to align the current layer with previous layer by using alignment marks. The markings are designed so that very small misalignments could be easily detected.

There are two chucks at the ASML scanner tool as shown in Figure 2. At the Pre-Align, the wafer needs to be pre-aligned to a certain distance at the notch by using the edge sensor [2]. Then, it is aligned on the E-chuck (E-chuck is exposure chuck) for an accurate alignment. There is a specific alignment strategy ID that is already fixed at the relevant layer.

Fig 2. Chuck at ASML Tool



II. LITERATURE REVIEW Pfund, Mason and Fowler (2006) describe about the important of cycle time in semiconductor field [3]. They explained

about the time spent to process a product. Lentz (2011) have shown in a study that, by reducing one percent of cycle time, it can decrease the cost per produced wafer by 0.7 percent [4]. The most famous paper about photo cycle time is probably by Factory physics (2000) [5].

The researcher explains in this paper about the behaviour of manufacturing systems with good analysis of the data. Adan and Resing (2001) describe about analyse of manufacturing lines for reduce cycle time in photolithography department [6]. They explain regarding full analysis of a single machine subject to time dependent failure. Their analysis fully applies to photo tools that process one product at a time. A photolithography tool that having a lot of processing steps for running many different devices. This means that many wafers can be processed at the same time.

Kock (2008) and Veeger (2010) used effective process time (EPT) method to model photolithography machines [7] & [8]. The effective process time (EPT) model called an aggregate simulation model. This model wills combines everything that happens in a tool. This approach uses the arrival and departure times for a machine to model it. The result from this model proved that do not need a lot of data to generate mean cycle time.

Furthermore, Van der Eerden (2004) who was working at ASML did a research about both a simulation model and queuing model [9]. He describes theoretical about photolithography tools and research regarding rework, effect of global alignment error, wafer rejects and tool dedication on both throughput and cycle time. In the same time, Aarts (2003) explain the same approach to study the effect of tool preventive maintenance, setup time, and unscheduled tool downs on the cycle times for a theoretical photolithography tools [10]. Both these studies used a detailed model that was not based on measured data, which makes it hard to translate their results to a real machine.

Babbs and Gaskins (2008) based on universal SEMATECH data analysis; explain in cycle time for a semiconductor manufacturing system for reduce tool downtime [11]. In the same time, Schoemig (1999) explain about variability reduction on cycle time [12]. He investigated the effect on cycle time of reducing the variance of the time to repair. Taylor and Heragu (1999), performed a similar study to prove about reducing in mean cycle time for tool down time [13]. This was a huge improvement plan on cycle time. They prove that reducing the cycle time mean is a more effective way in tool down time. Practical work was done by Van der Eerden (2006), who performed a cycle time improvement study in an actual semiconductor manufacturing plant [14]. They used a hybrid approach where EPTs are calculated from actual data from a factory operated by TI. In this paper, the researcher explains about the effect on cycle time after analysis on the EPT. This leads to a list of possible improvements and their impact to the system. Their approach finally improve photolithography cycle time until almost 50%. However, we still doubt on their accuracy of the cycle time predictions. However, the results shows that huge reduction on cycle time in semiconductor field.

III. METHODOLOGY In photolithography, alignment performance between current layer with previous layer is very important. Furthermore,

wafer global alignment marks is use a minimum of two and maximum of 25 alignment mark on the wafer. There are two kinds of global alignment marks. That are:

A. Coarse Wafer Global Alignment Marks • The Scribe-lane Primary Mark (SPM) in X & Y alignment and use 2 pairs of X and Y

B. Fine Wafer Global Alignment Marks • The Scribe-lane Primary Mark (SPM) in X and Y and use 4 pairs of X and Y

These alignments are designed to fit in the scribe lane between dies. There is X-version and Y-version which is X-for X alignment and Y-for Y alignment. The cycle time of a given routing (process flow) is the average time from release of a job at the beginning of the routing until it reaches an inventory point at the end of the routing. The time the part spends as WIP (Work In Progress). Lot cycle time is the time taken from lot start until lot end the process at a step using the specified recipe. In meanwhile, the throughput (WPH) is the number of wafers can be produced per hour as shown in Figure 3.

Fig 3. WPH Calculation

WPH = 3600 x Lot Size Process Time*

(seconds) * Process time = Time taken from Lot End to Lot End



All All the semiconductor company will try to reduce the Cycle Time. This is due to increased throughput (WPH). The (WPH) is the average output of a production process per unit time. By reducing the cycle time, the company will be reduced operating costs, reduced inventory costs, can increase the Quality and will be have ccompetition that can response fast to customer needs [15]. So, by reducing the cycle time, the company can make more money. This is because the time lost is not recoverable. So do not waste time [16] & [17].

Capacity planning is the process of determining the production capacity needed by an organization to meet changing demands for its products [18]. In the context of capacity planning, design capacity is the maximum amount of work that an organization is capable of completing in a given period. Four types of capacity planning are Availability, Manufacturing Efficiency, Downtime and Operational Utilization

1) Availability

The Equipment Availability to run production, engineering and test wafers. Availability excludes scheduled downtime, unscheduled downtime and activities such as cleaninga and calibration.

= (Total Time - NonScheduled Time - UnScheduled Downtime - Scheduled Downtime - Setup Time) (Total Time - Non Scheduled Time)

= Equipment Uptime Operations Time

2) Manufacturing Efficiency

The percentage of available time that is used for processing. The remaining time is lost due to operational inefficiencies such as wait for WIP, wait for the load and idle.

= Productive time + Engineering Time Equipment Uptime

3) Downtime

The time a tool is not available to run production due to unscheduled, scheduled maintenance and set up.

4) Operational Utilization

= Productive time + Engineering Time Operations Time

= Availability * Manufacturing Efficiency

Fig. 4. Summary of Cycle Time



OEE measures the nett available equipment capacity in relation to the total potential capacity of the equipment.

Fig. 5. OEE Calculation Method

OEE Formula breakdown and explanation

Availability = (Run+Idle)/(Run+Idle+Down)

Mfg Efficiency = Run/(Run +Idle)

Performance Efficiency=Actual Wafer Move/(Plan WPH*Run Hr)

Yield = Assume 100% for all tools

A. Remote Global Alignment Error (RGAE)Pad Inductor layer encounter 32% of global alignment error per month. This is purely due to Very thick oxide deposition

coupled with very thick PR thickness degraded signal quality. Thick metal slab minimizing Via mark depth and Metal grain/hillock caused signal distortion [19] & [20]. The increase trend of global alignment error causing increase of cycle time for pad inductor layer. In this experiment, the main goal is to reduce cycle time for pad inductor layer by introduce Remote Global Alignment Error Method.

This project is to evaluate the alternative flow for reduce cycle time for Pad Inductor Layer. The new flow name as Remote Global Alignment Error RGAE method. The RGAE method only can use for C18 Technology and for Pad Inductor layer only. In the new proposal method, not have send ahend step and also not have rework flow. So the rejected wafers need to split at Visual Inspection step. Looping at GA_PADIND path step only allow 3 times only. If it is still unsuccessful, a process to split the affected wafers for rework should be done. The RGAE method needs special Skip GAStep privilege that will allow for Global Alignment path only. After running all global alignment error wafers, the process is to place future holds at Visual Inspection step for 100% inspection Only "Reject" wafer status from scanner will be reuse under Global Alignment flow.

B. Proposal Method Reduce PAD Inductor Cycle Time Flow (RGAE)Figure 6 shows that the current method that using for pad inductor global alignment error that causing high cycle time due

to the rejected wafers need send for rework. Furthermore, Figure 7 shows those proposed RGAE methods that reduce cycle time for pad inductor global alignment error due to reject wafers will run again automatically until the wafers successfully expose.

Many egineering and science problems can be represented as a problem in graph theory. The graph represents the scenario of the real-life applications where the nodes in the graph can be treated as nodes in a network, and the edges are representing the communication links between the nodes. The relationship between a complete graph and its single-row representation was first formulated in [6] and [7]. Both models discuss the technique of transforming a graph into a single-row network where ESSR is applied to produce optimal results. The transformation finds its application, for example, in assigning telephone channels to caller-receiver pairs roaming in cellular regions in a cellular network on real-time basis [8]. Table 1 shows the results from Connected Graph Sequence (CGS).



Fig 6. Current Method Fig 7. Proposal (RGAE) Method

IV. RESULTS AND DISCUSSION A. Global Alignment Error on Alignment Advisor Test

A few devices from C18 technologies was selected to test alignment mark performance on pad inductor layer. Based on the data, the signal for parameter MCC, WWQ and Delta Shift for the new mark are same with the STD-ISL mark which is lower than control limit and it shows that the new mark does not give a good signal from the wafer comparing with others available mark.

Four alignment parameters/data need to be evaluated to qualify the Pad Inductor alignment mark. That are:-

• Multiple Correlation-coefficient (MCC)

• Delta Shift

• Wafer Quality

• Mark Residuals

1) Multiple Correlation-coefficients (MCC)

Multiple correlation coefficients (MCC) can be described as percentage or degree to which alignment signal fits a sine wave expressed as a decimal. The MCC needs more than 0.7 (recommended by ASML) and used as validation criterion. Figure 8 results show that MCC mark performance between two different marks that use for the pad inductor layer. One mark has good MCC performance compare to another mark.

Fig. 8. Test Result for MCC



2) Delta Shift (8.0 to 8.8 shift)

Delta shift can cause by machine (systematic alignment shift) and also by mark error or problems. As long as the delta shiftless than then +/-200, alignment should be accepted and aligned position should be found correctly. Figure 9 results show that delta shift mark performance between two different marks that use for pad inductor layer. The results show that, both marks are not good performance marks base on delta shift range that having more than +/-200. If this both marks release for use on production lot, high chance will have misalignment.

Fig. 9. Test Result for Delta Shift

3) Wafer Quality & Signal Strength

Water Quality is normalized ratio of signal strength or gain of the wafer to wafer stage mark. It used to indicate alignmentsignal strength that required at least 1% , desired as high as possible. Low wafer quality not necessary will give bad alignment as long as the mark is symmetric. Figure 10 results show that wafer quality mark performance between two different marks that use for the pad inductor layer. Both marks less than 0.5 and not a suitable use for production lot.

Fig. 10. Test Result for Wafer Quality

4) Mark Residuals

Mark residuals used as a validation check to determine how well dose each mark’s fit in the calculation grid. The residualshould not exceed 200nm. Furthermore, the mark residuals calculate base on minimum should have three alignment marks.

V. CONCLUSION In this experiment, the test shows that the mark performance for pad inductor was very bad. Many tests on different devices already done and show negative results. Due to global alignment error, the cycle time for pad inductor also increases. The goal of this research is to reduce cycle time for pad inductor layer due to global alignment error. This research has two objectives:

• By Introducing the Remote global alignment error (RGAE)Method

• Introduce alternative flow for avoid send to rework



Both objectives are successfully implemented and the goal reduces cycle time for pad inductor layer was achieved. This was done when tested with eight different devices for the pad inductor layer that have global alignment errors. All rejected wafers automatically selected and successfully “track in” inside tool using alternative flow that have a different alignment mark. Finally, all rejected wafers were exposed and avoid send for rework. This huge achievement reduces significantly cycle time for the pad inductor layer.

Some recommendations for future work:-

• Apply the same (RGAE) method for other critical layers that encounter global alignment error

• Able to “track out” when encounter 1st time global alignment error and able “track in” again in another tool. For current(RGAE) method, not able simulate this function

• Able to find out the solution to improve pad inductor alignment mark performance. This will more help in term ofreducing cycle time for pad inductor layers

ACKNOWLEDGEMENTS The authors are grateful to all those who have assisted directly or indirectly in providing the facilities and materials to complete this project at SilTerra Malaysia Sdn Bhd and at the Universiti Teknikal Malaysia Melaka

REFERENCES [1] Harry J. Levinson, Principles of Lithography, pg 201 – 223, SPIE Press (2001).[2] ASML, “ATHENA Knowledge Sharing”, Application Note, pg 24 – 28, ASML (1999).[3] M. E. Pfund, S. J. Mason, and J. W. Fowler. Handbook of Production Scheduling, chapter 9 : Semiconductor Manufacturing

Scheduling and Dispatching, pages 213-241. Springer, 2006.[4] M. Lentz. Industry economic model & enterprise value of cycle time. Presented at the SEMATECH Symposium Taiwan, Hsinchu,

Taiwan, September 2011.[5] W. Hopp and M. Spearman. Factory Physics Second Edition. McGraw-Hill/Irwin, 2000.[6] I. Adan and J. Resing. Queueing Theory: Ivo Adan and Jacques Resing. Eindhoven University of Technology. Department of

Mathematics and Computing Science, 2001.[7] A. Kock. E_ective Process Times for Aggregate Modeling of Manufacturing Systems, 2008.[8] C. Veeger. Aggregate modeling in semiconductor manufacturing using e_ective process times. 2010.[9] J. van der Eerden. Litho area productivity improvement. 2004.[10] S. Aarts. Inuence of Outages on LithoCell Performance. 2003.[11] D. Babbs and R. Gaskins. E_ect of reduced equipment downtime variability on cycle time in a conventional 300mm fab. In Advanced

Semiconductor Manufacturing Conference, 2008. ASMC 2008. IEEE/SEMI, pages 237{242, 2008.[12] A. Schoemig. On the corrupting inuence of variability in semiconductor manufacturing. In Simulation Conference Proceedings, 1999

Winter, volume 1, pages 837{842 vol.1.[13] G. D. Taylor and S. Heragu. A comparison of mean reduction versus variance reduction in processing times in ow shops. International

Journal of Production Research, 37(9):1919{1934, 1999.[14] J. van der Eerden, T. Saenger, W. Walbrick, H. Niesing, and R. Schuurhuis. Litho area cycle time reduction in an advanced 300mm

semiconductor manufacturing line. In Advanced Semiconductor Manufacturing Conference, 2006. ASMC 2006. The 17th AnnualSEMI/IEEE, pages 114{119, 2006.

[15] Toly Chen, “A Systematic Cycle Time Reduction Procedure for Enhancing the Competitiveness and Sustainability of aSemiconductor Manufacturer”, Sustainability 2013, 5, 4637-4652,2013

[16] Chien, C.F.; Hsu, C.Y.; Hsiao, C.W. Manufacturing intelligence to forecast and reduce semiconductor cycle time. J. Intell. Manuf.2012, 22, 2281–2294.

[17] Chen, T.; Wang, Y.C. An iterative procedure for optimizing the performance of the fuzzy-neural job cycle time estimation approach ina wafer fabrication factory. Math. Probl. Eng. 2012, doi: 10.1155/2013/740478.

[18] Occhino, T. J. 2000. Capacity planning model: the important inputs, formulas, and benefits, 2000 IEEE/SEMI AdvancedSemiconductor Manufacturing Conference, 455–458.

[19] ASML, “Process Effects on Alignment: Tungsten CMP/Aluminum PVD”, Application Note, pg 5 – 17, ASML (2004).[20] Yuanting Cui, Albert So, Sean Louks, “Fine Tune W-CMP Process with Alignment Mark Selection for Optimal Metal Layer and

Yield Benefits”, Proceeding of SPIE, Vol. 5375, pp. 827 – 838 (2004).



BIOGRAPHY Saandilian Devadas is Staff Engineer at Silterra Malaysia Sdn Bhd pursuing PhD in Industrial Engineering from University Technical Malaysia Melaka (UTEM). He has 10 years working experince in semiconductor photolithography department. He was work at STMicroelectronics, Singapore and Infineon Tehnologies (Kulim) Sd Bhd before jointed to Silterra. He earned Master of Science in Computer Science with Major in Graphics & Multimedia from University Technology Malaysia (UTM), Malaysia. He has published journal and conference papers.

Shajahan Maidin is a Senior Lecturer in the Faculty of Manufacturing Engineering at the University Technology Malaysia (UTM), Malaysia. He earned B.ENG. (Honors) in Manufacturing System Engineering from University of Portsmouth, UK, Masters in Manufacturing System Engineering from University of Warwick, UK and PhD in Design for Additive Manufacturing from University of Loughorough, UK. He has published journal and conference papers. Dr Shajahan Maidin has done research projects with Additive Manufacturing, Sustainable Product Development, Concurrent Engineering, Reverse Engineering, Computer Aided Design & Product Design.


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