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7/27/2019 Report Stage 1

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Time-to-Digital Converter

Vineet Sharma

M.tech (VLSI)

201311011

GUIDED BY:-

Prof. Biswajit Mishra


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Fig.1 Block Diagram of TDC[2]

IntroductionTime-to-Digital Converter (TDC) is used for measuring time interval between two events. It then

converts this time difference in a digital value.

In a simple form it can be considered as simple counter which starts running when the first eventstarts and stops counting when the other event takes place. The corresponding value of counter

gives the time difference between the events. The resolution of this counter based TDC cannot be

higher than the clock period of reference clock. So when time difference is in the range of

nanoseconds, we need counters operating at GHz frequency, as simple counters are not able to

operate at this frequency.

Because of limitations of the counter based TDCs, the new architectures has been proposed such

as Flash TDC and Vernier Delay line based TDC. These delay line based TDCshave high

resolution equivalent to the gate delay. [1] Because of high resolution, Delay line based TDC has

become popular and have lots of applications such as phase detection, time of flight

measurement, high speed signal capturing, data converters, etc.

Literature survey for TDCSeveral architecture has been proposed till date.Youngmin [2] has proposed a cyclic Vernier

TDC with digitally controlled oscillators (DCOs). Hong-Yi [4] has proposed a high-resolution

and wide-range TDC using a single-stage Vernier delay line (VDL).

DCO: Digital controlled oscillator

CNTs: Reading of coarse counter

CNTf: Reading of fine counter


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As the START signal arrives, slow DCO start oscillating a time period Tcoarse . The coarse

counter starts counting until the STOP signal arrives. At the arrival of STOP signal the Fast DCO

starts oscillating with a slightly lower period Tfine as compared to Tcoarse.

Fig. 2 Timing Diagram[2]

As the time period of Fast DCO is less than Slow DCO, it will certainly catch it after some

time.

The time between START and STOP signal can be calculated by

=

=+= + ( )


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Youngmin [2] Hong-Yi Huang [4]

Process 65nm CMOS 180nm CMOS

Supply 1.0 V 1.8V

Die Area 0.006mm

2

0.064mm

2

Technique Cyclic vernier Single stage

vernier dealy line

Resolution 5.5ps 10-80.6ps

Single shotprecision

0.008x(coarse+fine)+0.42LSB

Measurementrange 15 bits

Power Max 1.4mW(coarse)Max 0.63mW(fine) 5.55mW(*1)

9.34mW(*2)

Sampling

frequency 10MHz

Current ProgressCurrently I am working on Soft injection-ring oscillator. I have implemented it in breadboard

and performing experiments on it.

Fig.3 A soft-injection-locked ring oscillator

Table: Comparison Of Different TDCs architecture


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I am using crystal oscillator of 3.5MHz frequency and capacitances of 10pf for this experiment. I

am getting output frequency of 2.2MHz, but the shape of waveform is not pure rectangular.

.

Future workMy plan for next one to two months is:

To get the rectangular output waveform

After that replace this crystal oscillator with a different frequency crystal oscillator

Then try to catch the low frequency waveform by high frequency

And then count the number of periods and verify the formula for calculating the time

difference as mentioned earlier

References1. Time-to-Digital-Converters: Stephan Henzler, Springer series in advanced

microelectronics2. A Cyclic Vernier TDC for ADPLLs Synthesized From a Standard Cell Library

Youngmin Park, Student Member, IEEE, and David D. Wentzloff, Member, IEEE3. The Vernier-Based TDC Employing Soft-Injection- Locked Ring Oscillators Chia-Yu

Yao, Wei-Chun Hsia, Pei-Jung Tsai, and Yu-Jou Wen Department of Electrical

Engineering National Taiwan University of Science and Technology Taipei, Taiwan

4. All Digital Time-to-Digital Converter with High Resolution and Wide Detect Range,Hong-Yi Huang, Wei-Chung Hung, Hui-Wen Cheng and Ching-Hsing Lu

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