reporting of standard cell placement results patrick h. madden suny binghamton csd blac cad group...
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Reporting of Standard Cell Placement Results
Patrick H. Madden
SUNY Binghamton CSDBLAC CAD Group
http://vlsicad.cs.binghamton.edu
Thanks
Prof. Nael Abu-Ghazaleh, Patrika Agarwal, Dr. Charles Alpert, Andrew E. Caldwell, Prof. Jason Cong, Prof. Shananu Dutt, Dr. Hans Eisenmann, Bill Halpin, Dr. Dennis J.-H. Huang, Prof. Andrew B. Kahng, Prof. George Karypis, Faris Khundakjie, Prof. Cheng-Kok Koh, Prof. John Lillis, Igor L. Markov, Antonis Papadimitriou, Prof. Massoud Pedram, Dr. Bernhard Reis, Prof. Majid Sarrafzadeh, Prof. Carl Sechen, Ryon Smey, Dr. Bill Swartz, Arvind Vidyarthi, Dr Dongmin Xu, Xiaojian Yang, and Mehmet Can YILDIZ
Outline
Problem and Motivation The Benchmarks Common Metrics Reported Results Summary and Future Work
Standard Cells
Standard Cell Design
Objective
Place cells into rows to minimize wire length, congestion, delay, power, area, ….
MCNC Benchmarks
10+ years old Up to 25000 cells Golem3 benchmark (IBM) has nearly
100K cells
Half Perimeter Wire Length
Motivation:21.882 > 79.9
Yes, that’s correct.Reported results differ widely, and it’s difficult to make comparisons
The Devil is in the Details
How do you measure X?– We do it the same way as everyone else
Well, how exactly is that?– [generally 3 or 4 different responses]
Half Perimeter Wire Length
First port defined
Half Perimeter Wire Length
Center of cell
Half Perimeter Wire Length
Bounding box of pins
Half Perimeter Wire Length
Nearest port
Row Spacing
Row Spacing
Removal of channel area reduces wire length
Number of Rows
Suppose we have an 8x8 mesh….
Primary2: 29[15], 36[14], 28[19][5][7][11][24], 32[8]
Pad Positions
Scaling of Dimensions
Fract, Struct, Biomed, have dimensions scaled by a factor of 2 in TimberWolf based formats
Golem3 has dimensions scaled by a factor of 4
Tool Versions
TimberWolf has many academic and commercial versions
The academic version normally bundled with LAGER does not have the best performance
LAGER generates TW input configured for speed, and not quality
Reported Results:Avqlarge
Tool HPWL Spacing Port Location
FD98[5] 5.38 Row Origin
ARP[7] 6.54
Dragon[21] 5.25 Row Center
SPADE[24] 6.16 None Center
Mongrel[11] 4.87 None Center
Feng Shui[23] 6.301 Row Center
iTools[12] 4.78 Routed First
21.882 > 79.9?
21.882 79.9
Also, center-to-center, vs. first port, different numbers of rows, pad positions
19.975
Scale by 1/4
Summary
There are many unintentional skewed comparisons
No clear winner, for even a metric as simple as HPWL
If we want better placement tools, we should figure out what better means
Nobody cares about HPWL!
Real objective is to minimize delay, power, area, and make sure the chip can be routed (congestion)
30% difference in length estimate gives a 51% difference in RC delay for the wire….
But we have to crawl before we walk
Future Work
Some sort of agreement on HPWL and other metrics
New benchmarks for timing, power, routability (and placement competitions?)
Routing – the trouble in placement pales in comparison…
Suggestions
Zero row spacing Row numbers to allow square core area Pads at fixed locations HPWL to use exact pin locations,
minimum area bounding box to contain at least one port from each pin
Make placement results available (and tools too, if possible!)
What’s the Best Placer?
Mine, of course… But seriously, I have no idea (and would
be hard pressed to find a pair of tools where I’m confident that one is superior to the other)
How Good are Industry Tools
So good that no one wants to report results for the MCNC benchmarks
Academic tools don’t really consider congestion, delay, power, …. But how far off are we? How much WL do we lose, or should we expect to lose?