requirement for a package substrate to minimize the...
TRANSCRIPT
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Requirement for a package substrate to minimize the high temperature
package warpage
Nov. 17, 2009Hirofumi NakajimaNEC Electronics Co.
iNEMI Packaging substrates Workshop
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Agenda
1. High temperature package warpage2. Package warpage: trends3. PBGA, FBGA: temperature-dependent behavior 4. FCBGA: temperature dependent behavior 5. Bottom device of PoP: temperature-dependent
behavior 6. Mold compound requirements7. Package substrate requirements8. Motherboard warpage requirements9. Summary
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● ●● ●●● ● ●
● ●● ● ●● ● ●
Mother board
Mother board
Printed solder paste(75 um after reflow)
DieDie size
Mold compound
Substrate
Warpage
During reflow
High temperature package warpageExample: PBGA
Package warpage, deviation from flatness caused by internal stress, may cause unacceptable SMT quality including solder ballbridging and non-wet opens.
Both packages and PWB warp due to different CTEs, elastic ratios, and Tgs of composing materials.
Before reflow
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High temperature warpageExample: PoP (Package on package)
Room temperature
Reflowcondition
Bottom package of
PoP
Pre-stackingTop and bottom
packages
Top device of PoP behaves similar to FBGA.Bottom device of PoP always warps concave shape at elevated temperature, which tends to cause opens at center balls of each row or solder bridges at corner balls.
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0
50
100
150
200
250
300
0 10 20 30 40 50
Body size (mm)
War
page
at h
igh
tem
p. (u
m)
DryMoistured
PBGA, FBGAWarpage data example vs. criteria
220 um MAX for1.0 mm-pitch BGA
170 um MAX for 0.8 mm-pitch FBGA
110 um MAX for0.5 mm-pitch FBGA
The warpage data across PBGA’s and FBGA’s bottom faces are consolidated to verify whether the criteria are reasonable. Results: Existing larger packages do not meet the criteria when they are moist, but semiconductor suppliers will make effort to meet the criteria.
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Package warpage: trends
Convex (+) Concave (-)
• Increasing package size and decreasing package thicknessincrease the warpage.
• Larger package size requires larger footprint area on PWB, where both warpages become larger to fall in surface mount failures.
• Package warpage limits must also lower as time passes to widen the SMT process window and insure acceptable SMT quality.
• Optimization of materials and package construction is the sokution.
• PCB warpage improvement is also needed to share the burden imposed by SMT process demands for larger body sizes, at any given BGA pitch.
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ITRS draft for high temperature package warpage
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0.91.27
Cost-performance, high-performance and harsh applicationsLow-cost, mobile and memory applications
Ball Dia. (mm)Pitch (mm)
201720162015201420132012201120102009Year of Production
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PBGA, FBGA:Temperature-dependent behavior
• Molded condition is stress free, flat. Molding shrinkage and thesubsequent cooling cause the shrinkage of package.
• Reflow soldering makes a package expand and the CTE mismatch between materials causes the high temperature warpage.
Molding temp.Tg(substrate)
Tg (mold Resin)
RT
Stress in the PKG
↓Warpage
Molding shrinkage
Die set opening
Mold resin shrinkage
Peak temp.Of reflow
Temp.
Package dimension change
Die shrinkage Mold injection
Substrate shrinkage
11-14 ppm/deg
7- 9 ppm/deg
28- 35 ppm/deg
5-11 ppm/deg
3 ppm/deg
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PBGA, FBGA:Package design efforts• Package warpage is primarily design failure derived from the CTE mismatch
between die, substrate, and mold resin.• Warpage elements: material properties, die size, die thickness, substrate
thickness, mold thickness, and mold cap occupancy in the substrate area.
Molding temp.Tg(substrate)
Tg (mold Resin)
RT
Molding contraction
Die set opening
Mold resin shrinkage
Peak temp.Of reflow
Temp.
Package dimension change
Die shrinkage Mold injection
Balance 11-14 ppm/deg
7- 9 ppm/deg
28- 35 ppm/deg
5-11 ppm/deg
3 ppm/deg
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Adjusting molding shrinkage and CTE of mold resin is currently amain solution to improve warpage.
Conventional Less warp compoundSmaller molding shrinkage (%): 0.16 – 0.3 0.10 – 0.17Lower CTE α1 (ppm/deg): 9 – 15 7 – 9
α2 (ppm/deg): 30 – 50 28 – 35
PBGA, FBGA:Mold resin efforts
Molding temp.Tg(substrate)
Tg (mold Resin)
RT
Lower molding shrinkage
Mold resin shrinkage Lower α1
Lower α 2
Peak reflow temp.
Temp.
Package dimension change
Die shrinkage
Mold injection
Substrate shrinkage
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Even after using lower CTE mold resin, compound shrinkage of die and mold resin depend on die size. Substrate stiffness resists the stress and keeps package straight.Therefore, flexural modulus must be high even beyond Tg.
- Inorganic filler; amount, shape, size, material- Glass cloth; # of ply, flatten cloth, Aramid, Carbon fiber- Base resin; rigid backbone- Metal layer; # of Cu layer, thickness- Thicker substrate
PBGA, FBGA:Substrate efforts
Molding temp.Tg(substrate)
Tg (mold Resin)
RT
Mold resin shrinkage
Peak reflow temp.
Temp.
Package dimension change
Die shrinkage
Mold injection
Balance
Substrate must be flat, resisting the stress of CTE mismatch.
Modulus at RTDie: 130 – 180 GPaSubstrate: 18 – 17 GPaMold resin: 22 – 29 GPa
Modulus at 260 deg CDie: 130 – 180 GPaSubstrate: 10 – 15 GPaMold resin: 0.4 -1.8GPa
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FCBGA:temperature dependent behavior
Lower CTE of substrate and higher flexural modulus are solutions to achieve better FCBGA coplanarity at room temperature.
Molding temp.Tg(substrate)
RT
Substrate shrinkage
Peak temp.Of reflow
Underfillcure
Temp.
Package dimension change
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13
17
21
25
29
33 S1
S11
S21
S31
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60
80
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120
140
Z
[um
]
X [Ball]Y [Ball]
常温時(25℃)
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13
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33 S1
S12
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S34
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[um
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X [Ball]Y [Ball]
ピーク(250℃)
Die shrinkage
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FCBGA:Substrate efforts
Requirements • Thinner substrate• High flexural modulus core• Low CTE core• Mitigating CTE mismatch between
die and PWB
Source: Samsung Electro-mechanics
Package substrate
Core suppliers provide various products that appeal the advantage of their unique property balance.
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Bottom device of PoP:Temperature-dependent behavior
Small mold cap of PoP’s bottom device requires larger molding shrinkage rate and CTE of the mold resin.
Molding temp.Tg(substrate)
Tg (mold Resin)
RT
Mold resin shrinkage
Larger α1
Lager α 2
Peak temp.Of reflow
Mold injection
Temp.
Package dimension change
Die shrinkage
Larger molding shrinkage
Balance
Substrate shrinkage
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Bottom device of PoP:Mold resin efforts
Conventional Bottom PoP resinLarger molding shrinkage (%): 0.16 – 0.3 0.4 – 0.7Higher CTE α1 (ppm/deg): 9 – 15 17 – 34
α2 (ppm/deg): 30 – 50 60 – 90
Low CTE
High CTE
High CTE Mold compound
Silicon
Substrate
180°C ⇒ RT RT ⇒ 260°C
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Bottom device of PoP:Substrate efforts
Requirements • Thinner substrate• High flexural modulus core• Low CTE core
Source: Mitsubishi Gas Chemical
For higher flexural modulus, larger number of glass cloth plies or metal layers are preferred but also costly.
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Mold compound requirements
Low molding shrinkage and low CTE are basic requirements for molding resin for PBGA and FBGA.Less moisture absorption: Moist mold compound may have larger CTE, which causes larger warpage when reflowed.High molding shrinkage and high CTE are required for molding resin for the current mold cap design of PoP’s bottom device.Is it possible to prepare a series of mold resin variations which covers all CTE and molding shrinkage rates to adjust the CTE balance of package elements?
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0.10
#1
5045403530CTE above Tg
1816141210CTE below Tg
0.350.30.250.200.15Molding shrinkage
#6#5#4#3#2Mold resin type
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Package substrate requirements
In disregard of cost, the following means help to keep package straightness.
• Four or more metal layers• Two or more glass cloth plies• High flexural modulus polymer• Low CTE core• Low elastic modulus on the surface layers to
mitigate the stress caused by CTE mismatch.How can we refrain from increasing cost in using the preferred substrate structure?
• Standardizing substrate cores?• Creating roadmap for flexural modulus of
substrate• A two-ply core material must cost the same as a
one-ply core material.Motherboard warpage
• Less bow and twist at SMT footprint are requested
Si (3 ppm/deg)
SubstrateCore (11ppm/deg)
PWB (16 ppm/deg)
Low modulus
Low modulus
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Motherboard warpage requirements
Type Motherboard warpage 2008 2010 2012 2014 2016 2018
Laminate(%)
High volume production 0.5 0.5 0.5 0.5 0.5 0.5Advanced technology available in production 0.3 0.3 0.3 0.3 0.3 0.3
Cutting edge technology not available in production 0.2 0.2 0.2 0.2 0.2 0.2
Buildup(%)
High volume production 0.5 0.5 0.5 0.5 0.5 0.5Advanced technology available in production 0.3 0.3 0.3 0.3 0.3 0.3
Cutting edge technology not available in production 0.2 0.2 0.2 0.2 0.2 0.2
Source: Utsunomiya, JJTR 2009
Mother board warpage roadmap at room temperature is already too loose to satisfy the package warpage at elevated temperature.
3.03.02.02.01.51.0MAX Body size (mm): Cutting edge technology not available in production
2.02.01.31.31.00.7MAX Body size (mm): Advanced technology available in production
1.21.20.80.80.60.4MAX Body size (mm): High volume
606040403020MAX flatness of foot prints at PWB (um)
1.271.00.80.650.50.4Ball pitch (mm)
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Motherboard warpage requirements
Type Motherboard warpage 2008 2010 2012 2014 2016 2018
Laminate(%)
High volume production 0.5 0.5 0.5 0.5 0.5 0.5Advanced technology available in production 0.3 0.3 0.3 0.3 0.3 0.3
Cutting edge technology not available in production 0.2 0.2 0.2 0.2 0.2 0.2
Buildup(%)
High volume production 0.5 0.5 0.5 0.5 0.5 0.5Advanced technology available in production 0.3 0.3 0.3 0.3 0.3 0.3
Cutting edge technology not available in production 0.2 0.2 0.2 0.2 0.2 0.2
Source: Utsunomiya, JJTR 2009
Mother board warpage roadmap at room temperature is already too loose to satisfy the package warpage at elevated temperature.
3.03.02.02.01.51.0MAX Body size (mm): Cutting edge technology not available in production
2.02.01.31.31.00.7MAX Body size (mm): Advanced technology available in production
1.21.20.80.80.60.4MAX Body size (mm): High volume
606040403020MAX flatness of foot prints at PWB (um)
1.271.00.80.650.50.4Ball pitch (mm)
Too small size to be allowed for SMT
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Summary
Principally, package warpage at high temperature can be controlled by choosing the relevant material conbinations.
Mold resin for PBGA and FBGA to be
• lower CTE
• lower molding shrinkage
• A series of mold resin variations that provide CTE and mold shrinkage
Package substrate to be
• lower CTE
• higher flexural modulus
• Lower modulus on the surface layer to mitigate the stress derived from CTE mismatch between silicon and motherboard.
• the same cost as conventional substrate
Motherboard to be
• less warpage in the footprint area at both room and high temperatureEspecially, warpage roadmap of PWB does not meet the requirement of high temperature warpage of a package.
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