reram 3rd paper

Write Stress Reduction in 50nm AlxOy ReRAM Improves Endurance 1.4× and Write Time, Energy by 17%

Sheyang Ning1,2, Tomoko Ogura Iwasaki1, and Ken Takeuchi1

1Chuo University, Tokyo, Japan, 2University of Tokyo, Tokyo, Japan [email protected]

Abstract—Novel write verification methods are proposed to

improve write speed, energy and endurance of resistive random access memory (ReRAM). Flexible write stress is implemented during reset w/ verification and set w/ verification, by which the pulse width or voltage can be decremented as well as incremented. Proposed reset w/ verification and set w/ verification methods are characterized by measuring 50nm AlxOy ReRAM devices and compared against conventional methods. Improvements of 1.9× average endurance increase, or 1.4× average endurance increase with 17% write time, the reset time plus set time decrease and 17% average write energy reduction are demonstrated.

Index Terms—ReRAM, write with verification, ReRAM endurance, ReRAM write speed, ReRAM write energy.

I. INTRODUCTION Resistive random access memory (ReRAM) is considered

one of the most promising next generation nonvolatile memories due to its potential to provide fast write time, endurance and scalability [1]. However, ReRAM still faces several problems before commercialization. One of the issues is write performance degradation, in which switching to HRS or LRS becomes increasingly difficult over the lifetime of the device [2, 3]. In a prior work [3], HfO2 ReRAM device endurance was enhanced by introducing write with verification and increasing write stress adaptively as the device cycles. Further, increasing the voltage during set and increasing the pulse width (PW) during reset was found to be the most effective method to improve endurance. In this paper, a matrix of the previously proposed three reset cycling methods to determine reset pulse width (W1, W2 and W3) and three set cycling methods to determine set voltage (V1, V2 and V3) are applied to 50nm AlxOy ReRAM devices. Further, a new reset cycling method is proposed in which, the initial reset pulse width Tini_reset has the option to be decremented as well as incremented, and successive reset pulses during reset w/ verification are incremented by accelerated, rather than the conventional linear steps. The second proposal for set cycling applies the similar concepts of the decrement option to the voltage of the initial set pulse Vini_set. Compared with the conventional methods, applying the proposed reset and proposed set methods can increase the device average endurance by 1.9 times. Using proposed reset method with conventional set method V2, 1.4× endurance enhancement with 17% write time, the reset plus set write time reduction and 17% write energy saving can be achieved.

II. MEASUREMENT AND DISCUSSION

A. AlxOy ReRAM device characterization and endurance test by conventional methods The 1T1R AlxOy ReRAM single device resistance element

structure and the measurement setup are shown in Fig. 1. Figure 2 shows the current waveforms on set Vcell=2.5V, 100ns PW and reset Vcell= –1.5V, 20ns PW. Figure 3 describes the state diagram for the endurance test. A fresh ReRAM device is firstly formed by a 3V, 100ms pulse on Vcell. Then, the endurance test loop is entered. After 4000 fast set and reset cycles w/o verification (operation P2), one reset w/ verification (P3) is conducted to switch the ReRAM device to the high resistance state (HRS) with resistance >2×105Ω for reset success, and then one set w/ verification (P4) is conducted to switch the device to the low resistance state (LRS) with resistance <5×104Ω for set success. In P5, the conditions for the next cycle loop are determined, and then the sequence loops back to P2 for accelerating endurance cycling again. The endurance test ends when reset or set verification trials exceeds 21. Figure 4 shows details about the loop of P2~P5. Reset (–1.5V, Tini_reset) and set (Vini_set, 100ns) conditions are used in P2, P3 and P4 as the initial reset and set pulses. In prior work [3], during P3 reset w/ verification, PW is increased from Tini_reset by constant steps until the resistance meets the criteria for HRS. During P4 set w/ verification, set voltage is also increased linearly from Vini_set until LRS is met. P5 shows conventional variations of schemes to increase the Vini_set and Tini_reset for next cycling loop L+1. Three reset schemes make different decisions in P5. In W1, Tini_reset is not changed for L+1. W2 also maintains Tini_reset if the reset verification trial count m<4 in current loop L. If m≥4, it is likely that the current reset stress sequence is too weak, so Tini_reset is increased by 40ns for the next loop L+1. W3 uses the last and highest reset PW from reset verification, which increases Tini_reset by (m–1) × 40ns. For set, the schemes of V1, V2 and V3 are similar but the voltage is incremented by 0.1V with constant 100ns PW. The averaged endurance of 10 devices for each combination of these schemes are shown as a 3 reset × 3 set matrix in Fig. 5. All tested devices are failed on reset. The data for AlxOy matches the previous HfOx finding [3] that increasing PW (W2 and W3 vs. W1) enhances device endurance.

Figure 6 compares the Tini_reset increment as it changes with cycling for best conventional schemes combinations from Fig. 5. The best case device with the highest endurance within the 10 tested devices is illustrated for each method. The W1 scheme does not increase Tini_reset, which is fastest but has the lowest endurance, and is easy to fail when device is worn. W2 methods have the highest endurance and are faster than W3 but still relatively slow.

978-1-4673-6169-9/13/$31.00 ©2013 IEEE

B. Proposals for fast write, lower energy, and endurance enhancement Figure 7(a) shows the concept of proposed method. The

write speed can be increased by adding a decrement option for Tini_reset. The options to increase and decrease Tini_reset provide flexible write stress to adapt to the shifting of appropriate write conditions, for example, as a function of temperature [4], because set and reset becomes easier at higher temperature. Furthermore, one characteristic of ReRAM is that the filament shape can vary from cycle to cycle. Figure 7(b) illustrates the speculation that variations in filament shape could require both stronger and weaker program pulses. In the long term, it is expected that Tini_reset increase is necessary due to wearing in the barrier oxide [2, 3]. The first part of reset proposal (in P5) is shown in Fig. 8. If the previous reset loops L–2, L–1 and current loop L complete after the first trial, the current PW is judged to be more than adequate. Therefore, it is feasible to lower the reset condition, which decreases programming time, current and overall stress on the device. Thus, Tini_reset is decremented by –40ns in the next loop. Similarly, in the proposed set method, a decrement option of Vini_set–0.1V is added to the conventional V2 method. Figure 9 illustrates the second part of reset proposal. Instead of conventional constant increment, accelerated increment is proposed during reset w/ verification by using a factorial multiplier. By which, PW increases by 80ns in m=3 and by 120ns in m= 4.

Two metrics are defined in Fig. 10. The “total reset pulse width” is the cumulative PW in one reset w/ verification. “reset time plus set time” is the sum of “total reset pulse width”, read time (0.1µs) [5] in P3, P4, and set PW (0.1µs) in P4. In Fig. 11, the average endurance is increased when reset proposal (prop. P5 + prop. P3) is used. However, without the second part of reset proposal, which accelerates the reset PW increase in P3, the average endurance is found to decrease (prop. P5 with conv. P3). Fig. 12 and Fig. 13 shows reset pulse width and the initial set voltages for the best case devices, respectively. Extended endurance of 1.9× can be obtained by the proposed reset and proposed set method, compared with the conventional W2, V2 method. The key concept of the reset proposal can be clearly seen in Fig. 12, because Tini_reset stays lower and does not increase monotonically, as in the conventional W2 method. Large total PW’s are only occasionally required when the device reaches a hard-to-reset condition, possibly due to the variation of filament shape and size [6, 7]. By contrast, when the proposed increment and decrement of Tini_reset is used with the conventional constant PW increment of +40ns (prop. P5 + conv. P3), the device becomes difficult to reset within 21 verifications after wearing, or a larger reset stress would be required. Figure 13 shows that the proposed set method which allows increment and decrement of Vini_set maintains a lower average voltage level, compared with the conventional V2 method.

C. Comparison of write speed, write energy and average endurance Figure 14 compares the average total reset pulse width and

average reset time plus set time, on the devices with best endurance within 10 samples for each method. Resistance values were measured every 4000 cycles (due to P2) and then averaged in groups of 50, excluding the min and max values. As in Fig. 14(a), the proposed reset method highly optimizes the total reset PW especially during the latter half of device life

time. Further, there is no significant degradation of reset time plus set time for worn device, by using proposed reset method, as shown in Fig. 14(b).

In Fig. 15, Ereset_avg_1_device is the average energy of reset w/ verification, averaged over the cycles of one device. Ereset_avg_10_devices is also the average energy of reset w/ verification collectively averaged over 10 devices. Figure 16(a) shows the distribution of endurance and Ereset_avg_1_device on 10 devices for each method. In conventional reset, Tini_reset continues to increase with device cycling, which also causes increasing Ereset_avg_1_device. In Fig. 16(b), since the decrement of Tini_reset is applied in the proposed reset, in average the “prop. reset, V2” method decreases Ereset_avg_10_devices by 28%. As for the “prop. reset, prop. set”, it extends device cycling under lower set voltage (recall on Fig. 13) and larger reset pulse width. As a result the average endurance was largely increased but Ereset_avg_10_devices was slightly optimized. Figure 17(a) shows the distribution of Eset_avg_1_device on vertical axis. Interestingly, in Fig. 17(b), by using “prop. reset, prop. set” method, set energy increases 1.5×. The reason can be explained in Fig. 18, in which the proposed set has lower average set voltages (also in Fig. 13), which increases the average set verification trials. Thus overall set energy is increased by using proposed set method. Figure 19 shows that by “prop. reset, V2” is possible to decrease Ewrite_avg_10_devices by 17%, compared with the conventional approach.

Table 1 summarizes conventional and proposed methods characteristics of endurance, write time and energy consumption. Endurance enhancement of 1.9× is obtained by using proposed reset and set method. Also, by using the method of proposed reset with conventional set V2, 1.4× average endurance increase with 17% reset time plus set time reduction and 17% average write energy reduction can be achieved.

III. CONCLUSION Novel reset and set cycling methods are proposed to

improve 50nm AlxOy ReRAM device endurance, write time and energy consumption. The fluctuating characteristic of AlxOy ReRAM reset stress during cycling is understood, and a decrement option for Tini_reset and wider dynamic PW range is proposed. Reducing write stress by the proposed reset and set methods, provides improvements of 1.9× in endurance, or 1.4× endurance with 17% write time, the reset time plus set time and 17% write energy.

ACKNOWLEDGMENT The authors sincerely appreciate the support from H.

Akinaga, N. Awaya, K. Miyaji, K. Johguchi, M. Kobayashi, S. Hachiya, C. Sun and S. Tanakamaru.

REFERENCES [1] Y. Tamai et al., Ext. Abst. SSDM, pp. 1166-1167, 2008. [2] B. Chen et al., IEDM Tech. Dig., pp. 283-286, 2011. [3] K. Higuchi et al., IMW, pp.119–122, 2012. [4] Z. Fang et al., IRPS, pp. 964-965, 2010. [5] T.O. Iwasaki et al., Ext. Abst. SSDM, pp. 642-643, 2012. [6] B. Gao et al., IEDM Tech. Dig., pp. 417-420, 2011. [7] B. Gao et al., VLSI tech., pp. 30-31, 2009.

Fig. 1. ReRAM resistor element and measurement setup

Fig. 2. Set and reset pulse voltages and measured current waveforms.

Fig. 3. State diagram of device endurance test. Device is firstformed on P1, then accelerated endurance cycling w/o verificationon P2, followed by reset w/ verification on P3 and set w/verification on P4. P5 chooses initial conditions for next loop’siteration. Optimization of P3 and P5 is the focus of this work.

Fig. 4. Conventional pulse width (PW) and voltage conditions for each P2~P5. PW is modulated duringreset with verify P3, based on initial PW, Tini_reset. Voltage is modulated during set with verify P4, based oninitial voltage, Vini_set. P5 shows conventional logic to decide initial conditions for the next loop L+1. Indetail, W1, W2, W3 are 3 different conventional schemes to choose Tini_reset for P2 and P3. Similarly, V1,V2, V3 chooses Vini_set for P2 and P4 [3].

Fig. 5. AlxOy device endurance test results.Comparison of 10 devices average endurance, based on conventional P1~P5 [3].

Fig. 6. Comparison of initial reset pulse width Tini_reset increase through device lifetime, by using conventional P5 schemes.

Fig. 8. Proposed P5 method: adding decrease option for initial reset pulse width Tini_reset andinitial set voltage Vini_set.

Fig. 9. Comparison of conventional and proposed P3 method (in this example, Tini_reset=20ns at m=1).

Fig. 7(a). Conceptualcomparison betweenconventional and proposedscheme on changing Tini_reset.

Log

(Tin

i_re

set)

Write cycles

Faster

Conventional reset,monotonically increase

Proposed reset,increase and decrease

P2: 4000 set, reset cycles

w/o verification

P3: Reset w/ verification

P4: Set w/ verification

Device brokenIf set or reset

verification > 21 P1: Forming0 V3 V

Loop for endurance test

P5: Change initial reset pulse Tini_reset width and initial set voltage Vini_set

Fig. 7(b). Tini_reset.is increased and decreased due to filament status [4]. In long term Tini_reset is increased due to device wearing [2, 3].

FunctionGenerator

FunctionGeneratorParameterAnalyzer

Controller

Vcell

VgVsub

Resistor element

Oscilloscope (50Ω)

Top Electrode

Bottom Electrode

Switching Layer

(AlxOy)

50nm -4

-2

0

2

4

-150

-100

-50

0

50

100

150

0 50 100 150 200

Cur

rent

(µA

)

Time (ns)

Reset currentSet current

Voltage (V)Voltage (V)Voltage (V)Voltage (V)

Set current

Reset current

Set voltage

Reset voltage

Conventional P5 schemes on Tini_reset increase

0 0.5 1 1.5 2 2.5Write cycles (×106)

W1, V2

Initi

al re

set p

ulse

wid

th (

sec)

W3, V1

W3, V2

W2, V2

W2, V3

High endurance but slow

Fast but low endurance

10–6

10–5

10–4

10–7

10–8

0

200

400

600

800

1 2 3 4 5 6

Res

et p

ulse

wid

th (n

s)

Reset verification cycle m

Conv. reset pulse width increase in P3

Prop. reset pulse width increase in P3

Proposed reset (part 2) on P3, accelerate pulse width increase on reset w/ verification

Tini_reset + 40 × (m-1) (ns)

Tini_reset + 40 ×(m-1)! (ns)

Top electrode

Bottom electrode

Filamentstatus varies,Tini_reset increase and decrease

Barrier region wearing, Tini_resetincrease

W1 W2 W3

Ave

rage

end

uran

ce

(con

vent

iona

lsch

emes

)

SetReset

8×105

6×105

106

2×105

0

4×105

V3V2

V1

Vini_set+0.1V,

Vini_set+(n-1) ×0.1V,

Vini_set,

R<2×105 Ω, fail

Conventional P3: Reset with verification

Tini_reset

Reset success

Read at Vcell= 0.1V

Conventional P4: Set with verification

Tini_reset+ 40ns

Tini_reset+(m-1) ×40ns

Conventional P5: Change Tini_reset and Vini_set for next loop L+1, after reset w/ verification completes at trial m and set w/ verification completes at trial n

trial 1 trial 2 trial mtrial 1 trial 2 trial nR>5×104 Ω, fail

Set success

Reset W1

if m < 4

if m ≥ 4 Tini_reset + 40ns

Tini_reset + (m-1) × 40ns(increase)

(increase)

Tini_reset (no change)

Conventional reset scheme Tini_reset for next loop L+1

if n < 4

if n ≥ 4

Conventional set scheme Vini_set for next loop L+1

Tini_reset (no change)

Vini_set + 0.1V

Vini_set + (n-1) × 0.1V(increase)

(increase)

Vini_set (no change)

Vini_set (no change)

0 V

Initial reset pulse width: Tini_reset

Initial set voltage: Vini_set

Conventional P2: 4000 set and reset cycles

Reset W2

Reset W3

Set V1

Set V2

Set V3

Read at Vcell= 0.1V

100ns 100ns 100ns

–1.5V, –1.5V, –1.5V,

Tini_reset for next loop L+1

m (L–2) = 1,m (L–1) = 1,

and m (current L) = 1

reset success

Reset w/ verification succeeded at trial m

Tini_resetnot change

Proposed reset (part 1) on P5: Change Tini_reset for next loop L+1, after reset w/ verification completes at trial m

Tini_reset + 40nsincrease

Tini_reset

Tini_reset

next loop

next loopreset success

trial m=1reset success



Tini_reset – 40nsdecrease

Tini_resetno change

Tini_resetTini_reset

no change

Proposed set on P5: Change Vini_set for next loop L+1, after set w/ verification completes at trial n

n < 4 (current L)(except the

decrease case)

n ≥ 4 (current L) Vini_set + 0.1V

Vini_set – 0.1V

(no change)Vini_set

Condition of set w/ verification

Vini_reset for next loop L+1

set success

Set w/ verification succeeded at trial n

Vini_setnot change

Vini_set + 0.1VincreaseVini_set

next loop

next loopset success

set success set success set successVini_set – 0.1V

decreaseVini_set

no changeVini_set Vini_set

no change

Example on changing Vini_set for next loop L+1

Vini_set

trial 1 trial 2 trial n≥4

trial 1 trial 2 trial n<4

trial n=1 trial n=1 trial n=1

trial 1 trial 2 trial m≥4

trial 1 trial 2 trial m<4

Example on changing Tini_reset for next loop L+1

Tini_reset + 40ns(increase)

(decrease)

Tini_reset

Tini_reset – 40ns

Sam

e as

co

nven

tiona

l W

2 Sa

me

as

conv

entio

nal V

2 Ne

w

(no change)

Condition of reset w/ verification

New

(increase)

(decrease)

L–2 L–1 Current L L+1

Current L L+1

Current L L+1

L–2 L–1 Current L L+1

Current L L+1

Current L L+1

n (L–2) = 1,n (L–1) = 1,

and n (current L) = 1

m < 4 (current L)(except the

decrease case)

m ≥ 4 (current L)

Fig. 10. Definition of “total reset pulsewidth” and “reset time plus set time”.

Fig. 12. Comparison of total reset pulse width between conventional and proposed method. The best case device with the highest endurance within the 10 tested devices for each method was shown.

Fig. 11. Comparison of averagedendurance of 10 devices for eachcondition.

Fig. 13. Comparison of initial set voltage Vini_set between conventional and proposed set method, along with write cycling.

Fig. 14. Comparison of (a) Average total reset pulse width (b)Average reset time plus set time, on the device with highest endurancewithin 10 tested devices for each method.

Fig. 17. Comparison of average set energy. The proposed set methodincreases set energy. The explanation is shown in Fig. 18.

Fig. 19. Comparison of average write energy over 10 devicesfor each method.

Table 1. Comparison of conventional and proposed method on endurance, writetime and energy consumption by averaging over 10 devices. The value ofaverage total reset pulse width and average reset time plus set time are calculatedat the same method as average reset energy over 10 devices, as shown in Fig. 15.

∑ ∑ , ∑ ∑

/ 10/ 10

1

2

3

4

5

0 0.5 1 1.5 2 2.5

W2, V2Prop. reset, prop. set

Write cycles (×106)

Initi

al s

et v

olta

ge V

ini_

set (V

)

Fig. 16. Comparison of average reset energy. The conventional W2method keeps increasing initial reset pulse width Tini_reset, which causeshigher Ereset_avg_1_device for the devices with higher endurance.

_ _ _ _ _ _ _ _ _2

Fig. 15. Calculation of Ereset_avg_1_device, the average energy of reset w/verification, averaged over the cycles of one device. Ereset_avg_10_device is theaverage energy of reset w/ verification, averaged over 10 devices from j=1to j=10. is the energy of one reset w/ verification and i is the reset w/verification cycle count before write failure. The similar calculations wereused for calculating average set energy Eset_avg_1_device and Eset_avg_10_devices.

_ _ _

Fig. 18. The increase of average setenergy in Fig. 17(b) is due to theincrement of set verification trails,which is caused by decreased setvoltage on proposed set method.

_ _ _ ∑ ∑

/ /

Reset time plus set time

Time of reset w/ verification

Time of set w/ verification

1st pulse width

2nd pulse width

m thpulse width

trial m, reset successtrial 1 trial 2

+ + Total reset pulse width=

Read≈ 0.1µsRead ≈ 0.1µs

=+


P4: Set w/ verification


0

2

4

6

8

10

0

2

4

6

0 0.5 1 1.5

W2, V2W2, V3Prop. reset, V2Prop. reset, prop. set

Average endurance of 10 devices (×106)

Ave

rage

set

vol

tage

(V)

Average set verification trials

Set voltage decrease

Set verificationincrease

(a) Average set energy for each device

20

40

60

80

100

120

0 0.5 1 1.5 2 2.5


Larger set energy

Endurance, lifetime (×106)

E set

_avg

_1_d

evic

e(p

J)

(b) Average reset energy over 10 devices

0

20

40

60

80

100

120

0 0.2 0.4 0.6 0.8 1


Average endurance of10 devices (×106)

–28%

E res

et_a

vg_1

0_de

vice

s (p

J)

(b) Average set energy over 10 devices

0

20

40

60

80

100

120

0 0.2 0.4 0.6 0.8 1


Average endurance of 10 devices (×106)

Set energy increase

Not increase

×1.5E s

et_a

vg_1

0_de

vice

s (p

J)

0

20

40

60

80

100

0 0.2 0.4 0.6 0.8 1


Average Endurance of 10 devices(×106)

–17%

E writ

e_av

g_10

_dev

ices

(pJ

)

W2, V2Prop. reset, prop. set

0 0.5 1 1.5 2 2.5Tota

l res

et p

ulse

wid

th(s

ec)

Write cycles (×106)

10–6

10–5

10–4

10–7

10–8

(a) Average reset energy for each device

0

100

200

300

0 0.5 1 1.5 2 2.5


Endurance, lifetime (×106)

E res

et_a

vg_1

_dev

ice

(pJ)

Average endurance

Average total reset PW (µs)

Average reset time plus set

time (µs)

Ereset_avg_

10_devices (pJ)Eset_avg_

10_devices (pJ)Ewrite_avg_

10_devices (pJ)

Fig. 15 (b) Fig. 16 (c) Fig. 18

W2, V2 4.9×105 0.71 1.16 39.9 33.2 36.5

W2, V3 4.8×105 1.06 1.48 63 31 46.9

Prop. reset, V2 6.7×105 0.49 0.96 28.7 31.8 30.2

Prop. reset, prop. set 9.1×105 0.67 1.32 35.3 50.5 44.6

×1.4 –17% –17%×1.9 –28%

Ave

rage

en

dura

nce

5×105

106

0

Prop. reset = prop. P5 + prop. P3,Prop. P5 (decrement option of Tini_reset),Prop. P3 (accelerated PW increase on verification)

(b) Average reset time plus set time (P3 + P4)

0 0.5 1 1.5 2 2.5Write cycles (×106)


No significant degradation for the worn deviceA

vera

ge r

eset

tim

e pl

usse

t tim

e (s

ec)

10–7 No significant degradation for the worn device

10–6

10–5

10–4

10–7

10–8

(a) Average total reset pulse width in P3

0 0.5 1 1.5 2 2.5Write cycles (×106)


Conv. reset

Prop. reset

Ave

rage

tota

lres

et

puls

ew

idth

(sec

)

10–6

10–5

10–4

10–7

10–8

reram 3rd paper

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