Jason T. Stauth, Assistant Professor(jason.stauth@dartmouth.edu)

IEEE PowerSOC, October 5, 2016

Resonant & Multimode SC Converters:Power Management in the mm3 Regime

Outline

• High-density DC-DC conversion• Hybrid/Resonant Topology Overview• Generalized output impedance modelling for N:1

resonant topologies• Multimode operation• SC/ReSC power loss minimization & comparison• Example: 12V 3.7V Quasiresonant Series-

Parallel Converter• Conclusion

2

outsw

ppppout

sw

inpp

Cfi

v

LfVi

∆∝∆

∝∆

,

High Density DC-DC Converter:

3

Strategy 1: Increase frequency Smaller inductor, capacitor Increase in frequency dependent

losses (winding, core, gate drive etc.)

Strategy 2: Change Architecture Reduce inductor ΔV Multi-level or multi-stage converter Possible double efficiency penalty

Do Both?

−

→

−

→

FsA

HsV

IOUT

L Vout

iLS2

S1

Vin C IOUTC

L Vout

iLS2

S1

Vin

N:1

Key → Reduce passive component volume

Switched Capacitor Perspective

Only switches and capacitors Simple full integration in standard

CMOS

Capacitors have much higher energy density than inductors Stacked devices enable high

voltage with low voltage process Achieve higher device utilization

FOM1

Inherent charge sharing loss Difficult Regulation

Reconfigurable Architectures Lossy linear regulation

4

Spec

ific

Volu

me

(mm

3 / µJ

)

Specific Cost ($/ µJ)

Inductor

Capacitor

Accessing this energy density costs power

1[Seeman & Sanders, TPEL 2008]

+V1

-

+V2

-2

21 VCEloss ∆=

[Cooley & Leeb, APEC 2011]

Hybrid/Resonant SC Converters

5

CL

IL

VOUTSC Stage

e.g. FCML [1, 3], Series Parallel [2], Fibonacci, Dickson [3]

Leverage high active device utilization (same as SC) Soft charging or resonant energy

transfer (reduce charge sharing loss) Potential for higher utilization of

capacitor energy density (larger voltage swing allowed) SC front end lower V-s product shrink inductor dramatically Capability for Variable Regulation Multi-mode operation: high

efficiency across load range[1] Meynard PESC ‘92[2] Schaef APEC ‘17[3] Lei et al & PilawaAPEC ’16 & TPEL ‘15

(Concept can be generalized to many topologies)

[Kesarwani Compel ’15][Rentmeister ECCE ‘16]

Dickson ReSCSeries-Parallel ReSC

Examples

[Lei et al, COMPEL 2013]

COUT

VOUT

IDC

LX

SP

SP

SP

SP

SN

SN

SN

SN

Cx1CX2

VDD

CX3

i x

FCML/Meynard

CX1ix

SWCX2CX3

VDD

COUT

VOUTLX

IDC

S1

S2

S3

S4

S5

S6

S7

S8

Considerations: • Internal Charge Sharing• Voltage Balance on Capacitors = universal challenge• Startup, gate driving• Variable control & timing• Parasitics, ringing, etc.

[Kesarwani, COMPEL ‘15]Implementation is challenging, but performance is compelling

CX

1

S

P

S

COUT

VOUT

LX

CX

2C

X3

PP

S

S

PP

P

IDC

ix

VDD

VSW

VOUTix

CX1 CX2 CX3

State 1

VSW

VOUTVDD

VOUTix

CX1 CX2 CX3

State 2

VSW

6

Pilawa, Perreault (JSSC 2012)

Kim, Brooks, Wei(JSSC 2012)

FCML: Meynard ’92

Schaef, Stauth,(ISSCC 2015)

Lei, May, Pilawa(TPEL 2016)Pique, Alarcon

(PESC 2008)

Yousefzadeh, Alarcon, Maksimovic (TPEL 2006)

Examples: Past Work

7

(& others, e.g. Pilawa Little BoxAPEC ‘16)

Lx

iLx

C1C2CN-2S1

S1*

S2

S2*

SN-2

SN-2*

SN-1

SN-1*

Vout

Many other examples, esp FCML, 3-level:Reusch & Lee; Salem & Mercier; Shenoy et al;

General formulation: Step-Down Topologies SC = unregulated, arbitrary N:1 step down stage Inductive impedance shapes the current waveform Reff model: captures conduction loss & loadline

Generalized Output Impedance Modelling

8

Focus: Hybrid SC topologies that can be resonated with a single inductor (FCML, Series Parallel, Fibonacci)

+Vin-

+Vout

-

Reff

Iout

N:1

In Any Given Phase…

9

Vi VoutIi

RiCi

Vi VoutIi

RiCi L

𝐼𝐼𝑖𝑖 𝑡𝑡 = 𝑘𝑘𝑖𝑖𝑒𝑒−𝑡𝑡𝑅𝑅𝑖𝑖𝐶𝐶𝑖𝑖 𝐼𝐼𝑖𝑖 𝑡𝑡 = 𝑘𝑘𝑖𝑖𝑒𝑒

−𝑡𝑡𝑅𝑅𝑖𝑖2𝐿𝐿 sin 𝜔𝜔0𝑖𝑖𝑡𝑡

Key: 𝑞𝑞𝑖𝑖 = �0

𝑡𝑡𝑖𝑖𝐼𝐼𝑖𝑖 𝑑𝑑𝑡𝑡 𝐸𝐸𝑖𝑖 = �

0

𝑡𝑡𝑖𝑖𝑅𝑅𝑖𝑖𝐼𝐼𝑖𝑖2 𝑑𝑑𝑡𝑡

Charge Transferred: Energy Dissipated:

𝑡𝑡𝑖𝑖 =𝑇𝑇𝑠𝑠𝑠𝑠

2 =1

2𝑓𝑓𝑠𝑠𝑠𝑠

e.g. 2:1

)conditions initial(Fki =

Reff Model

10

𝑅𝑅𝑒𝑒𝑒𝑒𝑒𝑒 =𝑓𝑓𝑠𝑠𝑠𝑠 ∑𝐸𝐸𝑖𝑖𝑓𝑓𝑠𝑠𝑠𝑠 ∑𝑞𝑞𝑖𝑖 2

𝑃𝑃𝑙𝑙𝑙𝑙𝑠𝑠𝑠𝑠 = 𝑓𝑓𝑠𝑠𝑠𝑠�𝐸𝐸𝑖𝑖

𝑞𝑞𝑖𝑖 = 𝑎𝑎𝑖𝑖 𝑞𝑞𝑟𝑟𝑒𝑒𝑒𝑒Know proportionally how much charge flows out in each phase from topology

Same as aout element in:[Seeman & Sanders, TPEL ’08]

Cancels out in final calculation, sort of arbitrary

+Vin-

+Vout

-

Reff

Iout

𝑒𝑒.𝑔𝑔. : 𝑞𝑞𝑟𝑟𝑒𝑒𝑒𝑒= �𝑞𝑞𝑖𝑖

= 𝐼𝐼𝐷𝐷𝐶𝐶2 𝑅𝑅𝑒𝑒𝑒𝑒𝑒𝑒 = 𝑓𝑓𝑠𝑠𝑠𝑠�𝑞𝑞𝑖𝑖

2

𝑅𝑅𝑒𝑒𝑒𝑒𝑒𝑒

*optimized/normalized cap sizing/utilization*normalized Tsw/τ per phase

Results

11

Arbitrary SC Circuit

𝑅𝑅𝑒𝑒𝑒𝑒𝑒𝑒 =∑𝑎𝑎𝑖𝑖

2

𝐶𝐶𝑖𝑖coth 𝑡𝑡𝑖𝑖

2𝑅𝑅𝑖𝑖𝐶𝐶𝑖𝑖2𝑓𝑓𝑠𝑠𝑠𝑠 ∑𝑎𝑎𝑖𝑖 2

𝑅𝑅𝑆𝑆𝑆𝑆𝐿𝐿 =∑𝑎𝑎𝑖𝑖

2

𝐶𝐶𝑖𝑖2𝑓𝑓𝑠𝑠𝑠𝑠 ∑𝑎𝑎𝑖𝑖 2 𝑅𝑅𝐹𝐹𝑆𝑆𝐿𝐿 =

∑𝑎𝑎𝑖𝑖2𝑅𝑅𝑖𝑖𝑡𝑡𝑖𝑖

𝑓𝑓𝑠𝑠𝑠𝑠 ∑𝑎𝑎𝑖𝑖 2

𝑡𝑡𝑖𝑖 ≫ 2𝑅𝑅𝑖𝑖𝐶𝐶𝑖𝑖 𝑡𝑡𝑖𝑖 ≪ 2𝑅𝑅𝑖𝑖𝐶𝐶𝑖𝑖

𝑅𝑅𝑒𝑒𝑒𝑒𝑒𝑒,𝑅𝑅𝑒𝑒𝑆𝑆𝐶𝐶 =∑𝑎𝑎𝑖𝑖

2

𝐶𝐶𝑖𝑖tanh 𝑅𝑅𝑖𝑖

8𝐿𝐿𝑓𝑓0𝑖𝑖2𝑓𝑓𝑠𝑠𝑠𝑠 ∑𝑎𝑎𝑖𝑖 2

𝑅𝑅𝑒𝑒𝑒𝑒𝑒𝑒,𝑅𝑅𝑒𝑒𝑆𝑆𝐶𝐶 ≈∑ 𝜋𝜋𝑎𝑎𝑖𝑖24𝐶𝐶𝑖𝑖𝑄𝑄𝑖𝑖

2𝑓𝑓𝑠𝑠𝑠𝑠 ∑𝑎𝑎𝑖𝑖 2

Arbitrary ReSC Circuit

@ high Q

e.g. 2:1 ai = 1, Ci = C, Ri = R

𝑅𝑅𝑆𝑆𝑆𝑆𝐿𝐿 =1

4𝑓𝑓𝑠𝑠𝑠𝑠𝐶𝐶𝑅𝑅𝐹𝐹𝑆𝑆𝐿𝐿 = 𝑅𝑅

e.g. 2:1 ai = 1, Ci = C, Ri = R, Qi= (ωoRC)-1

𝑅𝑅𝑒𝑒𝑒𝑒𝑒𝑒,𝑅𝑅𝑒𝑒𝑆𝑆𝐶𝐶 ≈𝜋𝜋2

8𝑅𝑅

Note: Result is general • Works for arbitrary N-level SC/ReSC topologies where charge flow links the

output: SP, FCML, Fibonacci• Specific cases (Series parallel, FCML) worked out in: [Pasternak, Compel ‘16]

𝑅𝑅𝑅𝑅𝑒𝑒𝑆𝑆𝐶𝐶 =∑ 𝜋𝜋𝑎𝑎𝑖𝑖24𝐶𝐶𝑖𝑖𝑄𝑄𝑖𝑖

2𝑓𝑓𝑠𝑠𝑠𝑠 ∑𝑎𝑎𝑖𝑖 2𝑅𝑅𝑆𝑆𝑆𝑆𝐿𝐿 =∑𝑎𝑎𝑖𝑖

2

𝐶𝐶𝑖𝑖2𝑓𝑓𝑠𝑠𝑠𝑠 ∑𝑎𝑎𝑖𝑖 2

In SSL @ same frequency, Reff of resonant case is improved by a factor of ~ 𝝅𝝅𝟒𝟒𝑸𝑸𝒊𝒊

SC FSL/SSL boundary at 𝑡𝑡𝑖𝑖 = 2𝑅𝑅𝑖𝑖𝐶𝐶𝑖𝑖 For ReSC 𝑡𝑡𝑖𝑖 ≈ 𝜋𝜋 𝐿𝐿𝐶𝐶𝑖𝑖

@ inflection, resonant period is increased (frequency is reduced) by ~ 𝝅𝝅𝟐𝟐𝑸𝑸𝒊𝒊

Comparison(any arbitrary converter or phase)

• Fundamental resonant operation = primary case treated thus far

• @ high frequency CCM

• @ low frequency off-time modulation (DCM)

• Behavioral model can be used tocapture entire frequency range:

• α=9.2 (least squares analysis)

• Less than 2% error over entire range

ESRSW

EFF RffR α

απ

+≈ 0

2

81

DCM

Resonant

CCM

𝑅𝑅𝑒𝑒𝑒𝑒𝑒𝑒 =1

4𝐶𝐶𝑓𝑓𝑠𝑠𝑠𝑠

sinh 𝑅𝑅4𝐿𝐿𝑓𝑓𝑠𝑠𝑠𝑠

+ 𝑅𝑅4𝜋𝜋𝐿𝐿𝑓𝑓0

sin 𝜋𝜋𝑓𝑓0𝑓𝑓𝑠𝑠𝑠𝑠

cosh 𝑅𝑅4𝐿𝐿𝑓𝑓𝑠𝑠𝑠𝑠

− cos 𝜋𝜋𝑓𝑓0𝑓𝑓𝑠𝑠𝑠𝑠

Reff vs Frequency: Any Arbitrary Phase

13

Exact Expression –> 2:1 Converter:

~Q

~Q

Resonant operation indexes performance across all modes!

[Kesarwani, ISSCC ‘14]

[Pasternak, Compel ‘16]

Extended Multimode Operation

14

N:1SC

+

Vin

-

+Vsw-

+Vout

-

iL

Iout

L

Co

Variable regulation• Interpolate between levels:

• Depending on volt-seconds applied(frequency and Vsw-Vout)Inductor current waveform will appear:

111

−<<

−−

Nk

VV

Nk

in

outThis is a conceptual drawing, not schematically accurate

11 −<< Nkfor:

Nice way to accomplish multi-mode operation: Current Mode Control

N:1SC

+Vin-

iL

L

Co

Av

Ac

Gv

Gc

Syncronization, level shift, gate

drive

Vout

Iload

Cur

rent

Time

Ipeak

Ivalley

High-ish Load: CCM

Light-ish Load: DCM

Cur

rent

Time

Ipeak

Nice bonus: This scheme can ‘automatically’ balance flying capacitor voltages!

[Rentmeister ECCE ‘16]

SC Optimization

IDCV1

REFF2:1

PSW SWCONDLOSS PPP += SWGGEFFDC fERI += 2

Related to Rswitch, ↓ with ↑ size

Related to Cswitch, ↑ with ↑ size

16

=

RCfCfR

SWSWEFF 4

1coth4

1swspGGGG WEE ,4=

𝑅𝑅 =2𝑅𝑅𝑙𝑙𝑜𝑜,𝑠𝑠𝑠𝑠

𝑊𝑊𝑠𝑠𝑠𝑠

+= −

SPONXSWSPGGDC

DCSWSPONXopt

RCfEIIfRCW

,23

,2

1,

128tanh8

⇓

=∂∂ 0

sw

LOSS

WP

[Kesarwani, TPEL ’14]

This is true regardless of static loss, fixed resistance, bottom plate capacitance

C1

C2

M1

M2

M3

M4

VG

VG

VG’

VG’

RESR

CXIDC

Vout ix

VDD

SC Optimization

IDCV1

REFF2:1

PSW SWCONDLOSS PPP += SWGGEFFDC fERI += 2

17

)( swopt fFW =

0=∂∂

sw

LOSS

fP

3

,,2

2

, 128 SPONSPGGX

DCOPTSW REC

kIf = 𝑘𝑘 = 0.577

=+ −

kkk 1sinh

21 1

equation? ntal trancende⇒

3

,,2

2

, 1652.0SPONSPGGX

DCOPTSW REC

If = 3

,

22

4386.1SPGG

onspDCXopt E

RICW ⋅=

3,,3/4850966.2

X

SPONSPGGDCLOSS C

REIP ⋅⋅=

Device FOM

[Pasternak, Compel ’16]

Note: does not include bottom plate loss… lets discuss later!

ReSC Optimization

IDCV1

REFF2:1

PSW SWCONDLOSS PPP += SWGGEFFDC fERI += 2

18

sw

sponEFF W

RR ,

2 28π

=swspGGGG WEE ,4=

⇒=∂∂ 0

sw

LOSS

WP

spGG

spon

SWDCopt E

Rf

IW,

,14π

=

spGGsponSWDCMIN ERfIP ,,2π=

, =optSWf 0?

RESR

CX

IDC

Vout

ix

VDD

LX

CBP

CBP

VSW

M1

M2

M3

M4

S1*

S1

S2

S2*

• Says that ReSC (and other hybrids) get better with arbitrarily low frequency, independent of other factors…

• What is happening solution is choosing arbitrarily large, lossless inductor!

Device FOM

Btw: similar optimizations for N:1 topologies in Pasternak ‘16

Realistic Inductor Model

actAC

DCDC

fkR

QQ

RR

LL

0*

0*0

0,*0,

0*0

=

=

=

=

εε

ε

000

000,

00,

00

V,f @ Q base

V,f @ R base

Vfreq, low @ R base

V @ L base

=

=

=

=

Q

R

RL

AC

DC

000

000,

2 fkQ

LfRAC ==π

Neglects RDC other models possible

Dimensional Scaling:

x ε

x ε

x ε

Same turns ratio

ερ 1

∝Al

ε2NL ∝

Invariant RAC (const f0), larger L

Constant Volume Scaling of Inductance

00,

2

00,

2

2

LLRNR

LLRNR

NL

actACAC

actDCDC

=∝

=∝

∝

[Perreault et al and Sullivan APEC ‘09] 19

SC and ReSC Optimization

IDCV1

REFF2:1

PSW SWCONDLOSS PPP +=

Total Power Loss

ReSC is practical with mm-scale air-core inductors!Must achieve sufficient ‘Q’ to have an advantage

[Largely unpublished]

Pow

er L

oss (

norm

aliz

ed)

fsw/fFSL

Larger Smaller

Ideal inductor model

Real inductor models

Here:• Every point is optimal @ fsw• Fixed capacitance• Includes bottom plate loss

20

spGGsponSWMIN ERfP ,,∝

x ε

x ε

x ε

[Scaling Laws: Perreault et al and Sullivan, APEC ‘09]

Example: 12V 3.7V (LiIon) Quasiresonant Series Parallel

21

M1,2

M3

M4M5

M6M7

M8

Cin

startup control,pulse gen.

gate drivers

Details

22

• Regulation: 1-bit voltage-mode integral control with nested zero current detection

• Inductor = 33 nH (0402)• Flying Cap = 2 x 330 nF (0402)• Bypass Cap = (0201) input, (0402) output• Peak efficiency = 87% @ 4.6 W• Power density = 0.3 W/mm3 ≈ 5.0 kW/in3

(bounding box)

Current (A)

Conclusion

• Hybrid/Resonant SC topologies = great candidate high-density dc-dc converter

• Arbitrary N:1 converter output impedance a useful tool for analysis and comparison

• Quality Factor indexes performance in all modes, (without Q, you have nothing!)

• Multimode operation: great option for high efficiency across load range

• Any reasonable comparison must factor in the inductor: larger is better, but Q is the key driver

23

Thanks

24

This work was supported in part by NSF grants:ECCS 1309905, ECCS-1407725, ECCS 1554265 (CAREER)