KEERTI VYAS

CONTACT NO.: + 91 7891626211 EMAIL ID : kkvyas18@gmail.com

ADDRESS : "AXIS CITRINO"

Bommanahalli ,

kodichikkanahalli main road, off

Hosur Road , Bangalore-560068

OBJECTIVE:

I am looking forward for a good position, where I can exercise my knowledge and interpersonal skills and that

gives me an opportunity to learn new things and explore future career possibilities.

EXPERIENCE :

Experience of 2 years from 1st july 2013 to 31st july 2015 as Research Scholar in Geetanjali Institute of

technical studies , Dabok Udaipur, Rajasthan , India.

EDUCATIONAL QUALIFICATIONS: Completed M . Tech in VLSI Design from Geetanjali institute of technical studies(Rajasthan Technical University)

(2013-2015) and have 2 years experience as Research Scholar during M. Tech .

COMPUTER SKILLS:

Operating systems: Windows 2000/XP/2007/2008, Linux.

Languages: C, Java basics ,VHDL, MATLAB, C++, Verilog , System Verilog .

Software’s: MS Office (Word, Excel, Power Point), Xilinx, Tanner EDA, Lab view, Multisim.

PROJECTS:

1. DESIGNING OF COMPRESSOR USING MOS CURRENT MODE LOGIC(MCML) WITH A

CONCEPT OF SLEEP TRANSISTORS:

(M .TECH THESIS, RTU )

Brief Explanation:

In this research work we have designed compressor with sleep transistor at 16nm CMOS technology. A

compressor in its simpler form is a circuit that reduces three rows of partial products to two rows, hence its name

3-2 compressor. Several high order compressors, namely 4-2, 5-2 and 7-2 compressors have been designed in

Examination Specialization Year of Passing Board/University Percentage

M .Tech IV Sem. VLSI Design 2015 Rajasthan Technical University Thesis viva done

result pending.

Up to M .Tech III

Sem.

VLSI Design 2015 Rajasthan Technical University 71.9%

B .tech. Electronics and

Communication

Engineering(ECE)

2012 Rajasthan Technical University 78.05%

A.I.S.S.C. 2008 C.B.S.E 70.8%

S.S.C. 2006 C.B.S.E 62.6%

using MOS current mode logic in an effort to speed up compression operation, sleep transistor works to reduce

the leakage current and hence results in overall reduction in power consumption.

Platform: TANER EDA 14.1 v.

2. IMAGE COMPRESSION USING FACTORIAL FOURIER TRANSFORM.

(B .TECH PROJECT, RTU )

Brief Explanation:

In this project work , the FRFT, which is generalization of Fourier transform, is used to compress the image

with variation of its parameter ‘a’. It is found that by using FRFT, high visual quality decompressed image

can be achieved for same amount of compression as that for Fourier transform. By adjusting ‘a’ to different

values, FRFT can achieve low mean square error (MSE), better peak signal to noise ratio (PSNR), a high

compression ratio (CR), while preserving good fidelity of decompressed image. By varying ‘a’, it can

achieve high CR even for same cutoff. As cutoff increases, CR increases but image quality degrades since

there is tradeoff between image quality and CR. Platform: MATLAB

ACADMIC ACHIEVEMENTS:

GATE-2013 qualified.

Participated in AICTE recognized STC on VLSI through ICT design conducted by Electronics and

Communication Engineering Department from 10.03.2014 to 14.03.2014, NITTTR , Chandigarh.

Participated in AICTE recognized STC on Virtual Instrumentation through ICT conducted by

Electrical Engineering Department from 28.04.2014 to 02.05.2014, NITTTR, Chandigarh.

Participated in Texas Instruments India Analog Maker Competition 2014 in GITS, Udaipur.

PUBLICATIONS :

Keerti Vyas, Ginni Jain, Vijendra K. Maurya, A. Raman"Achieving low power by scaling frequency and

voltage" published in IJCA Proceedings for RAWCAI 2014 Edition .

Keerti Vyas, Ginni Jain, Vijendra K. Maurya, A. Raman'' Proposal of snubber circuit reduce problem of

collapsing in BJT due to overrating'' in proceedings of CICN 2015 conference, 2014.

Keerti Vyas, Ginni Jain, Vijendra K. Maurya, Rajeev Mathur "Illustrative comparison of MCML and

CMOS design techniques using Tanner EDA" published in IJCA, New York ,May2015.

Keerti Vyas, Ginni Jain, Vijendra K. Maurya, Anu Mehra " Comparative analysis of MCML compressor

architectures with and without concept of sleep transistor " will be published in Springer

proceedings(AISC) through ICT4SD conference, July 2015.

Keerti Vyas, Ginni Jain, Vijendra K. Maurya, Anu Mehra "Analysis of an efficient partial product

reduction technique" in proceedings of the international conference on green computing and internet of

things (ICGCIoT), October 2015.