rethinking chip stacking in high volume from chip- to … chip stacking in high volume from...
TRANSCRIPT
Rethinking Chip Stacking in High Volume from Chip-
to-Wafer, Via Last to Wafer Level Hybrid Bonding
Markus Wimplinger Corporate Technology Development & IP Director
Moving from Chip-to-Chip
Stacking to Wafer Level Hybrid
Bonding
Chip Stacking Today: State of the Art Technology
Source: www.edbpriser.dk
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Chip-to-Chip Stacking for 3D IC – State of the Art
Flip Chip
Bonder
Thin, Singulated
Chips
Temporary Bonding Process
Flow for preparation of thin
wafers / thin dies
Today‘s 3D Memory Stacking
SK Hynix Samsung
TSV Diameter 6µm 7.5µm
TSV Pitch 40µm 67µm
Micro-Bump 16µm 33µm
Aspect Ratio 7,8 6,7
3D Integration Options
Several different levels of 3D integation can be considered
from a chip architecture point of view
siz
e
Chip I/O
Global Wiring Level
Intermediate Wiring Level
Local Wiring Level
Transistor Level
3D-SIC
3D-SOC
3D-IC
Source: IMEC
3D Integration Options
Source: IMEC
Known Good Die
Stacking on
interposer or
base die
Wafer-to-Wafer Bonding is key process
Overlay defines integration density
Hybrid Bonding of 2 FEOL
metallization circuits
Combination of wafer-to-wafer
bonding and deposition
Comparison of different 3D integration schemes
Die Stack Wafer Stack Wafer Stack
(Hybrid)
Monolithic 3D
Interconnect TSV (Cu) + µPillar
/ C4
Bumpless Cu-TSV Bumpless Cu-TSV Inter Layer Via (W)
3D contact width > 20µm > 1µm for bulk Si
with via last
200nm to 1µm <100nm
Interconnect
Density
Low - Medium Medium High Ultimate
TSV Keep-out Large Small Very Small -
Bonding µPillar / C4 Oxide Hybrid Oxide
Yield High Requires architecture / circuit techniques
Hybrid Bonding: Alignment Requirements
For highest alignment tolerance, 80/20 oxide dominated hybrid bond
Source: Ziptronix
Fusion Bonding Alignment Contributors
SmartView alignment capability (W2W)
Function of the equipment
Wafer preparation, tooling and process
Function of wafer surface and processing
Function of pre-processing, preparation, activation,
fusion bonding, etc.
Function of whole MEOL metallization
Transition TX,TY
Rotation R
Max Error in fusion bonding
Etot = Ealignment + Escaling + Edistortion
Hybrid Bonding: Alignment Requirements
0%
20%
40%
60%
80%
100%
0 200 400 600 800 1000
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Overlay Accuracy (nm)
TSV 1µm Ø, 2µm pitch(ITRS target 2014)
TSV 800nm Ø, 1,6µm pitch(ITRS target 2018)
TSV 600nm Ø, 1,6µm pitch
SmartView®NT2
TSV pitch
TSV diameter
Today’s ITRS interconnect roadmap demands <400nm overlay alignment
Hybrid Bonding: Alignment Requirements
Source:
Highest alignment tolerance for hybrid bonding at 50% via
diameter of the pitch
EVG’s History in Fully-Automated Fusion Bonding
Gemini FB
First generation
2008
Gemini FB XT
SmartView NT2
Increased productivity
2014 Gemini FB
Modular HVM Tool Platform
2012
EVG850 LT
LowTemp® plasma bonding
2003
EVG®Gemini FB XT
3x improvement in
wafer-to-wafer alignment New SmartView®NT2
Better than 200nm (3σ) alignment
accuracy
50% increased throughput
Upgrade to six pre-processing modules
Faster handling and improved process
flows
Enabling new devices 3D stacked memory (high bandwidth
memory, etc.)
Next-generation stacked CMOS image
sensors
Monolithic device architecture
Building Blocks for Stacked Memory
Requirement of good electrical connectivity between top
and bottom tiers:
• No voids at the bonding interface and alignment accuracy
s Less than 200nm overlay Void-free Bonding
Building Blocks for Stacked Memory
3µm 6µm
Bo
nd
ing
Inte
rfa
ce
Courtesy of CEA Leti (Polis Project)
Courtesy of CEA Leti (Polis Project) Sony IMX260
Requirement of good electrical connectivity between top and bottom tiers:
• No voids at the bonding interface and alignment accuracy
• Good Surface Preparation for Cu grain growth
Application Examples for 3D Stacking
17
Application Example
Image Sensor (via last)
Image Sensor (3D
hybrid bonding)
Memory Stacking
Interposer
Sony IMX260 in
Samsung Galaxy S7
Omnivision PureCel Samsung ISO Cel Sony Exmor R
Xilinx FPGA AMD Fury
High Volume Manufacturing
Capable Integration Schemes for
Si-Photonics
Si-Photonics – Principle Structure
Full integration of
• Laser light sources
• Photo detectors
• Interconnect to electronics
and optical fibers
• Wave guiding and signal
modulation
Enabling technologies
• Heterogeneous integration of light
sources
• Guiding and modulation of light in
SOI substrates
• Low cost Assembly of optical
elements
Source Intel
Source Kotura
Photonic Integration
Source Aurrion CS International 2014
Si-Photonics Integration Scheme
+ sequential but fast integration process
+ high density of integration, collective processing
+ high quality epitaxial III-V layers
Drawback of wafer bonding:
InP substrates are relatively expensive and only a low filling factor needed
Source CEA LETI
Die Transfer Bonding
Dies
Compliant Layer
Handle Target Wafer
Pick and Place
Wafer-level bonding
Debonding
Chip-on-wafer bonding process shown by RWTH Aachen (http://www.isea.rwth-aachen.de/data/annualreports/2006/forschung12.pdf)
Processing of the
dies on compliant
layer is generally
possible
Direct Bonding Technology
Plasma activation crucial for this process
EVG810LT Critical stress for dislocation generation in InP
and thermal stress in InP-to-Si wafer bonding.
high surface energy and therefore good
bond strength is achieved by plasma
activation at low temperatures
Typical process flow for pasma activated direct bonding
Summary & Conclusions
Hybrid Bonding & Monolithic Integration High potential for stacking and integration of new
devices.
Maximum interconnection densities can be achieved
No loss of active silicon area by via processing
Plasma Activation Plasma activation modeling has been carried out
for highest bonding yield and minimized distortion
Alignment Control Several contributing errors have to be handled in
order to achieve high overlay
Alignment accuracy in fusion wafer bonding is a key for integration of new device designs
Novel, innovative process flows are required to enable cost-effective manufacturing of Si-Photonics devices. C2W transfer bonding using direct bonding enables integration of III-V materials with Si.
Thank you for your attention!
Please visit our booth #606 / 4F