Return Stack

Lecture 8.4

A VHDL Forth Core for FPGAs: Sect. 5

A 32 x 16 Stack

d(15:0) q(15:0)

clr

push

pop

clk

stack32x16 full

empty

Same as used in the Data Stack

A 32 x 16 Stack Module

d(15:0)

clk

clr

push

pop

full

empty

q(15:0)

we

wr_addr

rd_addr

stack_ctrl32wr2_addr

dpram32x16amsel

0

1

DINA (DI)

ADDRA (A)

CLKA (WR_CLK)

ADDRB (DPRA)

DOUTB (DPO)

WEA (WR_EN)

stack32x16

open(SPO)

The Return Stack

Stack32x16

R

Rmuxrsel

clrclk

rpush

rpop

clrclk

rload

rdec

R

R1

r_in

Rin(15:0)

ReturnStack

clrclk

rpush

rpop

rload

rdec

rsel

01

R(15:0)

full

empty

ReturnStack

RmuxPmux

PCclrclk

pload

pinc

IRclrclkirload

WC16C_control

plus1

R

Tin

Rin

R T

P

Pin

M

M P1

R

M

The WC16CWHYP Core

clkclr

rpop

rpush

psel rinsel

tsel(2:0)

rload

rdec

rsel

T

icode

B(1:4)DataStackclk

clr

dpop

dpush

ssel

nloadnsel

tload

0 11

1

0

0 2 3Tmux

y NN2E2E1S

S(1:8)

54 6 7

P(15:0)

M(15:0)

clr

clk

digloadT

Funit1

N2

y(15:0)

T(15:0)

Fcode(5:0)

N

ldload

The WC16CWHYP Core

FC16 Return Stack Instructions

Opcode Name Function 0030 >R “To-R” Pop T and push it on return stack 0031 R> “R-from” Pop return stack R and push it into T 0032 R@ “R-fetch” Copy R to T and push register stack 0033 R>DROP “R-from-drop” Pop return stack R and throw it away 0103 DRJNE Decrement R and jump if R is not zero 0104 CALL (:) Call subroutine (colon) 0105 RET (;) Subroutine return (semi-colon)

Tregclkclr

Nregclkclr

T1

Tin(15:0)

tload

nload

Nmux

Nin

T(15:0)

Smux

stack32x16

N1 T

N2

clkclr

dpop

dpush

empty

full

d

ssel

0

0

1

1

clkclr

dpop

dpush

ssel

nload

nsel(1:0)

tload

DataStack

y1(15:0)y1

2

N(15:0) N2(15:0)

nsel(1:0)

ReturnStack

RmuxPmux

PCclrclk

pload

pinc

IRclrclkirload

WC16C_control

plus1

R

Tin

Rin

R T

P

Pin

M

M P1

R

M

The WC16CWHYP Core

clkclr

rpop

rpush

psel rinsel

tsel(2:0)

rload

rdec

rsel

T

icode

B(1:4)DataStackclk

clr

dpop

dpush

ssel

nloadnsel

tload

0 11

1

0

0 2 3Tmux

y NN2E2E1S

S(1:8)

54 6 7

P(15:0)

M(15:0)

clr

clk

digloadT

Funit1

N2

y(15:0)

T(15:0)

Fcode(5:0)

N

ldload

when tor => tload <= '1'; nload <= '1'; tsel <= "111"; nsel <= "01"; dpop <= '1'; rload <= '1'; rpush <= '1'; rinsel <= '1';

“To-R” Pop T and push it on return stack.

>R

Tregclkclr

Nregclkclr

T1

Tin(15:0)

tload

nload

Nmux

Nin

T(15:0)

Smux

stack32x16

N1 T

N2

clkclr

dpop

dpush

empty

full

d

ssel

0

0

1

1

clkclr

dpop

dpush

ssel

nload

nsel(1:0)

tload

DataStack

y1(15:0)y1

2

N(15:0) N2(15:0)

nsel(1:0)

ReturnStack

RmuxPmux

PCclrclk

pload

pinc

IRclrclkirload

WC16C_control

plus1

R

Tin

Rin

R T

P

Pin

M

M P1

R

M

The WC16CWHYP Core

clkclr

rpop

rpush

psel rinsel

tsel(2:0)

rload

rdec

rsel

T

icode

B(1:4)DataStackclk

clr

dpop

dpush

ssel

nloadnsel

tload

0 11

1

0

0 2 3Tmux

y NN2E2E1S

S(1:8)

54 6 7

P(15:0)

M(15:0)

clr

clk

digloadT

Funit1

N2

y(15:0)

T(15:0)

Fcode(5:0)

N

ldload

“R-from” Pop return stack R and push it into T.

R> when rfrom => tload <= '1'; nload <= '1'; tsel <= "011"; dpush <= '1'; rsel <= '1'; rload <= '1'; rpop <= '1';

Tregclkclr

Nregclkclr

T1

Tin(15:0)

tload

nload

Nmux

Nin

T(15:0)

Smux

stack32x16

N1 T

N2

clkclr

dpop

dpush

empty

full

d

ssel

0

0

1

1

clkclr

dpop

dpush

ssel

nload

nsel(1:0)

tload

DataStack

y1(15:0)y1

2

N(15:0) N2(15:0)

nsel(1:0)

ReturnStack

RmuxPmux

PCclrclk

pload

pinc

IRclrclkirload

WC16C_control

plus1

R

Tin

Rin

R T

P

Pin

M

M P1

R

M

The WC16CWHYP Core

clkclr

rpop

rpush

psel rinsel

tsel(2:0)

rload

rdec

rsel

T

icode

B(1:4)DataStackclk

clr

dpop

dpush

ssel

nloadnsel

tload

0 11

1

0

0 2 3Tmux

y NN2E2E1S

S(1:8)

54 6 7

P(15:0)

M(15:0)

clr

clk

digloadT

Funit1

N2

y(15:0)

T(15:0)

Fcode(5:0)

N

ldload

“R-fetch” Copy R to T and push data stack

R@ when rfetch => tload <= '1'; nload <= '1'; tsel <= "011"; dpush <= '1';

Tregclkclr

Nregclkclr

T1

Tin(15:0)

tload

nload

Nmux

Nin

T(15:0)

Smux

stack32x16

N1 T

N2

clkclr

dpop

dpush

empty

full

d

ssel

0

0

1

1

clkclr

dpop

dpush

ssel

nload

nsel(1:0)

tload

DataStack

y1(15:0)y1

2

N(15:0) N2(15:0)

nsel(1:0)

ReturnStack

RmuxPmux

PCclrclk

pload

pinc

IRclrclkirload

WC16C_control

plus1

R

Tin

Rin

R T

P

Pin

M

M P1

R

M

The WC16CWHYP Core

clkclr

rpop

rpush

psel rinsel

tsel(2:0)

rload

rdec

rsel

T

icode

B(1:4)DataStackclk

clr

dpop

dpush

ssel

nloadnsel

tload

0 11

1

0

0 2 3Tmux

y NN2E2E1S

S(1:8)

54 6 7

P(15:0)

M(15:0)

clr

clk

digloadT

Funit1

N2

y(15:0)

T(15:0)

Fcode(5:0)

N

ldload

“R-from-drop” Pop return stack R and throw it away

R>DROP when rfromdrop => rsel <= '1'; rload <= '1'; rpop <= '1';

FC16 Return Stack Instructions

Opcode Name Function 0030 >R “To-R” Pop T and push it on return stack 0031 R> “R-from” Pop return stack R and push it into T 0032 R@ “R-fetch” Copy R to T and push register stack 0033 R>DROP “R-from-drop” Pop return stack R and throw it away 0103 DRJNE Decrement R and jump if R is not zero 0104 CALL (:) Call subroutine (colon) 0105 RET (;) Subroutine return (semi-colon)

>R

Decrement top of return stack and branch back to <WHYP statements> if not equal to zero.Therefore, <WHYP statements> are executedn times.

FOR…NEXT Loop

n FOR <WHYP statements> NEXT

drjne <WHYP statements>

ReturnStack

RmuxPmux

PCclrclk

pload

pinc

IRclrclkirload

WC16C_control

plus1

R

Tin

Rin

R T

P

Pin

M

M P1

R

M

The WC16CWHYP Core

clkclr

rpop

rpush

psel rinsel

tsel(2:0)

rload

rdec

rsel

T

icode

B(1:4)DataStackclk

clr

dpop

dpush

ssel

nloadnsel

tload

0 11

1

0

0 2 3Tmux

y NN2E2E1S

S(1:8)

54 6 7

P(15:0)

M(15:0)

clr

clk

digloadT

Funit1

N2

y(15:0)

T(15:0)

Fcode(5:0)

N

ldload

Decrement R and jump if R is not zero

DRJNE

when drjne => rdec <= not r1; pload <= not r1; psel <= '0'; pinc <= r1; rsel <= r1; rload <= r1; rpop <= r1;

-- r1 <= '1' if R-1 is all zeros r1 := '0'; for i in width-1 downto 1 loop r1 := r1 or R(i); end loop; r1 := (not r1) and R(0);

The Return Stack

Stack32x16

R

Rmuxrsel

clrclk

rpush

rpop

clrclk

rload

rdec

R

R1

r_in

Rin(15:0)

ReturnStack

clrclk

rpush

rpop

rload

rdec

rsel

01

R(15:0)

full

empty

ReturnStack

RmuxPmux

PCclrclk

pload

pinc

IRclrclkirload

WC16C_control

plus1

R

Tin

Rin

R T

P

Pin

M

M P1

R

M

The WC16CWHYP Core

clkclr

rpop

rpush

psel rinsel

tsel(2:0)

rload

rdec

rsel

T

icode

B(1:4)DataStackclk

clr

dpop

dpush

ssel

nloadnsel

tload

0 11

1

0

0 2 3Tmux

y NN2E2E1S

S(1:8)

54 6 7

P(15:0)

M(15:0)

clr

clk

digloadT

Funit1

N2

y(15:0)

T(15:0)

Fcode(5:0)

N

ldload

Call subroutine

Jump to address M andpush address of next instruction(P + 1) on return stack

CALL

when call => pload <= '1'; rload <= '1'; rpush <= '1';

call, X”1234”, --12 --14

In ROM:

ReturnStack

RmuxPmux

PCclrclk

pload

pinc

IRclrclkirload

WC16C_control

plus1

R

Tin

Rin

R T

P

Pin

M

M P1

R

M

The WC16CWHYP Core

clkclr

rpop

rpush

psel rinsel

tsel(2:0)

rload

rdec

rsel

T

icode

B(1:4)DataStackclk

clr

dpop

dpush

ssel

nloadnsel

tload

0 11

1

0

0 2 3Tmux

y NN2E2E1S

S(1:8)

54 6 7

P(15:0)

M(15:0)

clr

clk

digloadT

Funit1

N2

y(15:0)

T(15:0)

Fcode(5:0)

N

ldload

Subroutine return

Jump to address on top of thereturn stack, and pop thereturn stack

RET

when ret => psel <= '1'; pload <= '1'; rsel <= '1'; rload <= '1'; rpop <= '1';

\ led8.whpHEX : 1ms_Delay ( -- )

30D1 FOR NEXT ; : .5sec_Delay ( -- ) 1F4 FOR 1ms_Delay NEXT ; : MAIN ( -- ) BEGIN 8000 8 FOR DUP LD!

DUP DIG! .5sec_Delay 2/

NEXT 8 FOR U2/

DUP LD! DUP DIG! .5sec_Delay

NEXT DROP AGAIN ;

constant rom: rom_array := (JMP, --0X"0010", --1LIT, --2X"30D1", --3tor, --4drjne, --5X"0005", --6RET, --7LIT, --8X"03E8", --9tor, --aCALL, --bX"0002", --cdrjne, --dX"000b", --eRET, --fLIT, --10X"8000", --11LIT, --12X"0008", --13tor, --14

HEX

 

: 1ms_Delay ( -- )

30D1 FOR NEXT ;

 

: .5sec_Delay ( -- )

1F4 FOR 1ms_Delay NEXT ;

 

: MAIN ( -- )

BEGIN

8000

8 FOR

ROM Listing