reuse and ips - smartcomputerlab

Reuse and IPsReuse and IPs for electronic systemsfor electronic systems

P. BakowskiP. Bakowski

[email protected]@ieee.org

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ME2 – Reuse & IntegrationME2 – Reuse & Integration

This module introduces the concepts and the methods of This module introduces the concepts and the methods of usage for usage for virtual hardware reuse virtual hardware reuse and and integrationintegrationbased on HDLs:based on HDLs: VHDLVHDL and and Verilog Verilog

The module is built from 3 partsThe module is built from 3 parts

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The lecture (2*1.5h) part concentrates on the introduction The lecture (2*1.5h) part concentrates on the introduction of the notion of the of the notion of the Intellectual PropertyIntellectual Property and the and the Virtual Virtual CircuitsCircuits coded in HDLs on the examples based on VHDL coded in HDLs on the examples based on VHDL and Verilog languagesand Verilog languages

VHDL coding for reuse and integrationVHDL coding for reuse and integrationVerilog HDL coding for reuse and integrationVerilog HDL coding for reuse and integration

The building of The building of ARMARM processor and ARM based processor and ARM based SoCSoCs s are given as example of are given as example of RReuse & euse & IIntegration ntegration business business modelmodel

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The modeling/programming class (TP, 1*3h) consist in:The modeling/programming class (TP, 1*3h) consist in:

1. Transforming a Verilog/VHDL model of simple RAM 1. Transforming a Verilog/VHDL model of simple RAM into reusable component into reusable component

2. Preparing a generic decoder2. Preparing a generic decoder

3. Building a memory sub-system from the generic 3. Building a memory sub-system from the generic decoder and reusable RAM blocksdecoder and reusable RAM blocks

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At the end of this class you will be invited to consult the At the end of this class you will be invited to consult the choice of the microprocessor/microcontroller model to choice of the microprocessor/microcontroller model to use in your use in your mini-projects.mini-projects. Probably you will have to decide if you prefer VHDL or Probably you will have to decide if you prefer VHDL or Verilog language (note that quasi totality of the Verilog language (note that quasi totality of the professional – industrial models, icluding professional – industrial models, icluding ARM modelsARM models and and SoCSoCs, is coded in s, is coded in VerilogVerilog HDL) HDL)

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ME2 – Reuse & IntegrationME2 – Reuse & IntegrationThe mini-project (9 h ++) project focuses essentially on the The mini-project (9 h ++) project focuses essentially on the development of complete system integration a development of complete system integration a microprocessor microprocessor modelmodel (in VHDL or Verilog) and (in VHDL or Verilog) and RAM memory subsystemRAM memory subsystem and its and its simulation test with a simulation test with a few instructionsfew instructions in RAM memory. in RAM memory.

The initial choice of the microprocessor/micro-controller is narrowed The initial choice of the microprocessor/micro-controller is narrowed down to: AVR micro-controller (down to: AVR micro-controller (VHDLVHDL), a simple RISC processor (in ), a simple RISC processor (in VerilogVerilog), an ARM1 processor model (), an ARM1 processor model (VerilogVerilog) and an 8051 micro-) and an 8051 micro-controller (controller (VHDLVHDL).).However you are free to take and use any processor model available However you are free to take and use any processor model available in open source form (take a look at in open source form (take a look at opencores.orgopencores.org))

The The evaluationevaluation of the module is based on a short report (10 pages) of the module is based on a short report (10 pages) explaining the work you have done on the mini-project plus the explaining the work you have done on the mini-project plus the results of simulation.results of simulation.

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Why reuse ?Why reuse ?

1990 1995 2000 2005 2010 20151990 1995 2000 2005 2010 2015

top-down designtop-down design

integration based integration based designdesign

design complexitydesign complexity

1 mln 1 mln gatesgates

design gap design gap (75%)(75%)

productivity productivity (25%)(25%)

IP componentsIP components

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Virtual (IP) componentsVirtual (IP) components

New techniques facilitating the New techniques facilitating the researchresearch, , selectionselection, , adaptationadaptation, and , and integrationintegration of reusable components. of reusable components.

researchresearch

selectionselection

adaptationadaptation

integrationintegration

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The The effective reuseeffective reuse may begin at may begin at RTL levelRTL level with with soft soft componentscomponents and continue with progressive and continue with progressive implementation phases via implementation phases via firmfirm and and hard componentshard components. .

Soft : HDL codeSoft : HDL code

Firm: HDL netlistFirm: HDL netlist

Hard: Hard: GDSII mask layout file GDSII mask layout file

GDSIIGDSII Graphic Data System II Graphic Data System II - industry - industry de factode facto standard standard for IC layout data exchangefor IC layout data exchange

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System-on-ChipSystem-on-Chip ( (SoCSoC) architectures captured at RTL ) architectures captured at RTL level imply specific level imply specific communicationcommunication and and interconnectioninterconnection schemesschemes; they are difficult to accept the independently ; they are difficult to accept the independently designed components.designed components.

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Traditional “top-down” designTraditional “top-down” design

System level - algorithmSystem level - algorithm

Architectural level – RTLArchitectural level – RTL

Design from “scratch specifications”Design from “scratch specifications”

architectural architectural synthesissynthesis

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Logic levelLogic level


logic logic synthesissynthesis

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Mapping on FPGAs and ASICsMapping on FPGAs and ASICs


configuration/configuration/layout layout synthesissynthesis

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“ “top-down:outside-in” designtop-down:outside-in” design



Logic leveLogic levell

Design from high level specifications and Design from high level specifications and existing components existing components

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“ “top-down:outside-in” designtop-down:outside-in” design




Design from high level specifications and Design from high level specifications and existing components existing components

synthesized components/ synthesized components/ reusable componentsreusable components

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Evolutionary designEvolutionary design

evolving specificationsevolving specifications



previous previous generationgeneration

evolutionary timeevolutionary time

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synthesized components/ synthesized components/ reusable componentsreusable components



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modification/modification/extensionextension

next next generationgeneration



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Obstacles to systematic reuseObstacles to systematic reuse

component architectures are difficult to re-use component architectures are difficult to re-use and evolve and evolve

exploration of block alternatives is complex; exploration of block alternatives is complex; especially for programmable components especially for programmable components

verificationverification of complex system build from several of complex system build from several virtual circuits (VCs) will pose virtual circuits (VCs) will pose considerable considerable difficultiesdifficulties

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Solutions for systematic reuseSolutions for systematic reuse

the introduction of new design and/or development the introduction of new design and/or development level allowing to mix and match the VCs from different level allowing to mix and match the VCs from different sources - providing system reuse platform; this sources - providing system reuse platform; this platform may be referred to as domain engineering platform may be referred to as domain engineering

the introduction of the introduction of several degrees of variabilityseveral degrees of variability into into the future VCs allowing higher degree of the future VCs allowing higher degree of adaptabilityadaptability; ; this includes this includes parametrizationparametrization, , genericitygenericity and and configurabilityconfigurability

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the introduction of new design tools allowing rapid the introduction of new design tools allowing rapid retrievalretrieval, , selectionselection, , adaptationadaptation of the VCs of the VCs

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the introduction new the introduction new design languagesdesign languages and and processes based on processes based on constraint analysisconstraint analysis and evaluation and evaluation ((SystemVerilogSystemVerilog))

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expanding the design and development processes expanding the design and development processes on WEB-wide platform (on WEB-wide platform (collaborative toolscollaborative tools))

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Domain engineeringDomain engineering

Domain engineering makes the Domain engineering makes the abstraction from single abstraction from single design pathsdesign paths and tries to organize the and tries to organize the common featurescommon features of related design processes. of related design processes.

design pathsdesign paths common common featuresfeatures

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This requires a This requires a classification effortclassification effort concerning the concerning the potentially potentially available Virtual Componentsavailable Virtual Components. .

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The VCs may be classed into several categories: The VCs may be classed into several categories: memories, memories, control oriented processorscontrol oriented processors, , DSP-orientedDSP-oriented processors and blocks, custom function blocks (e.g. processors and blocks, custom function blocks (e.g. filters, GPUs, VPUs, ...), etc. filters, GPUs, VPUs, ...), etc.

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Domain engineering should also provide the techniques Domain engineering should also provide the techniques for the for the retrievalretrieval and and selectionselection of the appropriate blocks of the appropriate blocks for the construction of individual systems. for the construction of individual systems.

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The retrieval and selection processes will come with The retrieval and selection processes will come with librarieslibraries of VCs and of VCs and communication meanscommunication means to 3rd party to 3rd party providers. providers.

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The mechanisms to The mechanisms to importimport and and exportexport the components the components to/from the to/from the domaindomain will allow to make it will allow to make it evolvableevolvable..

importimport

exportexport

domaindomain

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Platform-based engineeringPlatform-based engineering

Platform-based engineeringPlatform-based engineering is focused on is focused on SSystem ystem oon n CChip integration. hip integration.

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Platform-based engineeringPlatform-based engineering

Integration starts with Integration starts with partitioning the systempartitioning the system around the around the existing standard blocks. existing standard blocks.

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Platform-based engineeringPlatform-based engineeringIt relies on standard bus architectures and It relies on standard bus architectures and standard standard interfacesinterfaces implemented in standard blocks. implemented in standard blocks.

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Reusable blocks engineeringReusable blocks engineering

The The reusable blocksreusable blocks (RTL modules) must offer a great (RTL modules) must offer a great deal of flexibility providing efficient deal of flexibility providing efficient adaptabilityadaptability..

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Reusable blocks engineeringReusable blocks engineeringThe reusable blocks (RTL modules) must offer a great The reusable blocks (RTL modules) must offer a great deal of flexibility providing efficient adaptability.deal of flexibility providing efficient adaptability.

Flexibility may be attained through:Flexibility may be attained through:

parametrization parametrization (Verilog)(Verilog)

Ncan – input Ncan – input signal sizesignal size

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parametrizationparametrization

genericitygenericity

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parametrizationparametrization

genericity genericity

configurabilityconfigurability

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Reuse and implementationReuse and implementation

The reuse engineering must be The reuse engineering must be technology independenttechnology independent ((soft/firmsoft/firm components) components)

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The The virtual systemsvirtual systems developed from developed from virtual virtual componentscomponents should evolve should evolve independentlyindependently from the from the underlying underlying implementation technologiesimplementation technologies. .

Partially truePartially true – see: TSMC - ARM holding – see: TSMC - ARM holding cooperationcooperation

April 2013: ARM and TSMC successfully tape out April 2013: ARM and TSMC successfully tape out the first the first Cortex-A57Cortex-A57 processor, using 16nm tech processor, using 16nm tech

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Reuse and implementation are related but Reuse and implementation are related but orthogonal activitiesorthogonal activities

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Reuse and implementation are related but Reuse and implementation are related but orthogonal activities orthogonal activities

The The reuse processesreuse processes operate over much longer operate over much longer time-scale than the implementation activities. time-scale than the implementation activities.


reuse processreuse process

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Reuse and implementation are related but Reuse and implementation are related but orthogonal activities orthogonal activities

The reuse processes operate over much longer The reuse processes operate over much longer time-scaletime-scale than the than the implementation activitiesimplementation activities. .


reuse processreuse process

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timetime

complexitycomplexity

technologytechnology

reusereuse

generationsgenerations

HDL code HDL code evolutionevolution

impl

emen

tatio

nim

plem

enta

tion

impl

emen

tatio

nim

plem

enta

tion

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technologytechnology

HDL HDL codecode evolutionevolution

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Logical and physical architectureLogical and physical architecture

Complex virtual components have two faces: Complex virtual components have two faces:

their functional or behavioral face and their functional or behavioral face and

the internal architecture providing the combined the internal architecture providing the combined functionalfunctional and and performanceperformance oriented features. oriented features.

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Some Some performanceperformance oriented features are completely oriented features are completely invisible from the outside interface. invisible from the outside interface.

outside interfaceoutside interface

performance performance architecturearchitecture

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The The logical architecturelogical architecture seen from outside is defined by seen from outside is defined by the list of the the list of the inputs and outputsinputs and outputs (structural aspect), the (structural aspect), the description of the performed operations, for instance description of the performed operations, for instance the the instruction set architectureinstruction set architecture (ISA) in case of (ISA) in case of processors), and the timing characteristics. processors), and the timing characteristics.

instruction set architecture (ISA)instruction set architecture (ISA)

inputs inputs and and outputsoutputs

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The The structural architecturestructural architecture describes the internal describes the internal structure and all internal operations providing the structure and all internal operations providing the external behavior with the external behavior with the implied performancesimplied performances. .


inputs inputs and and outputsoutputs performance performance

architecturearchitecture

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Note that more than Note that more than 80% 80% of theof the internal circuit internal circuit of of modern processors is developed to provide moremodern processors is developed to provide more performance (parallelism) performance (parallelism) and only and only 20% 20% is strictly is strictly necessary to provide thenecessary to provide the functionality functionality. .




functionality (~20%)functionality (~20%)

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The The evolutionevolution of the modern components is mainly of the modern components is mainly performance oriented. The great majority of the performance oriented. The great majority of the functionsfunctions are, and are, and must bemust be, , preservedpreserved..

instruction set architecture (instruction set architecture (ISAISA))



functionality (~20%)functionality (~20%)

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Intellectual Propriety (IPs)Intellectual Propriety (IPs)

Instead of re-designing every part of every chip, Instead of re-designing every part of every chip, re-usere-use existing designsexisting designs as much as possible and thus as much as possible and thus minimizeminimize the amount of the amount of new circuitrynew circuitry that must be that must be created from created from scratchscratch. .

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The most prevalent and promising method of re-use is The most prevalent and promising method of re-use is through through IP ComponentsIP Components - pre-implemented, re-usable - pre-implemented, re-usable modulesmodules that can - in theory - be quickly inserted and that can - in theory - be quickly inserted and verified to create verified to create a single-chip systema single-chip system. .

IP ComponentsIP Components

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Variously called:Variously called:

blocks, blocks,

cores, cores,

Virtual Components, Virtual Components,

IP Components, ..IP Components, ..

Intellectual propertyIntellectual property is an object or is an object or intangible itemintangible item - sound, - sound, picturepicture, combination of bits - whose major value comes , combination of bits - whose major value comes from the skill or from the skill or artistryartistry of its of its producerproducer..

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CopyrightCopyright may subsist in may subsist in creativecreative and artistic and artistic worksworks (e.g. books, movies, music, paintings, (e.g. books, movies, music, paintings, photographs, and photographs, and softwaresoftware) and give a ) and give a copyright holder the exclusive right to copyright holder the exclusive right to controlcontrol reproductionreproduction or adaptation of such works for a or adaptation of such works for a certain period of timecertain period of time

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PatentsPatents, can be granted for , can be granted for innovative circuit innovative circuit designsdesigns, but not for the HDL code or layout., but not for the HDL code or layout.

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The effort and skill that goes into creation of IPs is The effort and skill that goes into creation of IPs is of two basic types: of two basic types:

algorithmicalgorithmic + + architecturalarchitectural design , and design , and

physical designphysical design and optimization. and optimization.

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HDLs mature HDLs mature synthesis – synthesis – soft, firm IPssoft, firm IPs

FPGA, ASICFPGA, ASIC

hard IPshard IPs

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TypeType Design Design attributesattributes

Portable /Portable /modifiablemodifiable

Area,sped,Area,sped,powerpower

Integration Integration workwork

softsoft synthetisable synthetisable RTL – function RTL – function validatedvalidated

very /good very /good for FPGAfor FPGA

unpredictaunpredictableble

much workmuch work

Soft componentsSoft components have the architecture and algorithm have the architecture and algorithm specified in an specified in an RTLRTL (Register-Transfer Level) (Register-Transfer Level) codecode description that can be read by a description that can be read by a synthesis toolsynthesis tool, ,

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softsoft synthetisable synthetisable RTL – function RTL – function validatedvalidated



much workmuch work

firmfirm soft+netlist soft+netlist defineddefined

somewhatsomewhat somewhatsomewhat somesome

Firm componentsFirm components are are Soft ComponentSoft Component that have been transformed into that have been transformed into netlistnetlist of technological cells and synthesized into one or of technological cells and synthesized into one or more technologiesmore technologies to get performance, area, and power to get performance, area, and power estimatesestimates..

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softsoft synthetizable synthetizable RTL – function RTL – function validatedvalidated



Much workMuch work

firmfirm soft+netlist soft+netlist defineddefined

somewhatsomewhat somewhatsomewhat somesome

hardhard firm+physically firm+physically validatedvalidated

not not portableportable

completelycompletely littlelittle

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ARM holding – business modelARM holding – business model

ARM estimates that a major semiconductor company ARM estimates that a major semiconductor company would need to spend over would need to spend over $100 million every year$100 million every year to to develop their own architecture. develop their own architecture.

This represents more than This represents more than $20 billion of annual costs$20 billion of annual costs for for the industry. the industry.

By By designing oncedesigning once and and licensing many timeslicensing many times, ARM , ARM spreads the R&D costs over the whole industry, making spreads the R&D costs over the whole industry, making digital electronics affordable and therefore available to digital electronics affordable and therefore available to more and more people across the world.more and more people across the world.

REUSEREUSE

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ARM holding – business modelARM holding – business modelARM's ARM's licensing businesslicensing business started in the early 1990s with the started in the early 1990s with the development of our first development of our first processorprocessor. The processor is like the brain of . The processor is like the brain of the chip; it is where the software runs and it controls the functionality the chip; it is where the software runs and it controls the functionality of the product. of the product.

ARM designs each processor to be applicable to a broad range of end ARM designs each processor to be applicable to a broad range of end markets to maximise the number of Partners that can license each markets to maximise the number of Partners that can license each processor and to maximise the processor and to maximise the number of marketsnumber of markets in which the in which the Partner can deploy that technology.Partner can deploy that technology.

In most years ARM introduces 2–3 new processor designs. Over the In most years ARM introduces 2–3 new processor designs. Over the past ten years, ARM has developed other technologies suitable for past ten years, ARM has developed other technologies suitable for our licensing and royalty business model, such as graphics our licensing and royalty business model, such as graphics processors and physical IP components. Both of these technologies processors and physical IP components. Both of these technologies are now licensed widely and are generating royalty revenues.are now licensed widely and are generating royalty revenues.

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How the ARM business model works !How the ARM business model works !

ARM licenses technology designs to semiconductor ARM licenses technology designs to semiconductor companies. companies.

The licence fee is typically The licence fee is typically several million dollarsseveral million dollars, , dependent upon which technology has been licensed dependent upon which technology has been licensed and the type of licence. and the type of licence.

The semiconductor company will design and The semiconductor company will design and manufacture a chip utilising the ARM technology. manufacture a chip utilising the ARM technology.

The chip will then be incorporated into a digital The chip will then be incorporated into a digital electronic product, which is sold to the consumer.electronic product, which is sold to the consumer.

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IPs and licenses (ARM)IPs and licenses (ARM)

ARM company sells several kinds of IPs relative to ARM company sells several kinds of IPs relative to its microprocessor.its microprocessor.

There are:There are:

Implementation licenseImplementation license

Foundry licenseFoundry license

Design start licenseDesign start license

ArchitecturalArchitectural license license

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Implementation LicenseImplementation LicenseThe Implementation license is ARM's most popular The Implementation license is ARM's most popular licensing model and provides licensing model and provides complete information complete information toto design design andand manufacture integrated circuits manufacture integrated circuits containingcontaining anan ARM processor ARM processor. .

ARM processorARM processor

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Implementation LicenseImplementation LicenseImplementation licenses are ideal for semiconductor Implementation licenses are ideal for semiconductor vendors with design and manufacturing capability who vendors with design and manufacturing capability who plan plan to use ARMto use ARM processors processors in several productsin several products..

product 1 product 1 product 2 product 2

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Implementation LicenseImplementation License

ARM can provide either ARM can provide either hardhard or or soft coresoft core deliverablesdeliverables to suit individual Partner's design flows.to suit individual Partner's design flows.

hardhard softsoft

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IPs and licenses (ARM)IPs and licenses (ARM)Foundry LicenseFoundry License

The The ARM foundry programARM foundry program is an innovative model which is an innovative model which enables enables fablessfabless semiconductor vendors and OEMs to semiconductor vendors and OEMs to develop and sell develop and sell ARM processor-based productsARM processor-based products manufactured by manufactured by licensed foundrieslicensed foundries..

Example: TSMC (for ARM V8 – Example: TSMC (for ARM V8 – A51,53, ..) in 14nm (ThinFET)A51,53, ..) in 14nm (ThinFET)

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IPs and licenses (ARM)IPs and licenses (ARM)Foundry LicenseFoundry LicenseThe Program comprises two distinct licenses – The Program comprises two distinct licenses –

a a Design LicenseDesign License which is granted to the which is granted to the fabless fabless semiconductorsemiconductor vendorvendor or OEM and provides all the key or OEM and provides all the key elements and views needed to design an ARM-Powered elements and views needed to design an ARM-Powered system-on-chip, and system-on-chip, and

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IPs and licenses (ARM)IPs and licenses (ARM)Foundry LicenseFoundry LicenseThe Program comprises two distinct licenses – The Program comprises two distinct licenses –

a a Design LicenseDesign License which is granted to the which is granted to the fabless fabless semiconductorsemiconductor vendorvendor or OEM and provides all the key or OEM and provides all the key elements and views needed to design an ARM-Powered elements and views needed to design an ARM-Powered system-on-chip, andsystem-on-chip, and

a a Foundry LicenseFoundry License which is granted to the which is granted to the semiconductor foundry. semiconductor foundry.

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DesignStartDesignStartTMTM License LicenseThe DesignStart License enables the designer to The DesignStart License enables the designer to undertake the majority of their design activities, including undertake the majority of their design activities, including

place and route, place and route,

software development and software development and

design and design and

system verificationsystem verification, , prior toprior to obtaining a full ARM obtaining a full ARM Foundry Program License. Foundry Program License.

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IPs and licenses (ARM)IPs and licenses (ARM)Architecture LicenseArchitecture LicenseAn ARM architecture license enables the licensee to An ARM architecture license enables the licensee to develop their develop their own CPU implementationsown CPU implementations compliant with compliant with ARM's Instruction Set Architecture. ARM's Instruction Set Architecture.

The architecture licensee must have extensive design The architecture licensee must have extensive design resources and the highest level of implementation resources and the highest level of implementation expertise. ARM itself provides Cortex implementations.expertise. ARM itself provides Cortex implementations.

Apple : A3, A4, A5, A6, ..Apple : A3, A4, A5, A6, ..

Qualcom: SnapdragonQualcom: Snapdragon

Samsung: Samsung: Exynos 4, 5 ..Exynos 4, 5 ..

Nvidia : Tegra 2, 3, 4, K1 ..Nvidia : Tegra 2, 3, 4, K1 ..

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SummarySummary

traditional versus modern design path traditional versus modern design path

reuse and implementationreuse and implementation

intellectual proprietyintellectual propriety

role of standardsrole of standards

IP licenses and preparationIP licenses and preparation

ARM business modelARM business model

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ARM – SoC based projectsARM – SoC based projects

ARMv6ARMv6 - Broadcom2835: Raspberry-Pi and Odroid-W - Broadcom2835: Raspberry-Pi and Odroid-WARMv7ARMv7 Cortex-A8Cortex-A8: : Allwinner-A10Allwinner-A10: Cubieboard, Marsboard, PCduino,..: Cubieboard, Marsboard, PCduino,.. Cortex-A7Cortex-A7(*2): (*2): Allwinner-A20Allwinner-A20: Cubieboard, CubieTruck, Banana-Pi ,Marsboard, ..: Cubieboard, CubieTruck, Banana-Pi ,Marsboard, .. Cortex-A9(*4): Cortex-A9(*4): Exynos4412Exynos4412: Odroid-X2,Odroid-U2/U3, ..: Odroid-X2,Odroid-U2/U3, .. RK3128RK3128: Radxa-Rock, Rikomagic RK802IV, ..: Radxa-Rock, Rikomagic RK802IV, .. Cortex-A9Cortex-A9(*2)+Epiphany(*16) - Zynq7010:(*2)+Epiphany(*16) - Zynq7010: ParallellaParallella,..,.. Cortex-A15Cortex-A15(*4)+Cortex-A7(*4):(*4)+Cortex-A7(*4): Exynos5420Exynos5420: Odroid-XU: Odroid-XU Cortex-A15(*4)+CUDA(*192):Cortex-A15(*4)+CUDA(*192): Jetson-Nvidia Tegra K1Jetson-Nvidia Tegra K1,..,..

http://www.arm.com/products/processors/classic/arm11/

http://www.arm.com/products/processors/cortex-a/cortex-a8.php

http://linux-sunxi.org/A10


http://linux-sunxi.org/A20

http://en.wikipedia.org/wiki/Exynos

http://en.wikipedia.org/wiki/Rockchip


http://www.parallella.org/


http://en.wikipedia.org/wiki/Exynos

https://developer.nvidia.com/jetson-tk1

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ARM – SoC based projectsARM – SoC based projects

A few examples of projects: (1) Intelligent Personal Access Point (ipap) - Personal server: Odroid-X2,U3,.. (2) Intelligent Wearable Access Point (iwap) - Wearable server: Odroid-W,.. (3) OpenMPI cluster for audio streaming: 4*Cubieboard2,.. (4) OpenMPI cluster for video streaming: 4*Odroid-U3, .. (5) Embedded face detection and recognition: Odroid-U3, .. (6) Embedded real time body detection: Nvidia Tegra-K1, .. (7) 3D video streaming: Nvidia Tegra-K1,.. (8) Graphic game development with embedded openGL and hardware acceleration (ARM-Mali): Odroid-U3,.. (9) Multimedia standards and hardware accelerated codecs with GStreamer: Nvidia Tegra-K1,.. (10) Image processing with openCV and GPU acceleration: Nvidia Tegra-K1,.. (11) Embedded VoIP PABX: Odroid-U3,.. (12) Pocket speech (speech recognition) and control: Raspberry-Pi,Odroid-W, .. (13) Remote house control with SMS control messaging: SIM9000 micro-board + Raspberry-Pi or Odroid-U3,.. (14) House control - analog signals: Raspberry-Pi + Gertboard,.. (15) Intelligent embedded router: Odroid-U3,.. (16) Parallel processing with standard computer language - STDCL: Parallela (Epiphany 16-core processor),.. (17) Software Defined Radio - GNU openSDR: SDR kit + Odroid-U3 or Radxa Rock,.. (18) Real Time Embedded Linux-RK: Odroid-U3,..

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