review of digital logic design concepts. basic digital logic gates
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Review of Digital Logic Design Concepts
Basic Digital Logic Gates
Digital (Positive) Logic
• Logic Level High– 1 or ONE or HIGH or H or +Vdd or yes or ON or True
• Logic Level Low– 0 or ZERO or LOW or L or GND or no or OFF or False
0
1
Definitions
• Assert– A control signal is asserted when the action control
by the signal is being done.– Ex: Assume a control signal labeled en
• en is asserted when en is high
• Active low signal– A signal that is asserted when it is a logic level low.
• Active high signal – A signal that is asserted when it is a logic level high.
Buffer
A Y
0 0
1 1
SymbolEquation
Truth Table
Y AA Y
NOT (Inverter) GATE
A Y
0 1
1 0
SymbolEquation
Truth Table
A Y Y A
AND GATE
SymbolEquation
A B Y
0 0 0
0 1 0
1 0 0
1 1 1
Truth Table
Y ABAY
B
NAND GATE
SymbolEquation
Truth Table
AY
B Y AB
A B Y
0 0 1
0 1 1
1 0 1
1 1 0
OR GATE
Symbol Equation
Truth Table
AY
B Y A B
A B Y
0 0 0
0 1 1
1 0 1
1 1 1
NOR GATE
Symbol Equation
Truth Table
AY
B Y A B
A B Y
0 0 1
0 1 0
1 0 0
1 1 0
XOR GATE
Symbol Equation
Truth Table
AY
B Y A B
A B Y
0 0 0
0 1 1
1 0 1
1 1 0
XNOR GATE
Symbol Equation
Truth Table
A
YB
Equivalence Function
Y A B A B
A B Y
0 0 1
0 1 0
1 0 0
1 1 1
Digital Logic Types
• Combinatorial Logic Circuits– No Memory (or Registers)
• Sequential Logic Circuits– Memory (or Registers)
• Asynchronous Logic Circuits– No common clock
• Synchronous Logic Circuits– Common clock
Synchronous Sequential Circuits
Memory Storage Registers
Latches and Flip-Flops
D-Latch with (P)reset
D E Pre Rst Qn+1
d d 1 0 0
d d 0 1 1
d 0 1 1 Qn
0 1 1 1 0
1 1 1 1 1
Symbol
Equation (level clock) Truth Table
D
E
Pre
Rst
Q
QSET
CLR
D
E
Qn+1
1n n nQ EQ ED • When Pre/SET (Preset) is asserted, Q → 1 immediately.• When Rst/CLR (Reset) is asserted, Q → 0 immediately.• When neither SET nor CLR is asserted,
• Q → D (data) when E (enable) is asserted;• Maintains previous value otherwise.
d = “don’t care”
D Flip-Flop Positive Edge Triggered
Q
QSET
CLR
D Qn+1D
Clk
Pre
Rst
D Clk Pre Rst Qn+1
d d 1 0 0
d d 0 1 1
d 0 1 1 Qn
d 1 1 1 Qn
0 1 1 0
1 1 1 1
Symbol
Equation (rising clock)
Truth Table
1n nQ D • Q changes to D on rising edge of Clk
Finite State Machines
Finite State Machines (FSMs)
• Three basic types
1. Moore FSM2. Mealy FSM3. Mealy-Moore FSM
Moore FSM General Block Diagram
Input Vector Output Vector
NextState
PresentState
Feedback Path
CL= Combinational Logic Cloud
Reg= D Registers
Clock
Rese
t
REG
CL
F
CL
H Ypsns
X
clock
reset
Moore FSM State Equations
Input Vector Output Vector
NextState
PresentState
Feedback Path
Clock
Rese
t State Equations
,s s
s
n F X p
Y H p
REG
CL
F
CL
H Ypsns
X
clock
reset
Mealy FSM State Equations
Input Vector Output Vector
NextState
PresentState
Feedback Path
,
,
s s
s
n F X p
Y H X p
REG
CL
F
CL
H Ypsns
X
clock
reset
Mealy-Moore FSM State Equations
Input Vector
Next State Present State
Mealy Outputs
Moore Outputs 1 1 2 2
,
,
s s
s s
n F X p
Y H X p Y H p
REG
CL
F
CL
H1Y1
psnsX
clock
reset
Y2
CL
H2
State Diagrams
State Bubble
Name[Value]
Output
[Conditional]
State
(transition)
State Bubble Example
UnconditionalTransition
State name = S0State value = 00Y = 0 for this state
S000
Y=0
upn
upn
FSM Example
Example 2– 2-bit Up Counter
• State Diagram
Clock is implied
S0
s3
S2
S1
Reset
Y=0
Y=1
Y=2
Y=3
Example – 2-bit Up Counter
• State Table
ps ns y
S0 S1 0
S1 S2 1
S2 S3 2
S3 S0 3
S0 = 00
S1 = 01
S2 = 10
S3 = 11
Let
Let S0 = reset state
State Value Assignment
Output Vector
Example – 2-bit Up Counter
• Truth Table
ps1 ps0 ns1 ns0 y1 y0
0 0 0 1 0 0
0 1 1 0 0 1
1 0 1 1 1 0
1 1 0 0 1 1
Example – 2-bit Up Counter
• Excitation Equations
1 1 0
0 0
1 1
0 0
s s s
s s
s
s
n p p
n p
Y p
Y p
Recall Moore FSM
Input Vector Output Vector
NextState
PresentState
Feedback Path
Clock
Rese
t State Equations
,s s
s
n F X p
Y H p
REG
CL
F
CL
H Ypsns
X
clock
reset
Logic Diagram
F Logic
H Logic
Reg Block
Y Vector
No X Vector in this ExampleNo H Logic needed
2-bit Counter in 68HC11 Assembly
L0: LDAA #$00 ; Reset A with 0
L1: INCA ; A=A+1
CMPA #$03 ; Is A=3?
BNE L1 ; No. Increment A
JMP L0 ; Yes, Reset A to 0