review of state-of-the-art solutions for hil simulation of ... - review of state-of... ·...

2016-07-08

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Review of state-of-the-art solutions for HIL simulation of power systems, power electronics

and motor drives

Dr. Christian Dufour

EMR summer school 2016Montréal, Canada

©2016 Opal-RT Technologies, Inc.

1. Overview of real-time simulations

Purpose

Rapid Control prototyping

Hardware in-the-loop

2. CPU vs. FPGA simulation

3. CPU-based simulation examples

EMT (Electro-Magnetic Transient) mode

Phasor mode (transient stability)

4. FPGA-based simulation examples

Motor Drive

eHS (electric Hardware Solver)

MMC (Multi-level Modular Converter)

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Outline

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2. Digital simulators greatly ease and accelerate tests

Tests in the lab : safer testing

Good accuracy

Better test coverage

1. Sometimes difficult to test controllers and controlled systems

Safety issues

Technical feasibility

Cost

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Overview of real-time simulations

Purpose

• Sometime called V-cycle.

Model-based design and real-time simulators

Control Prototyping Hardware in-the-loop

Specification by models

Implementation

Calibration & release

Simulated controller

Simulated plant

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Purpose



2. Available Technologies: CPU vs. FPGA





Motor Drive



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Outline

CPU simulation FPGA simulation

Better algorithm flexibility (ex: switches) Lower sample time

Bigger systems Better event resolution

Ease of coding Lower I/O latency

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CPU vs. FPGA simulation

Respective advantages

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Purpose








Motor Drive



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Outline

Interpolated simulation of high-frequency PWM motor drives

Time-Stamped Bridge (TSB) : method using interpolated switching functions

PWM frequency : 10 kHZ

Simulator time step (10µs)

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CPU-based simulation examples

EMT (Electro-Magnetic Transient) for drives

Motor currents

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Bipolar HVDC system using ARTEMiS-SSN solver

SSN (State-Space-Nodal) is a nodal admittance-based solver built-in the ARTEMiS RT plug-in for SPS

Circuit : 2000 MW (500 kV, 2kA at each pole) HVDC link

Rectifiers and inverters : 12-pulse bipolar converters

Switched filter banks + capacitor banks for reactive power

Simulation at 49 µs time-step on 3 CPU cores @3.3 GHz

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EMT (Electro-Magnetic Transient) for grid systems

Large motor drive simulation using SSN

Validation of ACS6000 MV variable speed frequency converter (ABB)

Used to feed high power induction and synchronous motors

ARU (active rectifier unit) = transformer + 3-level NPC converter

Real-Time simulation @25 µs on 7 CPU cores

Circuit decoupling and parallel execution thanks to SSN

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EMT (Electro-Magnetic Transient) complex drives

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Focused on the power system stability using phasors

Transmission network modeled in the main frequency phasor domain

Dynamics of the system depend on rotating machines and control devices (excitation system, power system stabilizer, turbine, governor)

Sample time : a few milliseconds

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Phasor (transient stability) for super-large grid simulations

m1

m2

Main grid ref

m3

60 Hz

Network: IEEE 39 bus system scaled up 512 times

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Phasor (transient stability) for super-large grid simulations

Buses 5000 7000 20000

Generators 1280 1800 5120

Controllers 2304 3240 9216

Time to execute one model step

@ 10 ms2 ms 3 ms 8 ms

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Purpose





EMT mode (Electro-Magnetic Transient)



Motor Drive



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Outline

Designed to avoid long FPGA compilation times.

eHS: variable topology, variable parameter solver (no Place & Route->FAST)

eHS uses Fixed Admittance Matrix Nodal Method + Backward Euler method

Floating point arithmetic used (32 bits)

Time-step between 100 ns and 1 µs

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FPGA-based simulation examples

eFPGAsim suite and eHS (electric Hardware Solver)

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PMSM (Permanent Magnet Synchronous Machine) and boost converter

2 PMSM drives implemented using JMAG-RT Finite-Element Analysis Variable-DQ & Spatial Harmonic

Floating-point FPGA operators & interfaced with complex CPU models

Improved precision in transient states, full fault support

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Motor Drives (1)

PMSM (variable DQ model)

150 ns

PMSM (full FEA model)

450 ns

Boost converter 100 ns

IGBT inverter 150 ns

Switched Reluctance Motor and bidirectional boost DC-DC converter

Testing of modern hybrid electric vehicles (HEV)

Switching frequency : 50-100 kHz

Model connected to I/Os, ultra low latency

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Motor Drives (2)

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One of the main advantage of FPGA models is that the total I/O latency can be kept very low

1-2 µs max in current systems

Main part of this latency is due to 1 µs analog output converter

AO converter are asynchronous to the IGBT pulse, this results in the jitter below

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Ultra-low latency in FPGA models

SRM drive latency: from Digital Input to SRM voltage input ( left) and SRM current (right)

1 µs

Example

3-phase power source : 6.6 kV, 60Hz (simulated on CPU @20 µs)

Y/D transformer : 6.6 kV/440V, 60Hz (simulated on CPU @20 µs)

Six-pulse IGBT rectifier (discretized on FPGA @400 ns)

IGBT 3-level inverter (discretized on FPGA @690 ns)

PMSM motor model (JMAG-RT) (discretized on FPGA @100 ns)

PWM frequencies : inverter 8 kHZ, rectifier 4kHz

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Example

Motor currents (Phase A)

Red : SimPowerSystems offline simulation @500 ns

Blue : eHS simulation on FGPA

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Voltage inverters composed of hundreds of 2-IGBT-capacitor cells connected in series

Increased HIL performance when implemented in FPGA (remove latency of PCIe data link)

More than 400 cells per arm on FPGA (400 cells * 3 arms * 2 IGBTs per cell = 2400 IGBTs)

Medium-size MMC (100-150 cells per arm) can be simulated on CPU using SSN

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FPGA/CPU-based simulation examples


1 cell

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Many solver solutions exist for simulation of power systems, power electronics and motor drives

Based on CPU and FPGA

CPU : complex systems with advanced solvers (SSN), easier to code, bigger latency

FPGA : low latency (1 µs), lower sample time, better resolution, require customization of the solver

eFPGAsim’s eHS allows FPGA-HIL simulation without specific skills in FPGA programming

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Conclusion

review of state-of-the-art solutions for hil simulation of ... - review of state-of... ·...

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