revised syllabus microelectronics

8/12/2019 Revised Syllabus Microelectronics

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Master of Science-Technology in Microelectronics (Syllabus)

BoS-Dec-11 Page 1 of 19

Master of Science - Technology in Microelectronics

( For candidates admitted after April-2012 )Sl

No

Sub Code Sub Title Credits

Sem III

1 MEL651 Theory of MOS Devices 3-0-3-4

2 MEL653 Digital System Design Using HDL 3-0-3-4

3 MEL655 Process Technology 3-0-3-4

4 MEL657 Design of VLSI Systems 3-0-3-4

5 MEL659 CMOS Analog IC 3-0-3-4

6 MEL661 Elective-1

a. Nanotechnology

b. MEMS

c. EDA for IC Implementation

3-0-3-4

7 MEL613 Term Paper 1 1

Sem IV

8 MEL652 Synthesis and Optimisation of Digital Circuits 3-0-3-4

9 MEL654 Low Power VLSI 3-0-3-4

10 MEL656 Mixed IC 3-0-3-4

11 MEL658 High speed VLSI Design 3-0-3-4

12 MEL660 Testing of VLSI Circuits 3-0-3-4

13 MEL662 Elective 2

a. System on Chip

b. Optical IC

c. Design for Manufacturability and Yield Management

3-0-3-4

14 MEL614 Term paper 2 1


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MEL651 Theory of MOS Devices

3-0-3-4

Max Hrs: 36

UNIT I

Junction Field Effect Transistors :Introduction, Construction and operation, current voltage

characteristic equation, Secondary effects, Small-Signal equivalent circuit, Figure of merit of JFET,

High-frequency equivalent circuit of JFET, high frequency limitations.

Metal Semiconductor junctions and devices:Introduction ,Energy band diagrams of Metal and

N semiconductor before and after contact, Schottky barrier diode, Rectifying Metal-N

semiconductor junction, Rectifying Metal-P semiconductor junction, comparision of Schottky

barrier diode with PN diode.

UNIT II

MESFET:Fabrication and Modes of Operation, Threshold Voltage, I-V Characteristics of Depletion

and Enhancement devices, relations between the voltages .

Metal Oxide Silicon Systems:Introduction, Energy band diagrams, Band-bending and the effect

of bias voltages, Threshold Voltage, Oxide charges in MOS Capacitors.

UNIT III

MOS DEVICE PHYSICS: general considerations ,MOS IV characteristics, second order effects,

mos device models

UNIT IV

Metal Oxide Semiconductor FET:Introduction,Construction and basic operation, Fabrication of

N-type MOSFET (N-MOS) on an integrated circuit chip, Regions of operation: Cut-off, Linear, and

Saturation regions, current voltage analytical relations, types of MOSFETs, control of threshold

voltage, the MOSFET switch and CMOS Inverter, comparison between MOSFET & BJT

UNIT V

Small-Signal Models of the MOS: Trans conductance ,Intrinsic Gate-Source and Gate-Drain

Capacitance , Input Resistance, Output Resistance ,Basic Small-Signal Model of the MOS

Transistor, Body Trans conductance, Parasitic Elements in the Small-Signal Model , MOS

Transistor Frequency Response, Short-Channel Effects in MOS Transistors, Velocity Saturation

from the Horizontal Field, Trans conductance and Transition Frequency, Mobility Degradation from

theoretical Field, Weak Inversion in MOS Transistors, Drain Current in Weak Inversion, Trans

conductance and transitionFrequency in Weak Inversion , Substrate Current Flow in MOS

Transistors

Text Books:

1.microelectronic devices,deepank nagchoudary, Pearson Education, 2006.

2.Semiconductor Devices, Kanaan Kano, Pearson Education, 2001.


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References:

1.Physics of Semiconductor Devices, K. N. Bhat, Narosa Publications, 2004.2.Semiconductor Devices: Physics and Technology, S. M. Sze, Second Edition, Wiley India,

2008.

3. Analog circuit design by Razavi


4/19



MEL653 Digital System Design Using HDL

3-0-3-4

Max Hrs: 36

Digital Design using VHDL (or Verilog)

I. Introduction to Logic Circuits: Variables and Functions Inversion ,Truth Tables, Logic

Gates and Networks , Boolean Algebra, Sum-of-Products and Product-of-Sums

Forms, NAND and NOR Logic Networks,

II. Introduction to Verilog: Lexical conventions, data types, system tasks and

compilation, Modules and ports, Data-flow Modeling, Behavioral modeling

III. Optimization of Logic Functions: Karnaugh Map, Strategy for Minimization

Minimization of Product-of-Sums Forms, Incompletely Specified Functions Multiple-

Output Circuits, Multilevel Synthesis, Analysis of Multilevel Circuits, Cubical

Representation, Cubes and Hypercubes, A Tabular Method for Minimization.

IV. Number Representation and Arithmetic Circuits: Positional Number Representation ,

Addition of Unsigned Numbers, Signed Numbers, Fast Adders, Carry-Look ahead

Adder, Design of Arithmetic Circuits Using CAD Tools, Multiplication, Other number

representations. (special emphasis can be given to verilog programming)

V. Combinational Circuit Design: Multiplexers, Decoders, Encoders, Code Converters,

Arithmetic Comparison Circuits, Verilog for Combinational Circuits.

VI. Sequential Circuit Design: Basic Latch, Gated SR Latch, Master-Slave and Edge-

Triggered D Flip-Flops, T Flip-Flop, JK Flip-Flop, Summary of Terminology, Registers,

Counters, Reset Synchronization, Other Types of Counters, Using Storage Elements

with CAD Tools, Using Registers and Counters with CAD Tools, Design Examples.

References:

1. Fundamentals of Digital Logic with Verilog Design, Stephen Brown

and Vranesic, McGraw Hill Publications.

2. Verilog HDL, Samir Palnitkar, 2ndEdition, ISBN-10:0130449113,

Publisher: Prentice Hall Copyright: 2003


5/19



MEL655 Process Technology

3-0-3-4

Max Hrs: 36

Review of semiconductors:Introduction to ICs, Process and Product Trends, Increasing chip

and wafer size, Increasing chip and wafer size, Chip cost, Stages of manufacturing,

Crystal Growth & Wafer Preparation:Semiconductor materials preparation, Crystalline

Materials, Crystal orientation, Crystal Growth, Crystal & Wafer quality, Wafer preparation.

Wafer Fabrication:Wafer Terminology, Basic Wafer Operations, Wafer fabrication process

example, Wafer sort, Packaging.

Contamination Control:The problems (classes of contaminants), Contamination sources,

Clean air strategies, Clean room construction, Clean room maintenance.

CMOS process technology:Basic n-well/p-well process, Twin-tub process.

Process Yields:Yield measurement points, Wafer-Fabrication Yield Limiters, Wafer-sort

Yield limiters, Overall process yield.

Oxidation:Silicon oxide layer uses, Thermal Oxidation mechanisms, Rapid Thermal

Processing, Oxidant sources, Post oxidation evaluation.

Photolithography:Overview of the patterning process, Ten step patterning process, Basic

photoresist chemistry, Photoresist performance factors, photomasking process, Soft brake,

Alignment and expose, Photoresist development, Hard bake, Etching methods, Resist

stripping, OPC, Pellicles.

Doping: Formation of a Doped Region, Diffusion process steps, Ion implantation: concept,

system, Dopant concentration in implanted regions, Future of Doping.

Deposition:Introduction, Film Parameters, CVD basics, CVD process steps, CVD systems:

LPCVD, PECVD, Molecular beam epitaxy (MBE) systems

Metallization:Conductor metals, Deposition Methods, Vacuum evaporation method,

Sputtering.

Wafer fabrication costs, Chip packaging options, Chip characteristics, Package functions and

Design, Overview of packaging operations, Packaging processes, Package/Bare Die

Strategies, Package design.

References:1. Peter Van Zant, Microchip Fabrication, 3rdEdition, McGraw-Hill, International

Edition.

2. S.M. Sze, VLSI Technology, 2

nd

Edition, McGraw-Hill International Edition.


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MEL657 Design of VLSI Systems

3-0-3-4

Max Hrs: 36

Unit1: Text1 & Text2

Design Methodology: Y chart,Structured design techniques with examples, Programmable

logic, GA and SoG design, Cell-based design, Full custom design, SoC.

Design Flows: VLSI flow, Automated layout generation, Custom design flow, Programmed

behavioral synthesis.

Design Economics:Nonrecurring and recurring engineering Costs, Fixed Costs, Schedule,

Person power, Project management, Design Reuse. 9 Hours

Unit2: Text2

CMOS Logic Structureies:CMOS, BiCMOS, Pseudo-nMOS, Transmission gate, Dynamic,

Domino, Zipper, C2MOS, CVSL, SFPL logic.

Chip Design Methods: Behavioral synthesis, RTL synthesis, Logic optimization.

Design Capture Tools: HDL Design, Schematic Design, Layout Design, Floor planning and

Chip Composition.

Design Verification Tools: Simulation, Timing Verifiers, Network isomorphism, Netlist

comparison, Layout Extraction, Back-annotation, Design Rule Verification, Pattern

generation, EDA Tools for the System.

Control Unit Design: Finite State Machine Design procedure with example. 9 Hours

Unit3: Text1 & Text2

Datapath Sub-system Design: Introduction, Addition, Subtraction, One/Zero detectors,

Comparators, Counters, Shifters, Multiplication, Division, Parallel Prefix computations.

9 Hours

Unit4: Text1

Array Subsystem Design: SRAM, DRAM, Read only memory, Content Addressable

memory, Serial access memories, Programmable logic arrays.

Special Purpose Subsystems: Packaging, Power distribution, I/O, Clock. 9 Hours

REFERENCE BOOKS:

1. Niel Weste, David Harris, Ayan Banerjee, CMOS VLSI Design 3rdedidtion,Pearson education.

2. Niel Weste, Kamran Eshraghian, Principles of CMOS VLSI Design 2rdedidtion,

Pearson education.


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MEL659 CMOS Analog IC Design

3-0-3-4

Max Hrs: 36

Introduction and Background: MOS Device Basics, MOS Device Models, active RC Layout, Design

Rules. 3 hours

Single Stage Amplifiers: Common Source Amplifiers, Source Follower Common Gate, Cascode

Structures and Folded Cascode Structures. 4 hours

Current Mirrors: Simple Current Mirrors/Sources, Cascode Current Mirrors/Sources, Differential Pair

with Current Mirror Load. 3 hours

Differential Amplifier: Introduction to Differential Pair Amplifier, Quantitative Analysis to

Differential Pair Amplifier, Common Mode Response, Differential Amplifiers with Different Loads,

Effects of Mismatches. 4 hours

Operational Amplifiers: Op Amps Low Frequency Analysis, Telescopic Op Amps, Folded Cascode Op

Amps, Two Stage Op Amps, Common Mode Feedback. 4 hours

Frequency Response: Frequency Response of Common Source Amplifiers, Source Follower Common

Gate, Cascode Structures and Folded Cascode Structures, Differential Amplifiers, Single Ended

Differential Pair. 4 hours

Feedback: Voltage-Voltage, Current -Voltage, Voltage-Current &Current-Current Feedback

Loadingeffects. 3 hours

Frequency Compensation & Stability: Frequency Compensation Techniques in Telescopic Op Amps,

Folded Cascode Op Amps, Two Stage Op Amps. 4 hours

Operational Amplifier Applications: Filters, Applications, ADCS&DACS 3 hours

Text Book

1.Design of Analog CMOS Integrated Circuits, Behzad Razavi, McGraw-Hill, 2000.

References

2.Analysis and Design of Integrated Circuits, Paul R. Gray, Paul J. Hurst,

Stephen H. Lewis, Robert G. Meyer, 4th Ed., Wiley, 2001.

3.Phillip E. Allen and Douglas R. Holberg, CMOS Analog Circuit Design, 2nd

edition, OxfordUniversity Press, 2002

References

1.Operation and Modeling of the MOS Transistor, Y. Tsividis, McGraw-Hill,

2nd Edition, 1999.

2.Analog Integrated Circuit Design, D. Johns and K.Martin, Wiley, 1997.

3.The Designers Guide to SPICE & SPECTRE,K. S. Kundert, Kluwer Academic

Press, 1995


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MEL661.1 Nanotechnology

3-0-3-4

Max Hrs: 36

Electronic transport in 1,2 and 3 dimensions: Quantum confinement, energy subbands, quantum

wells, quantum wires, quantum dots. Effective mass, drude conduction and mean free path in

3D, ballistic conduction, phase coherence length, and quantized conductance in 1D.

Compound semiconductor nanostructures: growth of compound semiconductors, superlattices,

self-assembled quantum dots.

Nanoparticles, nanotubes and nanowires, fullerenes (buckyballs, grapheme

Molecular electronics: optoelectronic properties of molecular materials, nanotechnology, devices:

OLEDs, OTFTs.

Nanofabrication and nanopatterning: Optical, X-ray, and electron beam lithography, self-

assembled organic layers, scanning tunnelling microscopy, atomic force microscopy

References

1. Vladimir V. Mitin, Viatcheslav A. Kochelap, Michael A. Stroscio: Introduction to

Nanoelectronics: Science, Nanotechnology, Engineering, and Applications, Cambridge University

Press, 2008.

2. Rainer Waser: Nanoelectronics and Information Technology: Advanced Electronic Materials

and Novel Devices, Wiley-VCH, 2003.

3. Edward L. Wolf: Nanophysics and Nanotechnology: An Introduction to Modern Concepts in

Nanoscience, 2nd ed., Wiley-VCH, 2006.

4. John H. Davies: The Physics of Low Dimensional Semiconductors: An Introduction,

Cambridge University Press, 1998.


9/19



MEL661.2 MEMS

3-0-3-4

Max Hrs: 36

UNIT - 1

INTRODUCTION TO MICRO AND SMART SYSTEMS:

a) What are smart-material systems? Evolution of smart materials, structures and systems.

Components of a smart system. Application areas. Commercial products.

b) What are microsystems? Feynmans vision. Micromachined transducers.Evolution of micro-

manufacturing. Multi-disciplinary aspects. Applications areas. Commercial products.UNIT - 2

MICRO AND SMART DEVICES AND SYSTEMS: PRINCIPLES AND

MATERIALS:

a) Definitions and salient features of sensors, actuators, and systems.

b) Sensors: silicon capacitive accelerometer, piezo-resistive pressure sensor, blood analyzer,

conductometric gas sensor, fiber-optic gyroscope and surface-acoustic-wave based wireless strain

sensor.

c) Actuators: silicon micro-mirror arrays, piezo-electric based inkjet printhead, electrostatic comb-

drive and micromotor, magnetic micro relay, shapememory-alloy based actuator, electro-thermal

actuator.

4. d) Systems: micro gas turbine, portable clinical analyzer, active noise controlin a helicopter

cabin.

UNIT - 3

MICROMANUFACTURING AND MATERIAL PROCESSING:

a. Silicon wafer processing, lithography, thin-film deposition, etching (wetand dry), wafer-bonding,

and metallization.

b. Silicon micromachining: surface, bulk, moulding, bonding based process flows.

c. Thick-film processing:

d. Smart material processing:e. Processing of other materials: ceramics, polymers and metals

f. Emerging trends

UNIT - 4

MODELING:

a. Scaling issues.69

b. Elastic deformation and stress analysis of beams and plates. Residual stresses and stress

gradients. Thermal loading. Heat transfer issues. Basic fluids issues.


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c. Electrostatics. Coupled electromechanics. Electromagnetic actuation. Capillary electro-phoresis.

Piezoresistive modeling. Piezoelectric modeling. Magnetostrictive actuators.

UNIT - 5COMPUTER-AIDED SIMULATION AND DESIGN:

Background to the finite element element method. Coupled-domain simulations using Matlab.

Commercial software.

UNIT - 6

ELECTRONICS, CIRCUITS AND CONTROL:

Carrier concentrations, semiconductor diodes, transistors, MOSFET amplifiers, operational

amplifiers. Basic Op-Amp circuits. Charge-measuring circuits. Examples from microsystems. Transfer

function, state-space modeling, stability, PID controllers, and model order reduction. Examples

from smart systems and micromachined accelerometer or a thermal cycler. 8 Hours

UNIT - 7

INTEGRATION AND PACKAGING OF MICROELECTRO

MECHANICAL SYSTEMS:

Integration of microelectronics and micro devices at wafer and chip levels. Microelectronic

packaging: wire and ball bonding, flip-chip. Lowtemperature- cofired-ceramic (LTCC) multi-chip-

module technology. Microsystem packaging examples.

TEXT BOOKS

MEMS & Microsystems: Design and Manufacture, Tai-Ran Tsu,

REFERENCE BOOKS:

Analysis and Design Principles of MEMS Devices, Minhang Bao,Elsevier, Amsterdam, The Netherlands, ISBN 0-444-51616-6.

Design and Development Methodologies,

1.Smart Material Systemsand MEMS: V. Varadan, K. J. Vinoy, S. Gopalakrishnan, Wiley.

2.. MEMS- Nitaigour Premchand Mahalik, TMH 2007


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MEL661.3 EDA for IC Implementation

3-0-3-4

Max Hrs: 36

EDA for Digital IC

Design Flows: Introduction to Digital design flow, Integration, future scaling challenges

Basics of Synthesis: Definition of Synthesis, Behavioral and RTL synthesis

Equivalence checking: Equivalence checking problem, Boolean reasoning, Combinationalequivalence checking, sequential equivalence checking

Placement: Placement problem, Global placement and detailed placement

Static timing analysis: Representation, Gate-delay models, Timing analysis of combinational

and sequential circuits, statistical STA.

Routing: Routing, Types of Routers, Common routing algorithms

EDA for Analog and RF IC

Simulation of Analog and RF Circuits: Differential Algebraic equations for circuits, Device

models, basic circuit simulations, steady state analysis, multi time analysis, Noise in RF

design.

EDA for Physical Verification

Design Rule Checking: Geometrical algorithms for physical verification, Hierarchical data

structures, Time complexity of hierarchical Analysis, Connectivity models.

References: (As of now one text is prescribed, few Journal papers will be added further)

EDA for IC Implementation, Circuit Design and Process Technology, Edited by

Louis Scheffer, Cadence Design Systems San Jose, California, U.S.A. Luciano Lavagno,

Cadence Berkeley Laboratories, Berkeley, California, U.S.A., Grant Martin Tensilica

Santa Clara, California, U.S.A. CRC- Taylor and Francis.


12/19


13/19



MEL654 Low Power VLSI

3-0-3-4

Max Hrs: 36

Introduction top Low Power VLSI Design

Need for low power VLSI Design, Sources of power dissipation on Digital Integrated

circuits. Physics of power dissipation in CMOS devices. Emerging Low power approaches.

Section:I (Technology and Devices):

Dynamic dissipation in CMOS, Transistor sizing & gate oxide thickness, Impact oftechnology Scaling, Technology & Device innovation, evolution of deep sub-micron bulk and

SOI technologies, Leakage in CMOS nanometric technologies.

Section II (Low power Design Techniques):

Circuit level:Power consumption in circuits. Flip Flops & Latches design, high capacitance nodes, low

power digital cells library, low power very fast dynamic logic circuits, circuit techniques for dynamic

power reduction, circuit techniques for leakage reduction, Adiabatic and clock powered circuits.

Logic level:Gate reorganization, signal gating, logic encoding, state machine encoding, pre-

computation logic, Verilog/VHDL for low power.

System level:Power & performance management, switching activity reduction, parallel

architecture with voltage reduction, flow graph transformation, low power arithmetic

components, low power memory design.

Low power Clock Distribution: Power dissipation in clock distribution, single driver Vs

distributed buffers, Zero skew Vs tolerable skew, chip & package co design of clock network.

Section III (CAD tools for Low power):

Power estimation, Simulation Power analysis: SPICE circuit simulators, gate level logic

simulation, capacitive power estimation, static state power, gate level capacitance estimation,

architecture level analysis, data correlation analysis in DSP systems, Monte Carlo simulation.

Probabilistic power analysis:Random logic signals, probability & frequency, probabilistic

power analysis techniques, signal entropy. Synopsys tools for low power design, Magma

tools for low power design.

Text Books:

1. Gary K. Yeap, Practical Low Power Digital VLSI Design, KAP, 2002

2. Rabaey, Pedram, Low power design methodologies Kluwer Academic, 1997

3. Kaushik Roy, Sharat Prasad, Low-Power CMOS VLSI Circuit Design Wiley, 2000

4. Low power CMOS circuits, Logic design and CAD tool. Christian Piguet, CRC Press, Taylor and Francis, 2006.


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MEL656 Mixed IC

3-0-3-4

Max Hrs: 36

1.Introduction to Mixed signal Circuit Design: Challenges and opportunities Need for mixed signal circuitsand systems, software tools, industry trends, Research in mixed signal and Road Map.

2. Advanced Continuous Time Filter

3. Design of MOSFET-C Filter& Gm-C Filters

4 Sample and Holds, Voltage References and Translinear Circuits

5 Advanced switched capacitor circuitsIntroduction, general consideration, sampling switches - speed and precision consideration, switched capacitor

amplifiers, switched capacitor integrators and switched capacitor filters.

6.Data converters Fundamental: Introduction, basic building blocks, analog versus discrete time signal,

sample and hold characteristics, DAC & ADC specifications- Differential Non Linearity (DNL), Integral Non

Linearity (INL), offset error, gain error, latency, dynamic range, Signal to Noise Ratio (SNR), Spurious Free

Dynamic Range (SFDR) and Effective Number of Bits (ENOB).

7.DAC Design: Introduction, transistor level design of sub circuits for ADCs and architecture level design of

resistor string DAC, mismatch errors related to the resistor string DAC, R-2R DAC- current mode, Voltage

mode, current steering DAC, mismatch errors related to the current steering DAC, charge scaling DACs, cyclic

DAC and pipeline DAC.

8.ADC Design: Introduction, transistor level design of sub circuits for ADCs and architecture level design of

Flash ADC, two steps flash ADC, pipeline ADC, integrated ADC, accuracy issues, successive approximation

ADC and over sampling ADC.

9. Phase Locked Loop (PLL) Design: Introduction, building blocks, Phase Frequency Detector (PFD), chargepump, Voltage Controlled Oscillators (VCO), loop filter. Non ideal effects in PLL, frequency multiplication and

synthesizers

Books

1. R. Jacob Baker, CMOS: Circuit Design, Layout and Simulation , 3rd

edition Wiley-IEEE, 2010

2. R. Jacob Baker, CMOS:Mixed Signal Circuit Design, Wiley-IEEE, 20023. Phillip E. Allen and Douglas R. Holberg, CMOS Analog Circuit Design, 2

nd

edition, Oxford University Press,

2002

4. David Johns and Ken Martin,Analog Integrated Circuit Design, Wiley- India, 2008.

ReferencesR. Jacob Baker:CMOS Mixed Signal Circuits Design, Weslly-IEEE 2002R. Gregorian and Ternes:Analog MOS integrated circuits for signal processing, JosseyBass, 1986.

R.Gregorian:Introduction to CMOS OP-AMPs and comparators, John-Wiley, 1999.D.Johns and K.Martin:Analog integrated circuit design, John-Wiley, 1997.

Monolithic Phase-locked loops and clock recovery circuits: Theory and design, IEEE Press,

1996


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MEL658 High speed VLSI Design

3-0-3-4

Max Hrs: 36

Introduction to High Speed Digital Design: Frequency, time and distance, Capacitance and

Inductance Effects High speed properties of logical gates, Speed and power, modeling of wires,

Geometry and Electrical properties of wires, Electrical model of wires, transmission lines, lossless LC

transmission lines, lossy RLC transmission lines Special transmission lines, signal propagation on

interconnects in DSM .

Power Distribution and Noise: Power supply network, Local power regulation, IR drops, Area

Bonding, On chip bypass capacitors, Symbiotic bypass capacitors, Power supply isolation Noise

sources in digital system, Power supply Noise, Ground bounce, Cross talk, near end and far end cross

talk, Inter-symbol interference., managing noise in digital systems

Signaling convention and Circuits:, Signaling modes for transmission lines, Signaling over lumped

transmission media, Signaling over RC interconnects, driving lossy LC lines, simultaneous

Bidirectional Signaling, terminators in transmitter and receiver circuits.

Timing Convention and Synchronization:, Timing fundamentals, Timing properties of clocked storageelements, signals and events, open loop Timing , level sensitive clocking, pipeline Timing , closed

loop Timing clock Distribution, Synchronization failure and meta stability, PLL and DLL based lock

aligners.

Pseudo-MOS logic, Pass transistors, Transmission gates, Dynamic and domino logic, single rail and

dual rail designs, MODL. NORA and ZIPPER logic, Flip Flop and Latch structures, TSPC and CCMOS

latches.

TEXT BOOKS

1. Digital System Engineering, William S.Dally & John W. Paulton, Cambridge University Press,1998.2. High Speed Digital Circuits, Masakazu Shoji.,Addison Wesley Publishing Company, 1996

REFERENCES

1. Digital Integrated Circuits: A design Perspective, Jan M.Rabaey et al;2nd Edition 2003

2. Basic VLSI Design, Douglas A.Pucknell & Kamran Eshraghian, Prentice Hall,1994.

3. Design for Test for Digital ICs & Embedded core Systems, Alfred L Crouch; Prentice Hall.

4. High Speed Digital Design-A Hand book of Black Magic, Howard Johnson & Martin Graham,

Prentice Hall PTR,1993.


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MEL660 Testing of VLSI Circuits

3-0-3-4

Max Hrs: 36

Unit 1: 6 Hours

Introduction to Testing:

Introduction, Test economics and product quality, Fault modeling. 6 Hours

Unit 2: 18 Hours

Test Methods:

Logic and fault simulation, Testability measures. 6 Hours

Combinational circuit test generation, Sequential circuit test generation 6 Hours

Delay test, IDDQ test. 6 Hours

Unit 3: 12 Hours

Design for Testability:

Digital DFT and scan design. 3 Hours

Built-in self test. 6 Hours

Boundary scan 3 Hours

Reference:

1. M. L. Bushnell and V. D. Agrawal, Essentials for Testing of Digital, Memory and Mixed-Signal

VLSI Circuits, Springer, 2000.


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MEL662.3 System on Chip

3-0-3-4

Max Hrs: 36

System On Chip Design Process: A canonical SoC Design, SoC Design flow, waterfall vs spiral, top-

down vs Bottom up. Specification requirement, Types of Specification , System Design process,

System level design issues Soft IP Vs Hard IP, Design for timing closure, Logic design issues,

Verification strategy, On-chip buses and interfaces, Low Power, Manufacturing test strategies.

Macro Design Process: Top level Macro Design, Macro Integration, Soft Macro productization,Developing hard macros, Design issues for hard macros, Design ,System Integration with reusable

macros., design examples

SoC Verification:, Verification technology options, Verification methodology, Verification languages,

Verification approaches, and Verification plans. System level verification, Block level verification,

Hardware/software co-verification and Static net list verification.

Design of Communication Architectures for SoCs: On chip communication architectures, System level

analysis for designing communication, Design space exploration, Adaptive communication

architectures, Communication architecture tuners, Communication architectures for energy/battery

efficient systems. Introduction to NOCs

MPSoCs:-What, Why and How of MPSoCs, Techniques for designing MPSoCs, Performance and

flexibility for MPSoCs design, MPSoCs performance modeling and analysis. System In Package (SIP)

design.

TEXT BOOKS

1. SoC VerificationMethodology and Techniques,Prakash Rashinkar Peter Paterson and Leena

Singh .Kluwer Academic Publishers,2001.

2. Reuse Methodology manual for SystemOnAChip Designs,Michael Keating, Pierre Bricaud,Kluwer Academic Publishers, second edition,2001.

REFERENCES

1.Design Verification: Simulation and Formal Method based Approaches, William K. Lam, Prentice

Hall.

2. System on a Chip Design and Test, Rochit Rajsuman

3. Multiprocessor Systems on chips, A.A.Jerraya, W.Wolf, M K Publishers.

4. The EDA HandBook, Dirk Jansen, Kluwer Academic Publishers.


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MEL662.3 Optical IC

3-0-3-4

Max Hrs: 36


19/19



MEL662.3 Design for Manufacturability and Yield Management

3-0-3-4

Max Hrs: 36

1. Design for Manufacturability of VLSI Course Objective

The course objectives are to give comprehensive coverage of the process and design

variables that determine the ease and feasibility of fabrication (or manufacturability)

of contemporary VLSI systems and circuits. This course progresses from

semiconductor processing to electrical design to system architecture. The materialprovides a theoretical background as well as case studies, examining the entire

design for the manufacturing path from circuit to silicon. Each chapter includes

tutorial and practical applications coverage.

Course Outline

I. Introduction

II. Defect Monitoring and Characterization

III. Digital CMOS Fault Modeling and Inductive Fault Analysis

IV. Functional Yield Modeling

V. Critical Area and Fault Probability Prediction

VI. Statistical Methods of Parametric Yield and Quality EnhancementVII. Architectural Fault Tolerance

VIII. Design for Test and Manufacturability

IX. Testing Solutions for MCM Manufacturing

Books for Design for manufacturability & Yield management

1.Integrated Circuit Manufacturability: byJose Pineda de Gyvez,IEEE Circuits and

Systems Society

2. Crouch, Alfred

Design-for-Test for Digital ICs and Embedded Core Systems

Prentice Hall PTR- Jun, 1995

3. Design for Manufacturability and Statistical Design: A Constructive Approach, Michael Orshansky,

Sani Nassif, Duane Boning, 2008, ISBN# 978-0-387-30928-6, Publisher: Springer
http://void%280%29/http://void%280%29/http://www.amazon.com/s/ref=rdr_ext_aut?_encoding=UTF8&index=books&field-author=Jose%20Pineda%20de%20Gyvezhttp://www.amazon.com/s/ref=rdr_ext_aut?_encoding=UTF8&index=books&field-author=Jose%20Pineda%20de%20Gyvezhttp://www.amazon.com/s/ref=rdr_ext_aut?_encoding=UTF8&index=books&field-author=Jose%20Pineda%20de%20Gyvezhttp://www.amazon.com/s/ref=rdr_ext_aut?_encoding=UTF8&index=books&field-author=IEEE%20Circuits%20and%20Systems%20Societyhttp://www.amazon.com/s/ref=rdr_ext_aut?_encoding=UTF8&index=books&field-author=IEEE%20Circuits%20and%20Systems%20Societyhttp://www.amazon.com/s/ref=rdr_ext_aut?_encoding=UTF8&index=books&field-author=IEEE%20Circuits%20and%20Systems%20Societyhttp://www.amazon.com/s/ref=rdr_ext_aut?_encoding=UTF8&index=books&field-author=IEEE%20Circuits%20and%20Systems%20Societyhttp://www.amazon.com/exec/obidos/ASIN/0130848271/dftdigest-20/http://www.amazon.com/exec/obidos/ASIN/0130848271/dftdigest-20/http://www.amazon.com/exec/obidos/ASIN/0130848271/dftdigest-20/http://www.amazon.com/exec/obidos/ASIN/0130848271/dftdigest-20/http://www.amazon.com/s/ref=rdr_ext_aut?_encoding=UTF8&index=books&field-author=IEEE%20Circuits%20and%20Systems%20Societyhttp://www.amazon.com/s/ref=rdr_ext_aut?_encoding=UTF8&index=books&field-author=IEEE%20Circuits%20and%20Systems%20Societyhttp://www.amazon.com/s/ref=rdr_ext_aut?_encoding=UTF8&index=books&field-author=Jose%20Pineda%20de%20Gyvezhttp://void%280%29/

revised syllabus microelectronics

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