rf and baseband techniques for software defined radio

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RF and Baseband Techniquesfor Software Defined Radio

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RF and Baseband Techniquesfor Software Defined Radio

Peter B. Kenington

a r t e c h h o u s e . c o m

Library of Congress Cataloging-in-Publication DataKenington, Peter B.RF and baseband techniques for software defined radio/Peter B. Kenington.p. cm.—(Artech House mobile communications series)Includes bibliographical references and index.ISBN 1-58053-793-6 (alk. paper)1. Software radio. I. Title. II. Series.

TK5103.4875.K46 2005621.3845—dc22 2005045271

British Library Cataloguing in Publication DataKenington, Peter B.RF and baseband techniques for software defined radio—(Artech House mobilecommunications series)1. Software radio 2. Radio circuits—DesignI. Title621.3’8412

ISBN-10: 1-58053-793-6

Cover design by Yekaterina Ratner

© 2005 ARTECH HOUSE, INC.685 Canton StreetNorwood, MA 02062All rights reserved.

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International Standard Book Number: 1-58053-793-6

10 9 8 7 6 5 4 3 2 1

Contents

Preface xi

Scope of This Book xiOrganisation of the Text xi

Acknowledgements xiii

CHAPTER 1Introduction 1

1.1 What Is a Software-Defined Radio? 11.2 The Requirement for Software-Defined Radio 2

1.2.1 Introduction 21.2.2 Legacy Systems 2

1.3 The Benefits of Multi-standard Terminals 31.3.1 Economies of Scale 41.3.2 Global Roaming 41.3.3 Service Upgrading 41.3.4 Adaptive Modulation and Coding 5

1.4 Operational Requirements 51.4.1 Key Requirements 51.4.2 Reconfiguration Mechanisms 6

1.5 Business Models for Software-Defined Radio 71.5.1 Introduction 71.5.2 Base-Station Model 71.5.3 Impact of OBSAI and CPRI™ 111.5.4 Handset Model 12

1.6 New Base-Station and Network Architectures 131.6.1 Separation of Digital and RF 141.6.2 Tower-Top Mounting 151.6.3 BTS Hoteling 16

1.7 Smart Antenna Systems 181.7.1 Introduction 181.7.2 Smart Antenna System Architectures 191.7.3 Power Consumption Issues 191.7.4 Calibration Issues 21

v

1.8 Projects and Sources of Information on Software Defined Radio 221.8.1 SDR Forum 221.8.2 World Wide Research Forum (WWRF) 231.8.3 European Projects 23References 24

CHAPTER 2Basic Architecture of a Software Defined Radio 25

2.1 Software Defined Radio Architectures 252.2 Ideal Software Defined Radio Architecture 262.3 Required Hardware Specifications 272.4 Digital Aspects of a Software Defined Radio 30

2.4.1 Digital Hardware 302.4.2 Alternative Digital Processing Options for BTS Applications 332.4.3 Alternative Digital Processing Options for Handset Applications 35

2.5 Current Technology Limitations 412.5.1 A/D Signal-to-Noise Ratio and Power Consumption 412.5.2 Derivation of Minimum Power Consumption 432.5.3 Power Consumption Examples 472.5.4 ADC Performance Trends 51

2.6 Impact of Superconducting Technologies on Future SDR Systems 54References 55

CHAPTER 3Flexible RF Receiver Architectures 57

3.1 Introduction 573.2 Receiver Architecture Options 57

3.2.1 Single-Carrier Designs 573.2.2 Multi-Carrier Receiver Designs 603.2.3 Zero IF Receiver Architectures 603.2.4 Use of a Six-Port Network in a Direct-Conversion Receiver 82

3.3 Implementation of a Digital Receiver 843.3.1 Introduction 843.3.2 Frequency Conversion Using Undersampling 843.3.3 Achieving Processing Gain Using Oversampling 853.3.4 Elimination of Receiver Spurious Products 863.3.5 Noise Figure 883.3.6 Receiver Sensitivity 923.3.7 Blocking and Intercept Point 933.3.8 Converter Performance Limitations 953.3.9 ADC Spurious Signals 973.3.10 Use of Dither to Reduce ADC Spurii 1073.3.11 Alternative SFDR Improvement Techniques 1093.3.12 Impact of Input Signal Modulation on Unwanted SpectralProducts 1093.3.13 Aperture Error 1103.3.14 Impact of Clock Jitter on ADC Performance 111

vi Contents

3.3.15 Impact of Synthesiser Phase Noise on SDR ReceiverPerformance 1173.3.16 Converter Noise Figure 118

3.4 Influence of Phase Noise on EVM for a Linear Transceiver 1203.4.1 Introduction 1203.4.2 SVE Calculation Without Phase Noise Disturbance 1223.4.3 Approximation of a Local Oscillator Phase Noise Characteristic 1243.4.4 Incorporation of the LO Phase Noise into the EVM Calculation 1253.4.5 Example Results 1273.4.6 EVM Performance of a Multi-Stage System 131

3.5 Relationship Between EVM, PCDE, and ρ 134References 135

CHAPTER 4Multi-Band and General Coverage Systems 139

4.1 Introduction 1394.2 Multi-Band Flexible Receiver Design 1404.3 The Problem of the Diplexer 142

4.3.1 RF Transmit/Receive Switch 1464.3.2 Switched Diplexers 1514.3.3 Diplexer Elimination by Cancellation 152

4.4 Achieving Image Rejection 1584.4.1 Introduction 1584.4.2 Use of a High IF 1584.4.3 Image-Reject Mixing 159

4.5 Dynamic Range Enhancement 1704.5.1 Feedback Techniques 1714.5.2 Feedforward Techniques 1734.5.3 Cascaded Non-Linearity Techniques 1784.5.4 Use of Diplexer Elimination, Image-Reject Mixing, and HighDynamic Range Techniques in a Receiver 179References 180

CHAPTER 5Flexible Transmitters and PAs 183

5.1 Introduction 1835.2 Differences in PA Requirements for Base Stations and Handsets 184

5.2.1 Comparison of Requirements 1845.2.2 Linearisation and Operational Bandwidths 185

5.3 Linear Upconversion Architectures 1865.3.1 Analogue Quadrature Upconversion 1865.3.2 Quadrature Upconversion with Interpolation 1945.3.3 Interpolated Bandpass Upconversion 1975.3.4 Digital IF Upconversion 1985.3.5 Multi-Carrier Upconversion 1995.3.6 Weaver Upconversion 2015.3.7 Non-Ideal Performance of High-Speed DACs 204

Contents vii

5.3.8 Linear Transmitter Utilising an RF DAC 2055.3.9 Use of Frequency Multiplication in a Linear Upconverter 209

5.4 Constant-Envelope Upconversion Architectures 2105.4.1 PLL-Based Reference or Divider Modulated Transmitter 2105.4.2 PLL-Based Directly-Modulated VCO Transmitter 2115.4.3 PLL-Based Input Reference Modulated Transmitter 2125.4.4 Use of a Direct-Digital Synthesizer to Modulate a PLL-BasedTransmitter 2135.4.5 A PLL-Based Transmitter Utilising Modulated Fractional-NSynthesis 213

5.5 Broadband Quadrature Techniques 2155.5.1 Introduction to Quadrature Techniques 2165.5.2 Active All-Pass Filter 2165.5.3 Use of Highpass and Lowpass Filters 2175.5.4 Polyphase Filtering 2215.5.5 Broadband Passive All-Pass Networks 2225.5.6 Multi-Zero Networks 2255.5.7 Tunable Broadband Phase Splitter 2255.5.8 Lange Coupler 2275.5.9 Multiplier-Divider Techniques 228References 229

CHAPTER 6Linearisation and RF Synthesis Techniques Applied to SDR Transmitters 233

6.1 Introduction 2336.2 Power Amplifier Linearisation Techniques 233

6.2.1 Predistortion 2346.2.2 Analogue Predistortion 2346.2.3 Feedforward 2446.2.4 Basic Operation 2456.2.5 Power Efficiency 2486.2.6 Maintaining Feedforward System Performance 2516.2.7 Performance Stabilisation Techniques 2536.2.8 Relative Merits of the Feedforward Technique 261

6.3 Transmitter Linearisation Techniques 2626.3.1 Digital Predistortion 2626.3.2 Relative Merits of Predistortion Techniques 2766.3.3 Feedback Techniques 2776.3.4 RF Feedback 2776.3.5 Envelope Feedback 2786.3.6 Polar Loop 2806.3.7 Cartesian Loop 284

6.4 RF Synthesis Techniques 2876.4.1 Polar RF Synthesis Transmitter 2876.4.3 Sigma-Delta Techniques 295

6.5 Power Efficiency 296

viii Contents

6.6 Summary of the Relative Merits of Various Linear Amplifier andTransmitter Techniques 297

References 301

Appendix A 90° Phase-Shift Networks 305

A.1 General Structure 305Reference 309

Appendix B Phase Noise in RF Oscillators 311

B.1 Leesons Equation 311B.1.1 SSB Phase Noise Characteristic of a Basic Oscillator. 311B.1.2 Leesons Equation 311References 312

Acronyms and Abbreviations 313

About the Author 319

Index 321

Contents ix

Preface

Scope of This Book

Software defined radio (SDR) is an emerging form of radio architecture, whichencompasses a wide range of design techniques in order to realize a truly flexible,and potentially future-proof, transceiver system. As a field, it is very broad, encom-passing: systems design, RF, IF, and baseband analogue hardware design, digitalhardware design, and software engineering. Covering all of these topics in sufficientdetail to become a design reference would be a huge task, therefore, this bookfocuses on the former aspects of SDR, namely, systems design and RF, IF, and base-band analogue hardware design. It also includes an introduction to some of the digi-tal hardware options for the baseband signal-processing element, although it doesnot attempt to provide detailed design information in this area.

The emphasis on analogue hardware and digital conversion technologies stemsfrom the current reality that the antenna plus analogue-to-digital converter (ADC)architecture often envisaged for future radio receivers (and similarly for the trans-mitter) is far away from becoming a reality in the main cellular communicationsbands. Indeed, there are some very significant challenges to overcome before thiscould ever be considered a realistic architecture for cellular applications, and theseare highlighted in this book.

Many of the techniques described in the book are still at the research stage andare presented as ideas for further development. Some of these techniques may neverbecome a reality and may be superseded by alternative technologies; however, theirpresence in this book will hopefully stimulate such alternative ideas and further thedevelopment of the exciting field of SDR.

Organisation of the Text

The text is divided into six chapters covering the hardware aspects of soft-ware-defined radio design. The chapters may be summarised as follows:

1. Introduction.2. Basic Architecture of a Software-Defined Radio. The ideal software-defined

radio architecture is introduced and the practical limitations of currenttechnology are highlighted, which make this architecture currentlyunrealizable. Some of the digital aspects of a software-defined radio are alsodiscussed, along with appropriate implementation technologies. Finally,

xi

some issues with high-speed ADC performance and power consumption arehighlighted.

3. Flexible RF Receiver Architectures. A range of techniques is covered whichmay be used to realise a practical receiver RF section for a software-definedradio. Detailed examples are given, where appropriate, of the calculationsinvolved at various stages of the design.

4. Multi-band and General Coverage Systems. Techniques covered in thischapter include dynamic range enhancement methods, image removalarchitectures, and duplexer elimination techniques, among others.

5. Flexible Transmitters and PAs. A crucial and difficult area in asoftware-defined radio is a flexible, linear transmitter. This chapterhighlights the various techniques available to solve this problem and alsocovers techniques appropriate for providing the broadband quadraturesignals required in many transmitter (and receiver) architectures.

6. Linearisation and RF Synthesis Techniques Applied to SDR Transmitters.The final chapter discusses the various linearised power amplifier andtransmitter architectures appropriate for use in an SDR system. It comparesthem based upon complexity, cost, suitability for integration, and powerefficiency.

xii Preface

Acknowledgements

The material presented in this book represents a distillation of many years ofresearch, design, and development work, carried out primarily at the University ofBristol and at Wireless Systems International Ltd. I would like to thank my formercolleagues at both establishments for their assistance, encouragement, and criti-cism, without which many of the ideas presented here would never have reachedfruition.

In particular, I would like to thank Ross Wilkinson, Andy Bateman, BillWhitmarsh, Jim Marvill, Dave Bennett, Kieran Parsons, Shixiang Chen, SueGillard, John Bishop, Tony Smithson, and Jonathan Rogers for their help andenthusiasm throughout the many projects we worked on together.

I would also like to thank my wife, Gay, for her understanding during the manylong evenings and weekends taken to prepare the manuscript.

xiii

C H A P T E R 1

Introduction

1.1 What Is a Software Defined Radio?

The term software radio has become associated with a large number of differenttechnologies and no standard definition exists. The term is usually used to refer to aradio transceiver in which the key parameters are defined in software and in whichfundamental aspects of the radio’s operation can be reconfigured by the upgradingof that software.

A number of associated terms have also been used in the context of programma-ble or reconfigurable mobile systems [1]:

• Software defined radio (SDR): This is the term adopted by the SDRForum—an international body looking at the standards aspects of softwareradio [2].

• Multi-standard terminal (MST): This type of terminal is not necessarily asoftware defined radio in the context of this book, although it may be imple-mented in that way. It simply refers to a terminal which is capable of opera-tion on a number of differing air interface standards. This type of terminalwill provide either wider international roaming than would a single-standarddevice, or a necessary smooth upgrade path from a legacy system to a newstandard, for example, the transition from Global System for Mobile commu-nications (GSM) to wideband code-division multiple access (WCDMA).

• Reconfigurable radio: This term is used to encompass both software and firm-ware reconfiguration [e.g., through the use of programmable logic devices,such as field programmable gate array (FPGAs)]. Both forms of reconfigura-tion are likely to be necessary in any cost and power-efficient software radioimplementation.

• Flexible architecture radio (FAR): This is a wider definition still than thoseabove. It indicates that all aspects of the radio system are flexible, not just thebaseband/digital section. A true FAR should allow parameters such as thenumber and type of up/downconversion stages to be altered by software aswell as, for example, IF filter bandwidths and even the RF frequency band ofoperation. This is clearly a utopian goal for software radio.

Further variations on the above themes are also in use; however, they all fallinto one or other of the above categories. These categorisations will be used, whererelevant, in this book.

1

1.2 The Requirement for Software Defined Radio

1.2.1 Introduction

Software defined radio is an enabling technology in many areas of communications.It has been, or is being, examined for a very wide range of applications, including:

1. Military communications—the U.S. SpeakEasy programme [3]. Thisprogramme formed some of the initial basis for the SDR Forum [2]. Thebenefits of a software defined radio system in a military context are obvious.A radio which can change not only its scrambling or encryption codes on anad hoc basis, but one which can also change its modulation format, channelbandwidth, data rate, and voice codec type is clearly an exciting operationalprospect. An adaptable radio of this type could both foil an enemy’s attemptsat eavesdropping and be configured to match operational requirements orconditions (e.g., propagation characteristics). Such a system clearly has hugepotential benefits in the theatre of war.

2. Civilian mobile communication. In the competitive world of civiliancommunications, any system that allows an operator or service provider tooffer enhanced benefits or services relative to competing operators clearlyhas huge potential. The costs incurred in evolving a complete network to anew standard, by means of hardware replacement, are enormous. It isestimated, for example, that the cost of building the new 3G network inEurope, assuming that all of the expected licenses are deployed, will beupwards of $200 billion [4]. If the existing GSM infrastructure hardwarehad been designed on software defined radio principles (and if it possessedsufficient processing power when it was installed in the early 1990s—a verybig if), then the cost of deploying 3G would be a tiny fraction of this figure.They key issue is, of course, whether sufficient digital processing can bebuilt-in at deployment to allow for unknown service or air interfaceupgrades. This issue is explored further later when examining the businesscase for software defined radio.

3. Introduction of new technologies in legacy frequency bands. There are anumber of examples of this form of application for software defined radio,ranging from U.S. specialised mobile radio (SMR) deployments [5], throughEuropean data systems [6] to international seismic survey operations [7].These will also be examined in more detail later.

1.2.2 Legacy Systems

Software-defined radio technology is often an enabling technique when it is desir-able to upgrade from an existing, well-established system to a newer, high capacitynetwork. A good example of this is in the U.S. SMR bands, where frequency modu-lation (FM) is (or increasingly was) widely deployed for use by taxis, security firms,and so forth. The traditional options for upgrading such networks were:

1. Deploy an entire new network using the existing sites and frequency bands(but with a new technology, e.g., modulation format), furnish all of the users

2 Introduction

with new mobiles and handhelds, and have a hard switch-off of the oldnetwork on a particular day. There are numerous, obvious disadvantageswith this approach:

• Installation of new mobiles alongside existing ones is very difficult andnot popular with users.

• Installation of a complete new network in a relatively short time requires ahuge capital investment—a phased replacement is much more palatablefrom a financial perspective.

• Some network problems are almost inevitable when deploying a new tech-nology and then placing a heavy load on it at switch-on. If these are signif-icant, the users will be highly dissatisfied—again, a phased deploymentwill minimise such disruption.

2. Obtain a new frequency band for the new technology, deploy a newnetwork, which in this case needs to have similar coverage to the oldnetwork, but not necessarily similar capacity (initially), and graduallymigrate users to the new system. This is clearly a preferable option,assuming that the new frequency band obtained has adequate propagationcharacteristics. The key issue with this approach is that the obtaining of anew frequency band, in an already overcrowded spectrum, is both difficultand very expensive. In addition, both bands must be serviced from the samecustomer base (at least initially) and this can put a huge financial burden onthe existing customers, which may drive them away, or on the company’sinvestors if they choose to subsidize the system in the short term.

Adopting a software defined radio based approach to the terminals in such asystem allows the gradual deployment of both the new network (in the existing fre-quency allocation) and the new mobiles. For example, in a typical FM SMR sce-nario, one of the five allocated SMR channels could be replaced by a newdeployment, followed by a second deployment some time later, as mobile deploy-ment grew, and so on until the entire network had been renewed. Strictly speaking,a software defined radio terminal is not essential for this to take place (a dual-modeterminal would suffice); however, it is likely that if a significant technologicalchange is involved in transitioning from the old system to the new, then a softwaredefined radio based terminal will be the most cost effective (and smallest) solution.

1.3 The Benefits of Multi-standard Terminals

A multi-standard terminal (MST) is a subscriber unit that is capable of operationwith a variety of different mobile radio standards. Although it is not strictly neces-sary for such a terminal to be implemented using software defined radio techniques,it is likely that this approach is the most economic in many cases. Some of the keybenefits of a reconfigurable MST are outlined in the following sections.

1.3 The Benefits of Multi-standard Terminals 3

1.3.1 Economies of Scale

Even if terminal adaption over the air or via third-party software was not possible orwas not permitted by, for example, regulatory bodies, the production benefits of asoftware-defined radio approach could well justify its existence. The wide range ofnew and existing standards in the cellular and mobile marketplace has resulted inthe adoption of a diverse range of subscriber terminal (and base-station) architec-tures for the different systems deployed around the globe. The ability to develop andmanufacture a single reconfigurable terminal, which can be configured at the finalstage of manufacture to tailor it to a particular market, clearly presents immensebenefits to equipment manufacturers. With the design, components used, and hard-ware manufacturing processes all being identical for all terminals worldwide, theeconomy of scale would be huge. This has the potential to offset the additional hard-ware costs which would be inevitable in the realisation of such a generic device.

1.3.2 Global Roaming

The present proliferation of mobile standards and the gradual migration to thirdgeneration systems means that a large number of different network technologies willexist globally for some time to come. Indeed, even in the case of 3G systems, where aconcerted effort was made by international standards bodies to ensure that a singleglobal standard was produced, there are still significant regional differences, in par-ticular between the U.S. and European offerings (and also, potentially, China). Withthis background, it is clearly desirable to produce a terminal which is capable ofoperation on both legacy systems and the various competing 3G standards. Indeed,it could be argued that this is the only way in which 3G systems will be accepted byusers, since the huge cost of a full-coverage network roll-out will discourage manyoperators from providing the same levels of coverage (at least initially) as their exist-ing 2G systems enjoy. A user is unlikely to trade in his or her 2G terminal for onewith perhaps better services, but a significantly poorer basic voice coverage. This isindeed what is happening in virtually all current 3G deployments. A softwaredefined radio architecture represents a very attractive solution to this problem.

1.3.3 Service Upgrading

A powerful benefit of a software defined radio terminal, from the perspective of thenetwork operator, is the ability to download new services to the terminal after it hasbeen purchased and is operational on the network. At present, significant serviceupgrades require the purchase of a new terminal, with the required software built-in,and this clearly discourages the adoption of these new services for a period. Thelaunch of General Packet Radio Service (GPRS) data services on the GSM network isa good example of this.

With an SDR handset architecture, services could be downloaded overnight,when the network is quiet, or from a Web site in the same manner as personal com-puter (PC) software upgrades are distributed. There are clearly a number of logisti-cal issues with this benefit (e.g., what to do about phones which are turned off at thetime of the upgrade or what happens if a particular phone crashes with the new soft-ware, perhaps just prior to requiring the phone for an emergency call—software

4 Introduction

which the phone user may not have wanted, and so forth). Many of these problemshave been solved by the PC industry and hence it is likely that this benefit will berealised in some manner with software defined radios.

1.3.4 Adaptive Modulation and Coding

The ability to adapt key transmission parameters to the prevailing channel or trafficconditions is a further key benefit of a software defined radio. It is possible, forexample, to reduce the complexity of the modulation format, such as from16-QAM (quadrature amplitude modulation) to quadrature phase-shift keying(QPSK) when channel conditions become poor, thereby improving noise immunityand decoding margin. It is also possible to adapt the channel coding scheme tobetter cope with particular types of interference, rather than Gaussian noise, whenmoving from, say, a rural cell to an urban one. Many parameters may be adapteddynamically, for example, burst structure, modulation type, data rate, channel andsource coding, multiple-access schemes, and so forth.

1.4 Operational Requirements

1.4.1 Key Requirements

The operational characteristics of an ideal multi-standard terminal include the fol-lowing operations.

1.4.1.1 Software-Definable Operation

As outlined earlier, the key to many of the advantages of a multi-standard terminallies in its ability to be reconfigured either: during manufacture, prior to purchase,following purchase (e.g., after-market software), in operation (e.g., adaptation ofcoding or modulation), or preferably all four. This impacts primarily upon the digi-tal and baseband sections of the terminal and will require the use ofreprogrammable hardware as well as programmable digital signal processors in apower and cost-effective implementation.

1.4.1.2 Multi-Band Operation

The ability to process signals corresponding to a wide range of frequency bands andchannel bandwidths is a critical feature of a MST. This will impact heavily on theradio frequency segments of the terminal and it is this area which is arguably themain technology limitation on software defined radio implementation at present(although processor power consumption and cost are still both major issues forSDR).

1.4.1.3 Multi-Mode Operation

Many multi-mode software defined radios already exist, although they are oftennot promoted as such (since the other features/benefits of software defined radio

1.4 Operational Requirements 5

techniques are not exploited). The ability to change mode and, consequently, modu-lation, coding, burst structure, compression algorithms, and signalling protocols isclearly an essential feature of an MST.

1.4.2 Reconfiguration Mechanisms

There are two main reconfiguration mechanisms that are currently favoured forsoftware defined radio, with each having a number of variants. The basic mecha-nisms are over-air download and manual upgrades.

1.4.2.1 Over-Air Download

With this mechanism, a range of options from the updating of a small number ofparameters (e.g., filter coefficients), through the adding of a new service (e.g.,e-mail) to a full upgrade of the terminal software, are possible. There are two mainissues to be overcome: how to ensure that all mobiles in a network have beenupgraded before making use of the new parameters (e.g., a tighter channel spacing,following an upgrade of filter coefficients) and how to deal with the potentially largeamount of data which would need to be distributed to each phone (e.g., for a com-plete upgrade of the whole handset software). Although not huge by comparisonwith a typical PC application, for example, it would still constitute a significantamount of network traffic.

It is currently thought that the only realistic option to address this latter problemis to restrict over-air downloads to the updating of coefficients or the enabling ofalready-existing software services. In this case, it is assumed that the handset alreadycontains the software required for the new service (for example, the e-mail serviceproposed earlier), and all that needs to take place over the air interface is for the ser-vice to be enabled and an e-mail address assigned to the phone. This would onlyrequire a small amount of network traffic and hence would represent a realisticproposition for the network operator and a realistic cost for the user. The higherdata rates available in third generation (3G) systems may make broadcast updatingof handset software, and not just system parameters, a realistic option.

In the case of the other main issue, that of ensuring that all mobiles have beenupgraded prior to a major service change (e.g., a change of channel spacing or mod-ulation format), this is significantly more problematic. The only realistic option isfor a similar process to be adopted to that of Internet software upgrades. In this case,new software can be automatically downloaded once the service provider hasflagged that a new download is available. Both the old and the new systems wouldhave to operate simultaneously until such time as more than a certain (high) percent-age of users had upgraded. Support for the old service would then cease.

1.4.2.2 Manual Download

This option is again similar to its personal computer counterpart. If the users wish toadd a new service, they would simply purchase a disk or CD containing the requiredsoftware and load it into their phone from a PC (or have it installed by their phonevendor). This could apply to anything from a single new application (e.g., e-mail)

6 Introduction

through to an entire new suite of software including an operating system. Elementsof this model are beginning to emerge (along with its Internet download counter-part) in the sale of ring tones for some 2G and 3G phones.

1.4.2.3 Handset Operating Systems

For these models to work successfully, it is likely that some form of handset operat-ing system will need to emerge, in a manner similar to the Windows and Linux oper-ating systems for PCs. Such systems are already in use, with WindowsME andSymbian being the two main examples available currently, however these are, atpresent, not specifically tailored to the needs of an SDR handset or digital signal pro-cessing applications in general. Other options exist, however, such as OSE [8]; thisoperating system is already being used in base stations for this type of application. Ifand when this happens to the required degree, it paves the way for third-party appli-cations providers to greatly expand the capability of the humble mobile telephoneand this is probably essential for the success of third generation systems.

1.5 Business Models for Software Defined Radio

1.5.1 Introduction

The advent of software defined radio has already revolutionised the business modelfor mobile communications (see the discussion of legacy systems in Section 1.2.2).There are two further business issues which need to be addressed:

1. The business model for infrastructure procurement—the changes which arenow possible to traditional outsourcing models;

2. The financial penalties and benefits in adopting a software defined radioapproach to terminal design. In other words, in a fiercely price-competitivehandset market, why pay a premium for the additional technology necessaryfor a software defined radio–based terminal (and how large is thatpremium)?

1.5.2 Base-Station Model

The architecture of most wireless base stations has moved from an intrinsicallymodulation-specific architecture to a largely software-defined architecture. Thischange, in addition to the recent moves toward standardisation of the internalbase-station transceiver system (BTS) digital interfaces, in the Open Base-StationArchitecture Initiative (OBSAI) and Common Public Radio Interface (CPRI™) ini-tiatives (see Section 1.5.3), radically alters the BTS procurement and business modeloptions. The interface between the waveform generation and waveform transmis-sion functions is now, in many cases, digital and it is increasingly common for anoriginal equipment manufacturer (OEM) to outsource both the baseband digitalcard hardware and the high-power RF transceiver hardware. This leaves the OEMfree to concentrate on the complex application layer software and services provisionareas, which are their key differentiators in many applications.

1.5 Business Models for Software Defined Radio 7

The ideal BTS model, from an OEM’s perspective, would involve a small num-ber of standard (not necessarily standardised) building blocks, which could be cas-caded in order to form a complete hardware solution. This has not been possible inthe past, due to the application-specific and vendor-specific nature of the compo-nents involved. The advent of SDR techniques, however, is increasingly leading tothis model being adopted.

An outline of the modulation generation and transmission elements of this typeof base station is shown in Figure 1.1. It is now possible to define each of the mainelements (digital signal processing and linearised transmitter and diplexer) as mod-ules (from a hardware perspective). Of these items, many are already outsourced byOEMs, for example, the digital and/or digital signal processor (DSP) card, thediplexer, and also the PA element of the transmitter. The final step, from an SDRbusiness perspective, is to outsource the upconverter and associated synthesizer aspart of an overall linearised transmitter solution. There are now a number of BTSOEMs heading down this route in order to simplify the hardware and supply-chainaspects of their base-station infrastructure solutions.

This trend will continue and spread to the OEMs not already adopting this model,since the OEMs increasingly need to concentrate their efforts on their areas of corecompetence, in order to provide product differentiation. These areas are typically insoftware and services provision (e.g., the quality of the switch), as they are capable ofgenerating additional profit or valuable service differentiation for the network opera-tor. They are therefore increasingly keen to offload the RF hardware elements of thesystem as these occupy skilled (and expensive) engineering effort and carry substantialdevelopment risk, yet yield minimal benefit in the form of saleable features.

1.5.2.1 New BTS Business Models Enabled by SDR

The adoption of an SDR architecture for a BTS moves the interface to the digitaldomain and leads to the concept of an RF black box containing all of the RF aspectsof both the transmitter and receiver(s), plus, increasingly, the diplexer, although thisis still a separate component in many designs. Such a system is illustrated in Figure1.2 with a Cartesian interface; alternatively, a digital IF or digital polar interfacecould also be used.

An argument often levelled against the adoption of this approach is that too muchof the base station is being subcontracted. It is common practice, at present, for the PAmodule to be bought as a subsystem from an outside supplier, and this is a widely

8 Introduction

Upconverter RF PA

Diplexer

To receiver

DSP Linearisation

Linearisedtransmitter

Basebandinput(s)

Figure 1.1 Digital input/RF output transmitter employed in a software defined radio base station.

accepted business model within the BTS OEM community. Putting this into context,Figure 1.3(a) shows a generic RF upconverter and PA combination, and it wouldappear, at first glance, that subcontracting the design of the PA does not represent asignificant amount of the overall system. If, however, the PA is linearised, which is acommon requirement in code-division multiple access (CDMA), orthogonal fre-quency division multiplexing (OFDM), and π/4-DQPSK (differential quadraturephase-shift keying) systems, the complexity embedded within that block becomes sig-nificant and it is also a much bigger component of the overall transmitter cost andsize. This is highlighted in Figure 1.3(b), in which the relative size of the power


Digitallineariser

DAC Upconverter PA

Diplexer

LNADownconverterADCDigitaldownconverter

Lineariser feedback

I/Q digitalinput

I/Q digitaloutput

Figure 1.2 Contents of an RF black box SDR system.

RF PA

RF PA

(a)

(b)

Figure 1.3 (a) Conventional block-diagram of the RF section of a linear transmitter and (b)representation of this scaled by cost.

amplifier (PA) and RF signal processing elements is scaled based upon cost, althoughthis figure would also look similar if the scaling was based upon physical size.

The conclusion from this illustration is clear: subcontracting the remaining ele-ments of the RF section of an SDR transmitter will have a relatively minor impact onunit cost (and, typically, a positive impact on overall BTS cost). It will free up valu-able RF engineering resource for other tasks and will have no impact on the productdifferentiation capability of the OEM—few, if any, base-station sales are basedupon the incorporation of a novel upconverter within the BTS design.

1.5.2.2 Upgrade Versus Replacement in a BTS Context

Upgradability is often a difficult concept to sell in a high-technology system. It seemsto be a straightforward argument on the surface: Technology advances so quicklythat systems rapidly become obsolete; why not, therefore, design them so that theycan be upgraded rather than discarded? In practice, the cost of upgrading versus thecost of replacement does not usually make this argument compelling. Take the PCmarket as an example. Very few people upgrade processors, motherboards, and soforth, as it is not usually economic. By the time a user has upgraded the motherboardso that it is capable of working with a new, faster processor, added a new graphicscard to work with the desired new applications, added or replaced the hard drive, asthe new software assumes a greater disk capacity and hence uses more disk space,and so forth, the cost is usually similar to or greater than the cost of a new machine.In addition, the upgraded machine is unlikely to have a warranty and hence the useris alone responsible for any compatibility problems.

In the case of a BTS, some of the compatibility and warranty issues can be allevi-ated, since it is likely that the upgrade hardware will be provided by the original sys-tem vendor and hence they will be responsible for maintaining system integrity(although OBSAI and CPRI™ may change this paradigm). The issue of cost versusreplacement is still just as valid, however, and here there are some significant differ-ences when compared to the PC model described earlier.

The radio parts of a BTS consist of two main sections:

1. The radio frequency and analogue electronics, including the analoguebaseband processing (e.g., anti-alias filtering), IF components, localoscillators, low-noise amplification, power amplification, and so forth.These elements are mostly housed within the transceiver unit (sometimesknown as the TRx), with the RF power amplifier and diplexer often beingseparate components.

2. The digital signal processing hardware, firmware, and software. This oftenappears as one or more separate cards (e.g., one per RF carrier) plugged intoa card frame, with a common bus. This part of the BTS contains the DSPdevices, application-specific integrated circuit (ASICs), FPGAs, memory, andclock oscillators necessary to generate the modulation, coding, framing, andso forth required for the system or systems which it is designed to support.

The interface between these two elements can be analogue, in which case thenecessary digital-to-analogue converter (DACs) and analogue-to-digital converter

10 Introduction

(ADCs) can be found on the digital signal processing cards, or digital, when theywill be found in the TRx unit(s). It is increasingly common for the interface to adoptthe latter, digital format, with both OBSAI and CPRI™ adopting this architecture.

There is a significant difference in the rate and type of development betweenthese two parts of a BTS system. For example, a new design of RF power amplifierin an existing frequency band (e.g., 900 MHz) might well use the same RF powerdevices as an existing design from, say, 2 years previously. Even if new devices areavailable, they are unlikely to differ in any significant regard, of import to soft-ware-defined radio, from their predecessors. They are unlikely, for example, tocover a significantly greater bandwidth (they are usually band-specific anyway) orhave a significantly improved intermodulation distortion (IMD) performance. Theold design is therefore not, strictly speaking, out of date—it will still work well witha new modulation format. The same is true of most aspects of the RF part of the sys-tem; new parts are created which are cheaper, smaller, and more efficient, but func-tionally they are little or no more capable than their predecessors, from areconfiguration viewpoint. It is therefore realistic to design the RF elements of thesystem to be future-proof in some meaningful way, without fear that futureimprovements in technology will render them unusable.

Linearised power amplifiers are a good example of this. A mid-1990s feed-forward based power amplifier in, say, the 800-MHz band, is still a fully flexible,reconfigurable component today and it still covers the correct (allocated) band-width. A newer design of amplifier will certainly have advantages over its earliercounterpart (most notably in the areas of cost, size, and efficiency); however, theolder design will still perform adequately in a software-defined radio context.

In the case of the digital parts of the system, however, this is certainly not thecase. Moore’s law [9] indicates that an 18-month-old processor (e.g., a DSP) willhave half the processing power of a recent part; extrapolate this over a realisticreplacement life cycle of perhaps 5 to 7 years (or more) leads to a processing powerdifference of around 16 times. Trying to future-proof this part of the system wouldtherefore be very difficult and would involve the use of a very large number ofstate-of-the-art components and a considerable expense. It is unlikely that this costcould be justified, based upon a future-proofing argument alone and it is difficult tosee any other good reason for adopting this approach.

The most sensible option for future-proofing may therefore be to invest signifi-cant design effort in future-proofing the RF and analogue baseband elements of thesystem (probably, but not necessarily, including the ADCs and DACs) and makingthe baseband digital cards in the form of current-technology throwaway items,much like the motherboard in a PC. The cost of upgrading a digital card (or a num-ber of digital cards) in the future will be modest in comparison to the cost of upgrad-ing the whole BTS and much lower than the cost of upgrading the RF elements; theRF power amplifier alone is likely to account for 50% or more of the cost of a thirdgeneration BTS installation (excluding site costs) within the next few years.

1.5.3 Impact of OBSAI and CPRI™

OBSAI [10] and CPRI [11] are industry-led standardisation activities aimed atopening up the interfaces within a BTS. They are intended to provide an open


marketplace into which third-party equipment vendors will be able to providehigh-volume BTS subsystems for a range of OEM customers, thereby reducing costsfor an individual OEM customer. Most major OEMs now belong to one or other ofthese organisations, with initial drafts of the standards already having been pub-lished and product developments being under way.

The standards cover:

• Baseband module to RF module high-speed data interface (transmitting theI-Q data representing the waveform(s) to be transmitted);

• Low-speed data for control, operation, administration, maintenance, andprovisioning (OAM&P), and so forth;

• Clock/timing distribution;• Interface to remote RF heads.

In addition, OBSAI is currently going further and specifying aspects of the mod-ule mechanics, power supply, testing, and so forth.

Both of these standards activities are based around an SDR-friendly basebandin-phase and quadrature (I-Q) interface. The use of SDR hardware architectures istherefore highly appropriate for both of these standards and they have the potentialto bring the economies-of-scale benefits of SDR to the BTS marketplace. This arisesfor a number of reasons:

• The baseband, crest-factor reduction, DAC, and upconversion architecturesare reuseable across a range of frequency bands and air interface standards,typically with very minor changes [e.g., a synthesizer voltage-controlled oscil-lator (VCO)].

• Likewise, the downconversion, analogue-to-digital (A/D) conversion, andbaseband receive architectures are also reusable across a range of frequencybands and air interface standards with similarly minor changes.

• Software for the protocols associated with the above interfaces is typicallyreuseable across all platforms.

These initiatives could therefore be viewed as good for the adoption of SDRtechniques within mainstream base-station designs.

1.5.4 Handset Model

There are three categories of customer for software defined radio technology andeach has its own potential series of benefits, which will be reaped if it is successful:

1. Equipment manufacturers. The benefit to equipment manufacturers islargely in terms of economies of scale: The adoption of SDR allows amanufacturer to ideally only manufacture a single handset product (at leastin terms of its electronics). If this occurs, then the benefits to thatmanufacturer are potentially huge. Only a single product needs to besupported, in terms of hardware, thus considerably simplifying almost allaspects of manufacturing, thereby:

12 Introduction

• Lowering inventory requirements;• Reducing the number of suppliers;• Increasing ordering volumes;• Reducing documentation/support/spares requirements, and so forth;• Reducing test equipment and test-set design requirements.

This will also, therefore, have a significant impact upon cost. It will also,of course, reduce the need for design teams for different air interfaceplatforms and hence may even lead to staff reductions in these areas.

2. Network operator. Competition between network operators is largely onthe basis of cost and quality of service; anything that can give an operator anedge in quality, without resulting in a significant increase in cost is clearly ofinterest to them. SDR terminals allow the operator the potential of fieldupgrades in order to correct problems or add new services and features. Thecorrection of problems is actually a very attractive area, as a handset recallto fix a software bug is an extremely expensive undertaking. The ability tobe able to add new service innovations instantly, rather than having to waitfor old handsets to become obsolete, is also of great interest. A goodexample of where this would have been useful to a network operator is in theaddition of frequency-hopping to the GSM network. One of the early,popular handsets did not implement that feature and hence the introductionof frequency-hopping was delayed on many networks, until this handsetcould be deemed obsolete.

3. Consumer. The consumer’s buying decision is influenced by many factorsand technology/features is only one of them. Many other factors are of equalor greater importance, such as: size, weight, battery life, case styling, andeven brand credibility; all of these are equally or more important to manyusers. The advent of software defined radio does, however, bring somepowerful benefits and these may prove to be key selling features to somecustomers. Such features include genuine global roaming and fullupgradability (in the same way that PC software can be upgraded). Thislatter feature will lead to a new PC-like after-market software industry.Global roaming, on the other hand, will only be an advantage to theinternational business traveller; however, this market segment is typicallywealthy and a heavy airtime user and is therefore a very attractive customerto a network operator and operators are likely to take disproportionatesteps to acquire this customer’s business (e.g., greater than average handsetsubsidies). This makes the affordable adoption of SDR technology morelikely for this (top) end of the market, therefore providing a way into themarket for this technology via the business traveller route.

1.6 New Base-Station and Network Architectures

The use of PA linearisation and, in particular, digital-input linearised transmittersenables a number of new base-station topologies to be realised. These topologies

1.6 New Base-Station and Network Architectures 13

result in a number of significant advantages for both the base-station manufacturerand the network operator, particularly in the areas of power consumption and cost.

In a conventional base station, the baseband and RF sections of the transceiverare usually physically close to each other, and in many cases in the same box. Thepower amplifier(s) are also generally close, typically being located in the same rack(if not the same box, in the case of single channel PAs). The RF power is not, there-fore, being generated close to its intended point of use (the antenna), and a signifi-cant amount is wasted in getting it there. There are three alternative topologieswhich are enabled by the use of linear power amplifiers: the separation of digital andRF sections within a base station, tower-top mounting (not new in itself, but linearPAs add some new possibilities which may overcome current concerns), andorphaned RF networks (also known as BTS hoteling).

1.6.1 Separation of Digital and RF

The advent of OBSAI and CPRI™, together with that of the digital-input transceiversystems upon which they both rely, means that the historic placement of both thedigital and RF sections of a base station in close physical proximity is no longer arequirement. The baseband section can now be effectively stand-alone, since the RFtransceiver is simply a linear processing device, which will faithfully reproduce theinput signal described to in digital form. It is therefore possible to physically sepa-rate the baseband and RF sections of the base station by an almost arbitrary dis-tance, particularly if an optical transport medium is utilised between the two. Thetransceiver may therefore be mounted at a convenient location close to the antenna,for example, on the side of a building or at the top of a mast, with a consequentreduction in RF power requirements (due to the virtual elimination of high-powerRF cable losses) and a lowering of both purchase and running costs.

An example of the type of application where the separation of the digital and RFaspects of a base station may prove useful is in a (larger) urban base site. Here, spacemay be rented in expensive office accommodation, close to the top of a building, forexample. The only item, however, which needs to be placed in that location is the RFsection; the remainder of the system could easily be placed in lower-cost basementspace, with, for example, a fibre-optic link between the two.

Alternatively, a single location could be used to house the base-station digitaland network interfacing hardware for a number of base sites, required, for example,to provide coverage in a large building (e.g., a shopping mall or an airport). Theindividual base sites would then merely consist of a number of RF sections [orremote RF heads (RRH)], with each comprising an RF black box (see Section1.6.3.2) and an antenna. The RF black box itself would incorporate a digital or opti-cal input, RF transmitter and an RF input, digital (or optical) output receiver,together with a diplexer (as appropriate) and any local power supply functionality(DC, or AC mains). It is often easier to source mains power locally rather than toattempt to distribute low-voltage DC along with the digital or optical signals,although cables do exist to facilitate this (e.g., Amarra [12]).

14 Introduction

1.6.2 Tower-Top Mounting

A second new topology is to mount the RF transceiver at the top of the mast con-taining the transmit and receive antennas, as illustrated in Figure 1.4(a). Someinstallations of this type already exist; however, the approach adopted has been tosend low-power RF signals up the mast, to be amplified at the top. This approachhas a number of benefits over the more traditional approach of mounting the ampli-fier(s) in a cabin at the base of the mast, since it eliminates high-power RF cablelosses. These can account for up to half of the power generated in the PA, and this inturn can lead to a doubling of the effective PA efficiency (based on dc power input tothe PA versus RF power transmitted from the antenna).

The main issues with adopting this approach are:

1. Maintenance. The failure of a unit at the top of a mast will result in anexpensive operation to effect a repair or replacement. The reliability requiredfrom such (outdoor) units is therefore high, and network operatorsare largely skeptical that it can be met. There are grounds for optimism,however, as confidence in active electronics at the masthead has been boostedby the installation and good reliability of tower-mounted amplifiers (TMAs)in 3G systems. In addition, the lower RF output powers required fromtower-mounted units mean that they require fewer active devices and will runcooler (thereby mitigating two major potential sources of unreliability).

A further consideration with regard to reliability is that of failures in thehigh-power RF cable, for example, due to water ingress. While not the mostcommon cause of base-station failure, it is nevertheless a significant issue


RFBlackBox

Basestation

Opticalfibre

Network

Base-stationcabin

Mast

Basestation

Opticalfibre

Network

Mast

Basestation

Basestation

Centralbase-stationhub

(a) (b)

RFBlackBox

RFBlackBox

RFBlackBox

~ ~ ~ ~

~~~10 km

Figure 1.4 Use of a digital-to-RF black-box to (a) enhance an existing base-station concept and (b) enable anew centralised hub architecture.

and the replacement of this cable with, for example, fibre-optic cable, shouldgreatly reduce the incidence of failures in this part of the system.

2. Weight. Mounting a number of high-power RF transceivers at the top of amast will add significantly to the loading on the mast and could lead to therequirement for an upgraded or replacement mast. This clearly adds to thecost of the installation and will remove some of the cost benefits of thisapproach (but probably not all, if designed-in at the outset). It is, however,worth bearing in mind that the weight of the cables going up the mast to feedthe RRH unit(s) will be greatly reduced (optical fibre, for example, is muchlighter than low-loss, high-power coaxial feeder cable). The weight issue istherefore one which requires careful analysis for each individual case andmay end up as an advantage in many installations.

3. Delay. If a public data network, or a significant number of routers orswitches, is used for distribution of the digital signals, this will result in asignificant delay being inserted into the cell. This will have the effect ofreducing the maximum cell radius and hence its overall coverage. In the caseof providing transmission utilising a public distribution network, this delaymay well be unknown (and could vary from day to day with routing changeswhich are out of the control of the network operator). This latter issue maywell exclude the use of public networks for distributed base-stationapplications. As long as a public network is not used (nor a large number ofrouters/switches), an acceptable cell radius can usually be obtained for mostair interface systems, even after transmission has taken place over many tensof kilometers.

1.6.3 BTS Hoteling

1.6.3.1 Introduction

The concept of BTS hoteling is illustrated in Figure 1.4(b). This is a new innovationin network deployment in which the majority of the components of a traditionalbase station are housed in a central location (the hub). This hub can be placed at aconvenient, low-cost location, for example, in the basement of a downtown buildingor in an out-of-town industrial park. This leaves a minimum of components that arerequired to be housed at the cell site. The concept is similar to that of its Internetcounterpart (i.e., Internet hoteling).

All of the network components, interface elements, and so forth, as well as thebaseband signal generation, modulation, demodulation, coding, and framing func-tionality are housed at the central base-station hub. The hub interfaces directly tothe relevant telecommunications network and derives all subscriber calls fromthere. It also generates and receives the modulated data samples required for trans-mission to/from the remote RF head. The hub therefore contains all of the intelli-gence of the base station and appropriate measures can be taken to ensure itscontinued operation (e.g., having a permanent staff for maintenance, utilising N+1redundancy with automatic switching and so forth). Neither of these provisionswould be economic for a single base-site, however they may well be justified at alarge BTS hoteling hub.

16 Introduction

1.6.3.2 Remote RF Head

The contents of the remote RF head (or RF black box of Figure 1.4) are similar tothose shown in Figure 1.2 and described in Section 1.5.2.1. The key difference hereis that a digital interface is added which is capable of longer transmission distancesthan that required in a typical base-station application (where only a few tens ofcentimeters of backplane or shielded cable are required). This interface is typicallyoptical for longer distances (see Figure 1.5), although twisted pair (e.g., CAT5) orcoaxial cables may also be used for in-building or shorter outdoor applications.

1.6.3.3 Advantages of BTS Hoteling

BTS hoteling is beginning to be deployed in trial networks by a number of opera-tors. They are interested in this technology as it yields a number of significantbenefits:

1. Simplification of maintenance/upgrades. Since the majority of the base-station equipment for a number of sites will be housed in one location, onlyone maintenance visit is required to cover all of these sites. At present, allsites must be visited individually.

2. Reduction/elimination of base-site huts and cabins. Aside from the capitaland maintenance cost of these buildings, they also add to planningdifficulties, due to the acoustic noise of the air conditioning systemspresently required by many of them (ignoring the aesthetic and healthconcerns of local residents, which can also impact upon planning decisionsin many markets). Enlarging a hut to house newer (e.g., 3G) equipment, inaddition to the existing 2G racks, generally involves a renegotiation with thesite landlord, and this can prove expensive (in some cases, around $75,000in legal fees alone!).

3. Reduced power consumption. Placing the RF elements at the top of thetower eliminates the cable losses inherent even in high-power coaxial cable.These losses are typically around 2 dB (but can be much higher), equating toa 37% reduction in power consumption (assuming that power requirementsscale with output power for the PA chosen).


Digitallineariser

DAC Upconverter PA

Diplexer

LNADownconverterADCDigitaldownconverter

Lineariser feedback

Opticalinput/output

Digital/opticalinterface

Figure 1.5 Internal structure of the RF black box concept.

4. Lower deployment costs. In addition to the cost benefits of a lower powerPA, the fact that the BTS now no longer requires a cabinet at the bottom ofthe tower will significantly reduce its build cost (and probably siteacquisition costs as well). Air conditioning also needs only to be provided ata single location, namely, the BTS hub.

5. Lower operating costs. The much greater (effective) efficiencies referred toabove, together with the removal of the need for air conditioning at a largenumber of remote sites, leads to a significant reduction in operational costs.This will amount to many millions of dollars per annum for a typicalEuropean 3G network.

6. Higher reliability. The removal of one BTS failure mechanism (thehigh-power coaxial cable) and the placement of much of the BTS hardwarein a benign air-conditioned environment will lead to an improvement inoverall system reliability. Also, the potential to use N+1 redundancy for theBTS elements contained in the hub site, means that any failures that do occurwill have a minimal impact upon the smooth running of the network.

7. Ease of maintenance. Placing the majority of the BTS hardware in onelocation allows central maintenance to be undertaken and possibly even24-hour manning. This will significantly reduce the time between a failureoccurring and its repair. If a failure occurs in the RF section, this should takeno longer to repair than at present for, for example, a cable failure (reputedto be more common than PA failure in most networks).

8. Ease-of-network expansion. In an existing network, adding a new sitetypically requires the acquisition of space for both an antenna and a groundcabinet. In a city centre, the former may be relatively readily available (e.g.,lampposts and traffic lights), with the latter being the bigger problem (due torestrictions on street furniture). If the only electronics to be deployed are thoserequired for the RF and this is now small (city centre deployments tend to below power), minimal or zero street furniture deployments may be possible.

1.7 Smart Antenna Systems

1.7.1 Introduction

A smart antenna system can bring significant benefits to both 2G and 3G networks.These benefits are principally in the areas of improved interference cancellation andin enhanced system capacity. These benefits do, however, come at a price with therequirements for multiple RF power amplifiers, armoured feed cables and calibra-tion systems adding significantly to the cost of this type of system. Although adap-tive antenna systems have been proposed and researched for some time, they haveyet to achieve widespread acceptance to date and this is largely because of their asso-ciated deployment and equipment costs. The advent of software defined radio archi-tectures is, however, a key development in enabling smart antenna base stations tobe realised utilising baseband beamforming. This type of architecture assists in miti-gating some of the cost, size, cabling, and calibration issues discussed earlier, bring-ing smart antenna systems closer to acceptance by network operators. It is still notclear, however, whether such systems will ever achieve a satisfactory business case.

18 Introduction

1.7.2 Smart Antenna System Architectures

A beam-steering smart antenna system operates by feeding gain and phase weightedversions of the same signal(s) to an array of antenna elements spaced, typically, halfa wavelength apart. The gain and phase weightings imposed on the signals fed toeach antenna element determine the direction of the beam and the beam pattern(i.e., the position of the sidelobes and nulls). All of these features may be controlledby the smart antenna system, allowing the wanted signals to be targeted by the mainlobe and any unwanted interferes minimised by steering a null (or multiple nulls) intheir direction(s).

Although some smart antenna deployments exist today, these are mainlyretro-fits to existing base stations (mostly in the United States) and utilisehigh-power gain/phase controllers to implement the beam-steering functionality. Inthe future, however, new deployments, are likely to be designed-in as a part of thebase station and these will almost certainly employ baseband beamforming in placeof the high-power Butler matrix [13] beamformers used at present. In a basebandbeamforming architecture, the gain and phase weightings, required to steering thebeam and its associated nulls, are formed within the digital signal processing func-tionality found at baseband. All that is then required of the transmitter andmulticarrier power amplifier (MCPA) is to faithfully reproduce these signals ashigh-power RF channels, without significant distortion (either linear—i.e.,gain/phase errors/ripple—or non-linear—i.e., IMD). The transmitter units musttherefore be highly linear (generating very little IM distortion) and have a flatfrequency response.

There are two main methods of realising a baseband beamforming smartantenna system:

1. Utilise conventional (e.g., feedforward) RF-input/output multicarrierpower amplifiers (MCPAs) in conjunction with a traditional transmitter/upconverter. A system designed in this way is illustrated in Figure 1.6. In thisconfiguration, the power amplifiers are mounted in the cabinet at the base ofthe mast and are cooled by fans and an overall air conditioning system forthe cabinet itself. The relative inefficiency of this type of amplifier and therequirement to overcome feeder losses in transmitting the signals to the topof the mast, both lead to the requirement for large amounts of heat to bedissipated.

2. Utilise a digital-input SDR transmitter of the type described earlier in thischapter (see Sections 1.5.2.1 and 1.6.3.2). The architecture for this solutionis shown in Figure 1.7. The base-station cabinet no longer contains the RFelements of the transmit chain, as these have now been moved to themasthead, along with the MCPA.

1.7.3 Power Consumption Issues

It is worth examining the power consumed in adopting each of these approaches.Consider, for example, a four-element adaptive array (arguably the smallest feasibledeployment) and a three-carrier WCDMA configuration. Assume that each carriermust be transmitted (from the BTS cabinet) at 10W (i.e., 15W at the output of the PA

1.7 Smart Antenna Systems 19

to allow for losses in the diplexer, connectors, and so forth) and that allowance ismade for the fact that the power from each antenna element sums to form the wantedbeam (i.e., each PA needs only to generate one-fourth of the total required power).

In the case of the architecture shown in Figure 1.6, the total transmitted power(from all of the MCPAs) is 45W, with the efficiency level being typically around10% (or less) for existing feedforward systems. This results in a total dissipatedpower of 450W, most of which must be removed by air conditioning.

In the case of the architecture shown in Figure 1.7, and assuming that the feedercable used in the above example has 2 dB of loss (typical for a 30-m cable run), thetotal MCPA output power required at the top of the mast, for equivalent coverage,

20 Introduction

Mast

Antenna elements

Ground cabinet

Basebanddigitalprocessing

DACs andupconversion

MCPA

High-powerRFcoax



MCPA



MCPA



MCPA

Network interface

Feedbackdownconverterand ADC(one requiredfor each antennaelement)

Low-powerRF coaxfeed (onerequired foreach antennaelement

Figure 1.6 Downlink smart antenna system based upon conventional multi-carrier poweramplifiers. Note that only one of the calibration feedback paths is shown, for simplicity—one isrequired for each antenna element.

has reduced to 28W. The efficiency of the MCPA will also have increased to over15% (based on the use of digital predistortion in the SDR transmitter), hence result-ing in a total system power dissipation of less than 190W. This represents a savingof 260W—close to 60%—over the architecture shown in Figure 1.6. This is clearlya very significant saving and is conservative (as an overall BTS system saving),since most smart antenna systems will use more than four elements and two orthree sectors.

1.7.4 Calibration Issues

A further issue, which separates the two architectures discussed earlier, is that of theadditional cabling required to maintain calibration for the complete system.

A smart antenna system relies on the faithful translation to RF of the gain andphase weights applied to the signals at baseband. Furthermore, it relies on each of theantenna elements receiving signals of the correct gain and phase weighting relative toeach other. This latter requirement typically necessitates periodic calibration of eachof the RF transmit/power amplification systems (of which there are four in the exam-ple shown in Figure 1.6). This will result in yet more cabling, as shown in that figure,in order to accommodate the feedback signals required from each antenna element.

1.7 Smart Antenna Systems 21

Mast

Antenna elements

Ground cabinet

Baseband digital processing

DACs and upconversion

MCPAs

Opticalfibre

Network interface

Figure 1.7 Downlink smart antenna base-station configuration employing digital poweramplification.

With an SDR transmitter-based solution, it is possible to lock each of thehigh-power transmitter units together (with one acting as the master), hence pre-serving their relative gain and phase properties without repeated calibration. Thissaves both RF signal processing hardware and multiple RF cables—both adding tocost and also, potentially, to reduced reliability.

1.8 Projects and Sources of Information on Software Defined Radio

1.8.1 SDR Forum

The SDR Forum [2] is an industry-based standards and promotional organisationwhich is “dedicated to supporting the development, deployment, and use of openarchitectures for advanced wireless systems.” It therefore aims to:

• Accelerate the proliferation of enabling software definable technologies neces-sary for the introduction of advanced devices and services for the wirelessInternet;

• Develop uniform requirements and standards for SDR technologies to extendthe capabilities of current and evolving wireless networks.

It consists of three work committees and these are outlined in the followingparagraphs.

1.8.1.1 Regulatory Committee

The charter for the Regulatory Committee states that its purpose is: “To promotethe development of a global regulatory framework supporting software downloadand reconfiguration mechanisms and technologies for SDR-enabled equipment andservices.”

1.8.1.2 Markets Committee

The charter for the Markets Committee states that it exists to “raise industry aware-ness through public relations activities, including published articles, press releasesand representation at industry trade shows; to increase and maintain Forum mem-bership; and to collect and analyse market data on all industry segments.”

1.8.1.3 Technical Committee

The charter for the Technical Committee states that it exists to “promote theadvancement of software-defined radios by using focused working groups todevelop open architecture specifications of hardware and software structures.”

Within the Technical Committee there are three working groups:

1. Download/Handheld: Charter—To promote the use of software-definedradio technology in handheld terminals, providing dynamic reconfigurationunder severe constraints on size, weight, and power.

22 Introduction

2. Base Station/Smart Antennas: Charter—To promote the use of software-defined radio and reconfigurable adaptive processing technology in wirelessbase stations worldwide for terrestrial, satellite, mobile, and fixed services.

3. Mobile: Charter—To promote the use of software defined radio technologyin commercial and military applications where station mobility, dynamicnetworking, and functional flexibility are required. Identify and maintainthe collection of recommended wireless, network and application interfacestandards to meet these objectives. Develop and promulgate new standardsas necessary.

1.8.2 World Wide Research Forum (WWRF)

Working group 6 of this forum is undertaking activities dealing withreconfigurability and is taking inputs from (amongst others) the U.K. Mobile Vir-tual Centre of Excellence (MVCE) [14].

1.8.3 European Projects

Over the last few years, a number of European projects have also been focused onvarious aspects of software defined radio technology, including:

• SLATS [15];• FIRST [16];• SUNBEAM [17];• CAST [18];• MOBIVAS [19];• WINDFLEX [20];• WINE [21];• PASTORAL [22];• DRIVE [23];• MuMoR [24];• SODERA [25, 26];• SCOUT [27];• TRUST [28, 29].

Note that this list is in roughly chronological order and is not exhaustive.Each of these projects has examined slightly different aspects of SDR, incorpo-

rating both techniques, such as software download and dynamic reconfigurationand technology, such as multiband transmitter and receiver architectures. Whilenone of the above projects is intended to generate standards or guidelines (unlikethe SDR Forum, discussed earlier), they have generated technology in the soft-ware-defined radio area and all have informed standards in their respectivefields—generally through European Technical Standards Institute (ETSI)submissions.

1.8 Projects and Sources of Information on Software Defined Radio 23

References

[1] Kenington, P. B., “Linearised Transmitters: An Enabling Technology for Software DefinedRadio”, IEEE Communications Magazine, Vol. 40, No. 2, February 2002, pp. 156–162.

[2] http://www.sdrforum.org.[3] Lackey, R. J., and D. W. Upmal, “SPEAKEasy: The Military Software Radio”, IEEE Com-

munications Magazine, Vol. 33, May 1995, pp. 56–61.[4] DaSilva’s, J. S., “It Is Dangerous to Put Limits on Wireless”, 3GIS Conference, Athens,

Greece, July 2–3, 2001; http://www.cordis.lu/ist/ka4/mobile/pubar/past/ec_pres_2001.htm.[5] Kenington, P. B., “Dynamic Channel Multicarrier Architecture (DC/MA)-An Ideal Solution

for Asia”, Proc. of 2nd Annual Asia Pacific Public & Private Trunked Mobile Radio Confer-ence ‘96, Singapore, August 26–28, 1996.

[6] “Radio Equipment and Systems (RES); Land Mobile Service; Technical Characteristics andTest Conditions for Radio Equipment Intended for Transmission of Data (and Speech) andHaving an External Connector”, ETSI, European Telecommunication Standard (ETS) 300113, 1999.

[7] http://www.fairfield.com/Boxhome.html.[8] http://www.ose.com.[9] Moore, G. E., “Cramming More Components onto Integrated Circuits”, Electronics, Vol.

38, No. 8, April 19, 1965.[10] http://www.obsai.org.[11] http://www.cpri.info.[12] http://www.andrew.com.[13] Butler, J., and R. Lowe, “Beam-Forming Matrix Simplifies Design of Electronically Scanned

Antennas”, Electronic Design, April 12, 1961, pp. 170–173.[14] Georganopoulos, N., et al., “Terminal-Centric View of Software Reconfigurable System

Architecture and Enabling Components and Technologies”, IEEE Communications Maga-zine, Vol. 42, No. 5, May 2004, pp. 100–110.

[15] http://www.csem.ch/slats/project.html.[16] http://www.cordis.lu/infowin/acts/rus/projects/ac005.htm.[17] http://www.cordis.lu/infowin/acts/rus/projects/ac347.htm.[18] http://www.cast5.freeserve.co.uk/.[19] http://www.ccrle.nec.de/Projects/mobivas.htm.[20] http://labreti.ing.uniroma1.it/windflex/.[21] http://www.vtt.fi/ele/projects/wine/.[22] http://pastoral.telecomitalialab.com/.[23] http://www.ist-drive.org/index2.html.[24] http://www.ee.surrey.ac.uk/CCSR/IST/Mumor/.[25] http://dbs.cordis.lu/fep-cgi/srchidadb?ACTION=D&SESSION=113462004-4-8&DOC=1

&TBL=EN_PROJ&RCN=EP_RCN_A:57124&CALLER=PROJ_FP5 (or search for pro-ject number: IST-1999-11243 in the Cordis database).

[26] http://www.bbw.admin.ch/html/pages/abstracts/html/fp/fp5/5is99.0336-1.html.[27] http://www.ist-scout.org.[28] http://dbs.cordis.lu/fep-cgi/srchidadb?ACTION=D&SESSION=122992004-4-8&DOC=1

21&TBL=EN_PROJ&RCN=EP_RPG:IST-1999-12070&CALLER=PROJ_IST (or searchfor project number: IST-1999-12070 in the Cordis database).

[29] http://www4.in.tum.de/~scout/trust_webpage_src/trust_frameset.html.

24 Introduction

C H A P T E R 2

Basic Architecture of a Software DefinedRadio

2.1 Software Defined Radio Architectures

A software defined radio (SDR) is a form of transceiver in which ideally all aspectsof its operation are determined using versatile, general-purpose hardware whoseconfiguration is under software control. This is often thought of in terms of base-band DSPs, hence the term software radio, which is often used to describe this typeof system; however, FPGAs, ASICs (containing a re-programmable element, e.g., anembedded processor), massively parallel processor arrays, and other techniques arealso applicable. The more general terms flexible architecture radio (FAR) and soft-ware defined radio (SDR) are therefore becoming increasingly adopted. Althoughnot strictly necessary, in order to be termed software defined, this type of radio isalso commonly assumed to be broadband (multi-band or multi-frequency in opera-tion). This assumption is made, as one of the principal applications of this type oftransceiver is perceived to that of replacing the numerous handsets currentlyrequired to guarantee cellular (and in the future, satellite) operation worldwide.Even with the GSM system having achieved a certain degree of ubiquity worldwide,it is still not possible to utilise a single handset in all countries (with cellular cover-age) worldwide. Furthermore, the many competing standards (GSM, CDMA,WCDMA, AMPS, D-AMPS, PDC) all have differing characteristics, tariffs, and soforth, and hence a multi-mode, multi-band transceiver, covering all of thesesystems, would certainly be a useful device.

The concept of a multi-band or general coverage terminal is, strictly speaking,an extension of the basic software defined radio concept into that of a broadbandflexible architecture radio, since the basic reprogrammability and adaptabilityaspects of operation do not depend upon multi-band coverage. It would be possible,for example, to construct a useful software defined radio which operated in the800-/900-MHz area of spectrum and which could adapt between AMPS, GSM,DAMPS, PDC, and CDMA. It is now normal, however, for a handset to havemulti-frequency operation and hence the extension of this principle to a softwaredefined radio is a natural one. The international business traveller market isstill seen as both large and lucrative, particularly in terms of call charges, hencemaking this type of handset attractive to both manufacturers and networkproviders.

There are many issues which must be addressed in determining if a software-defined radio is realistic and also to what extent it is flexible. For example, it is pos-sible to create a single-band software defined radio with a narrowband channel

25

restriction relatively easily [1]. Coping with wider channel bandwidths and operat-ing in multiple bands in differing parts of the spectrum is much more difficult, butnevertheless essential, for a combined GSM/PCS/WCDMA handset, for example.

What this chapter aims to do is to examine the simplest possible architecture foran SDR and then to demonstrate why this will not be feasible, for most applications,for some time to come (if ever, in some cases). The remainder of this book will thengo on to describe the more complex, but more realistic, architectures in use today (orpotentially usable in the near future).

2.2 Ideal Software Defined Radio Architecture

An ideal software defined radio is shown in Figure 2.1; note that the A/D converteris assumed to have a built-in anti-alias filter and that the D/A is assumed to have abuilt-in reconstruction filter. The ideal software defined radio has the followingfeatures:

• The modulation scheme, channelisation, protocols, and equalisation for trans-mit and receive are all determined in software within the digital processingsubsystem. This is shown containing a DSP in Figure 2.1; however, as washighlighted earlier, there exists a variety of applicable signal processing hard-ware solutions for this element.

• The ideal circulator is used to separate the transmit and receive path signals,without the usual frequency restrictions placed upon this function when usingfilter-based solutions (e.g., a conventional diplexer). This component relies onideal (perfect) matching between itself and the antenna and power amplifierimpedances and so is unrealistic in practice, based upon typical trans-

26 Basic Architecture of a Software Defined Radio

High-linearity,high-efficiencyRF PA

DSP

Digital processingsubsystem

RF-outputDAC

D/A

RF-inputADC

A/D

Idealcirculator

Transmit/receiveantenna

Figure 2.1 Ideal software defined radio architecture.

mit/receive isolation requirements. Since the primary alternative (a diplexer)is very much a fixed-frequency component within a radio, its elimination is akey element in a multi-band or even multi-standard radio. Some potentialtechniques for solving this problem are proposed elsewhere in this book. Notethat the circulator would also have to be very broadband, which most currentdesigns are not.

• The linear (or linearised) power amplifier ensures an ideal transfer of the RFmodulation from the DAC to a high-power signal suitable for transmission,with low (ideally no) adjacent channel emissions. Note that this functioncould also be provided by an RF synthesis technique, in which case the DACand power amplifier functions would effectively be combined into a singlehigh-power RF synthesis block.

• Anti-alias and reconstruction filtering is clearly required in this architecture(but is not shown in Figure 2.1). It should, however, be relatively straightfor-ward to implement, assuming that the ADC and DAC have sampling rates ofmany gigahertz. Current transmit, receive, and duplex filtering can achieveexcellent roll-off rates in both handportable and (especially) base-stationdesigns. The main change would be in transforming them from bandpass(where relevant) to lowpass designs.

2.3 Required Hardware Specifications

The ideal hardware architecture, shown in Figure 2.1, imposes some difficult speci-fications upon each of the elements in the system. It is worth examining each ofthese specifications in detail, in order to judge the likelihood of technologicaladvancement over the coming years making them a realistic proposition. This willthen provide a backdrop to the techniques presented in the remainder of this bookand their applicability to particular standards or systems.

In order to derive these specifications, it is necessary to make some assumptionsabout the types of modulation scheme (and in some cases, multiple access scheme)which the radio is likely to need to accommodate. If these assumptions are based oncurrent and currently proposed schemes for cellular and PMR systems worldwide,the specifications shown in Table 2.1 could be chosen. Note that many other vari-ants of these requirements are possible and that Table 2.1 represents only one(hopefully realistic) collection of values.

The specifications outlined in Table 2.1 highlight some key difficulties in realis-ing a transceiver capable of meeting these requirements, over a broad coveragerange. These may be summarised as follows:

1. Antenna: A frequency range of almost 5 octaves is required, together with arealistic gain/loss figure around 0 dBi. Combine this with the usual (handset)requirements of small size, near-omnidirectional coverage pattern (typically,excluding the users head), and low cost, and the physical realisation of thiscomponent becomes extremely challenging.

2. Circulator or duplexer: This is discussed in more detail later in this book;however, it needs high isolation and a broadband coverage range. In the case

2.3 Required Hardware Specifications 27

of a conventional, filter-based duplexer, this latter requirement is essentiallyimpossible to achieve with current technologies.

3. A/D converter: The sampling rate of this converter, if it is to Nyquist sampledirectly at RF, would need to be at least 4.4 GHz and, in reality, much more(to allow for a realistic anti-alias filter roll-off and real-world converterperformance). If, however, the converter is permitted to undersample, therequired sampling rate drops dramatically. The required sampling rate couldfall to 20 MSPS (based on two-times Nyquist bandpass sampling), assumingthat the RF filtering and ADC analogue input were up to the task (asignificant challenge in the former case). This would lead to an inputbandwidth requirement extending to 2.2 GHz and a resolution of around 20bits (from the receiver dynamic range requirement1). Even this is anextremely exacting specification, particularly with current technology, andhence the alternative architectures, covered in Chapters 3 through 6, arerequired to allow a realisable A/D converter to be used.

Note that if a synthesizer and conventional downconversion are employed(in place of bandpass sampling), this resolution is available at very low costin the form of digital audio converters. Up to 200 kHz of channel bandwidthcan be accommodated in this way, relatively easily and cheaply (based on I/Qdownconversion prior to the A/D converters). At the time of this writing,


Table 2.1 Basic Specifications for a Handportable Software Defined Radio

Parameter Value NotesFrequency coverage 100 MHz−2.2 GHz This would cover most PMR, cellular,

PCN/PCS, mobile satellite, and UMTS bandsworldwide.

Receiver dynamic range 0 dBm to −120 dBm(based on a 25-kHzequivalent channelbandwidth)

This must not only cope with fading and in-band interferers, but any signals in the abovefrequency range.

Transmit power output 1W This is reducing as time progresses and healthfears increase, but most systems still require thispower level (many PMR systems require more).

Transmit adjacent channel power −75 dBc This figure is slightly in excess of most knownspecifications in this area (e.g., TETRA [2]).

Transmit power control range 70 dB Most CDMA systems, for example, require alarge power control range.

Transmit power ramping range 75 dB DECT [3] requires 68 dB and is probably thetoughest current requirement in this area.

Channel bandwidth 5 MHz Based on the 3GPP WCDMA standard forUMTS [4].

Receiver image rejection 60 dB Based on an interpretation of the TETRA [2]specifications.

Source: [1].

1. Even a 5-MHz receiver bandwidth (based on the above 20-MSPS sampling) can be swamped by one or morenarrowband carriers, when operating in, for example, the GSM bands. The full receiver dynamic range istherefore (ideally) required from the ADC.

16-bit converters are becoming available with an appropriate sample rateand the trend is for converters to have increasing analogue bandwidths (>1GHz is now emerging as a specification in a number of parts); it thereforeseems likely that this requirement will be realisable within the next 5 to 10years (although power consumption is likely to be a concern; see Section2.5.1).

4. D/A converter: This component is currently realisable, although with arelatively high power consumption, again assuming that conventionalupconversion is employed and that power control is employed either prior toor within the linear power amplifier. A resolution of 12 to 14 bits at 20MSPS would be required. IF output devices are also now increasinglycommon and the available IFs are increasing as technology improves.Current devices are capable of operation at an IF in the hundreds ofmegahertz region; however, here again, this will improve over the comingfew years to the point where RF output frequencies (e.g., 800/900 MHz and1.9/2.1 GHz) will become a reality, at a realistic cost.

5. Receiver anti-alias filtering: Based on the two-times Nyquist samplingconverters discussed above, an attenuation of 60 dB is required around 18MHz from the channel edge. This would be extremely difficult, if notimpossible, to achieve in a bandpass filter capable of tuning from 100 MHzto 2.2 GHz. With the architecture proposed in Figure 2.1, this componentpresents a serious challenge and strongly indicates that a synthesiser-baseddownconversion mechanism would almost certainly need to be employed ina software defined radio for the foreseeable future. Improvements insampling rates (for a given converter resolution) will, however, allow thisrequirement to be relaxed and may enable some limited forms of SDR to berealised without such high-performance filtering needing to be included.

6. DSP (DSP processors and equivalent technologies): Technology in this areais progressing very rapidly and the primary issue at present is that of powerconsumption (for handset operation). Combinations of reconfigurablehardware (e.g., FPGAs) and fully software programmable processors arelikely to yield the best performance in terms of power consumption, althoughother, newer architectures are also strong challengers in this area (e.g.,massively parallel arrays). These technologies are discussed in Section 2.4.

7. RF power amplifier: Considerable research has been directed at thelinearisation of power amplifiers in recent years and a number of candidatetechniques exist (see Chapter 6). Many narrowband systems have employedthe Cartesian loop technique, achieving up to −70-dBc intermodulationproduct levels. For broader bandwidth systems, RF predistortion, digitalpredistortion, and feedforward techniques have also been used. At present,digital predistortion is a realisable solution and fits well with thearchitecture of a software defined radio. In particular, it is now increasinglyemployed in base-station equipment [5]. In the future, however, RFsynthesis architectures, such as envelope restoration and sigma-deltatechniques, may well also see widespread application.

2.3 Required Hardware Specifications 29

The specifications outlined in Table 2.1 and the components required to realisethem are clearly not available with current technology and may not be achievable, inmany cases, for a considerable period (if ever). It is therefore necessary to examineother architectures and/or restrictions in the specifications contained in Table 2.1, inorder for software defined radio to become a reality in the short or medium term.Such architectures are dealt with in detail in the remaining chapters of this book.

2.4 Digital Aspects of a Software Defined Radio

2.4.1 Digital Hardware

There exists a range of solutions to the digital processing problem for a softwaredefined radio, each with its own characteristics and application areas. The digitalprocessing area is, in many respects, as challenging as the analogue processingdescribed in detail in this book and the intention of this section is merely to highlightthe options and their main characteristics. The two biggest issues at present are thepower consumption and cost of the various options. In a base-station application,these are less of an issue (but are still a significant challenge); however, they are per-haps the main inhibitor to the widespread used of software defined radio in handsetsand other portable devices.

The arguments for and against (largely against) the provision of large amountsof reconfigurable processing in a base station (as a future-proofing method) havealready been covered in Chapter 1. The use of reconfigurability as a method of pro-viding upgrading, improvement, or backwards compatibility (i.e., a smooth transi-tion from a legacy system) is, however, a strong argument for flexible processing andSDR concepts. It is in this context that the processing options outlined in thefollowing will be discussed.

Cost is also a multi-faceted issue. Most designs judge cost based almost exclu-sively on the cost of the target device used for the code (be it a processor or anFPGA). In the case of a very high-volume application (e.g., a handset), this might bea reasonable approach, although even here it could be somewhat shortsighted. In thecase of a base-station design, however, there are many other considerations that willdetermine the overall cost of a design (particularly if lifetime cost is considered andnot just purchase cost). As a summary, the factors that influence the cost of the digi-tal elements of an SDR BTS include:

• Direct cost of the processing device itself.• Costs involved in the associated ancillary and interfacing devices (e.g., mem-

ory, clock circuitry, and so forth)• Non-recurring expense (NRE). This is most obviously associated with ASIC

or application specific signal processor (ASSP) designs and includes mask-setcosts, fabrication, and so forth. These costs are rising dramatically as featuresizes reduce and are therefore making the break-even volume (compared to,say, FPGAs) much higher as time progresses.

• Tools/training investment. Changing from one digital technology to another(e.g., from DSPs to FPGAs) may well involve a significant change of design


personnel, or at the very least a degree of retraining. This will have an associ-ated cost and also an opportunity cost as the time to market will be increased(see the following). Even changing from one manufacturer’s processors toanother may involve a loss of productivity while the development team famil-iarizes itself with a new feature set and the new tricks required to get the bestout of a particular device.

• Cooling. The cost of cooling can undergo step changes as the form of coolingrequired changes. The most obvious example is in going from convectioncooling to forced-air cooling, with the cost of the fans now needing to beadded to the bill of materials. Additional power consumption will also add tothe cost of the power supply, although with modern switched-mode designs,this is usually small. It is, however, a much bigger issue in handset designs dueto the increased requirements it places upon the battery and the user accep-tance issues of large batteries or reduced talk times.

• Development time/resource. This is becoming an increasingly importantaspect of cost, as product life cycles, even of base-station designs, reduce aseach new design appears. The volume of units sold of a particular design isthen lower and the cost of producing that design becomes an ever-larger pro-portion of its selling price. Techniques or architectures which allow thesedesigns to be generated quickly, or significant portions of designs to be reusedbetween evolutionary models in a range (as well as across models in a givenrange), are clearly attractive, even if the devices upon which they are based arenot the lowest-cost components available.

• Flexibility. This is a benefit in terms of time to market for new products andhence a benefit in terms of opportunity cost. If full flexibility could be pro-vided for the same cost as a fixed solution (e.g., a single-application ASIC),then it would be a simple decision to adopt a flexible approach. This is almostnever true and hence a full business case must be developed for flexibility, in agiven marketplace, and each opportunity judged on its merits.

2.4.1.1 Digital Signal Processors (DSPs)

DSPs were arguably the original enabling technology for software defined radio(other than perhaps in military circles where cost is less important). They have theadvantage of complete flexibility, wide applicability, and a wide availability ofskilled practitioners in their software. They are also high-volume devices and hencethe benefits of economies of scale may be realised across a large number of applica-tions in a wide range of industries (not just wireless communications). This, in gen-eral, makes up for their lack of optimisation for a given specific project or nicheapplication area, and allows them to be a realistic option for early prototyping andinitial production volumes of a new design, as well as for the final volume product,in some cases.

They are best suited to the less computationally intensive forms of signal pro-cessing, rather than very high-speed front-end applications. They are often utilisedfor involved, off-line processing of data which has been acquired and undergone ini-tial processing/storage by a different type of device (e.g., an FPGA or an ASIC).

2.4 Digital Aspects of a Software Defined Radio 31

They are, however, well supported and also tend to come in backwards-compatiblefamilies, which allow development to take place on a state-of-the-art (SOTA)device, with the final application device being lower cost. This generally occurs fortwo reasons:

1. The SOTA device being used in development will not be SOTA by the end ofthe development cycle and hence will generally have reduced in cost. Thevolume of usage of the device will also have increased, which will also help toreduce its cost.

2. Developers tend to pick a device for their development systems which isdefinitely large enough to meet the requirement in question. It is often thecase that once development is nearing completion, the design will have beenoptimized such that it may be executed in a lesser member of the same devicefamily. This will have an associated cost benefit. In larger systems, it may bethe number of devices that can be reduced; however, this will still result in alower overall cost.

2.4.1.2 Field-Programmable Gate Arrays (FPGAs)

FPGAs have undergone a revolution in recent years, both in performance and cost.From humble beginnings as simple, flexible glue logic in complex digital designs,they are now a credible processing platform in their own right and able to rival ASICsolutions in many areas (and act as a low-cost prototyping mechanism for ASICdesigns). They have also undergone a revolution in volume pricing, which meansthat they are no longer consigned to the prototype and initial volume parts of theproduct life cycle, but can now be used throughout volume production, in someapplications. It is also possible to convert from an FPGA to a quasi-ASIC, with ahigh-degree of confidence of success and a relatively low NRE (and hencebreak-even volume). FPGAs are therefore challenging and displacing ASICs intraditional ASIC application areas.

Furthermore, they provide much more flexibility than can be cost-effectivelybuilt into an ASIC, thereby fitting with the requirements of SDR very well. In com-mon with DSPs, they also tend to come in families, thereby, again, allowing an ini-tial design to take place on a large (potentially overspecified) device with the finaldevice being chosen to just fit the processing requirement.

It is also possible (but not necessarily economic) to add IP processor cores intoan FPGA (or an FPGA-derived ASIC). This makes possible a single-chip solution insome applications and this may be important for size or reliability reasons (with theimproved reliability coming from the reduction in devices and soldered joints).

2.4.1.3 ASICs

The main issue with utilising ASICs [or, more correctly, application-specific signalprocessors (ASSPs)] within an SDR system, lies in their lack of flexibility (or con-versely, the cost of adding flexibility). There are many methods by which flexibilitymay be introduced within an ASSP, and these include:


• Provision of multiple toolbox functions with flexible input parameters. Anexample would be a QAM modulator that had an input variable to configureit from 16 to 256 QAM, for example.

• Provision of hardware for all current modulation formats, coding schemes,and so forth in a single (large!) ASSP, with the ability to select between the dif-ferent paths. This is not strictly flexible in the generic sense; however, it is flex-ible in its range of functionality—the user will not care how he is providedwith service over a range of standards, just that he obtains service at a lowcost. The major disadvantage with this option is that it is not reallyfuture-proof, unless the system designer has an extraordinary insight into thefuture trend in mobile communications (and can convince his or her manage-ment that he or she is right).

• A combination of one or both of the above with some programmable DSPfunctionality (e.g., using an embedded DSP core). The key here is in providingenough DSP power to be useful and provide a degree of future-proofing, with-out designing essentially a DSP device—it would almost certainly be lowercost to buy an off-the-shelf DSP device from a volume vendor.

Development and fabrication costs are also a major consideration in choosingan ASSP route. For example, the break-even costs in going from a 180-nm to a90-nm feature size increase by a huge factor (between 10 and 100 times). This has adramatic effect on the business case for an ASSP development.

2.4.2 Alternative Digital Processing Options for BTS Applications

2.4.2.1 Enhanced FPGAs

This type of digital processing option, also known as a configurable computingmachine (CCM) [6], essentially adds some application-specific functional blocks orarchitectural constructs to a standard FPGA device, as a method of providing tailor-ing or optimisation for a specific market segment (e.g., wireless). There are a num-ber of options within this category and these are mostly tailored (in design goals, atleast) toward handset applications. These are summarised in Section 2.4.3.

2.4.2.2 Programmable Application-Specific Standard Product (P-ASSP)

This type of processor consists of a general-purpose core that is supplemented by arange of functionally optimized coprocessors or kernels. These latter elements areoptimized for specific signal processing functions, such as equalisation, and allowthe commonly used wireless signal processing functions to be implemented in a moreoptimal manner than would be the case by utilising purely a general-purpose DSP.

An example of this type of device is that of the Wireless Systems Processordesigned by Morphics [7]. In this processor, multiple devices process differentaspects of the signal-processing task in parallel, with dedicated processing elementsbeing targeted at particular parts of the problem. This provides an optimised, yetflexible, architecture and hence is a good compromise solution. It does, however,rely on the IC system designer accurately predicting which functional elements will


be required in a range of current and future applications. This is clearly a difficultthing to predict and hence the flexibility of this device will be limited for futureapplications and the degree of future-proofing it affords is likely to be small. Withthe design life cycle for a BTS becoming ever shorter, however, this may not be amajor issue in practice.

2.4.2.3 Massively Parallel Processor Arrays

A massively parallel array is a processor array consisting of a large number of pro-cessors connected by very high-speed on-chip interconnect. Each processor has acomparatively modest processing capability on its own (compared to, say, a singlededicated DSP chip) and is assigned a portion of the overall signal-processing prob-lem. The idea behind this approach is that the available processing power (and hencesilicon) is used most efficiently, thereby extracting the optimum performance from agiven unit of cost or power consumption.

This process does, however, rely on the interchip communication overhead notbecoming a significant use of processor resource. It also relies on fast interprocessorcommunication and on a good mapping of the signal-processing problem across thearray of processors. This mapping process is usually undertaken by a specialist tooland hence requires the digital processing engineers to undergo retraining in a verydifferent way of performing their signal processing designs. This can extend the timeto market for an initial design and is also risky, since this type of processor is cur-rently only manufactured by small companies (e.g., picoChip [8]). If such a companywas to fail, a manufacturer could be left with a large amount of (expensive,non-standard) IP that would then have to be rewritten for an alternative signal pro-cessing solution. This problem is common (to varying degrees) to most of the newerprocessing technologies discussed here.

2.4.2.4 Reconfigurable Compute Fabric

The Reconfigurable Compute Fabric (RCF) device from Freescale Semiconductor isan attempt to provide the benefits of a programmable signal-processing solution, ata cost level and power consumption close to that of an ASIC-based (or ASSP-based)solution. A single device combines a number of RCF cores (six in an MRC6011) intoa single computing node. It claims a peak performance of 24 Giga complex calcula-tions per second, for I and Q signals, at 8-bit resolution [9]. The device has a powerconsumption of around 3W and is therefore only suitable for infrastructureapplications (at present).

Each RCF core contains the following functions:

1. RISC processor with instruction and data cache;2. Reconfigurable computing array of 16 cells, each containing: a pipelined

multiply-accumulate (MAC) unit; arithmetic, logic, and conditioning units;and a special-purpose complex correlation unit;

3. Large input/output buffers;4. Single and burst transfer DMA controller.


The device claims that the RISC processor is optimised for efficient C-code com-pilation—an important element in ensuring that designs are portable and low-risk(from a device availability perspective).

2.4.3 Alternative Digital Processing Options for Handset Applications

Research and development activity is underway, both in academia and in a numberof start-up companies, examining ways of achieving reconfigurability and flexibilityin baseband processing, while maintaining a low power consumption. This sectionoutlines a number of these activities, both academic and commercial, as it is notclear which (if any) will become successful solutions for SDR handset applications.

2.4.3.1 Garp

The Garp architecture was designed by the University of California at Berkeley as areconfigurable accelerator for use with general-purpose processors. It aims to solvethe problems of long reconfiguration times and low data bandwidths, which haveproved to be a deterrent for designers wishing to utilise reconfigurable computingtechniques. The Garp architecture, shown in Figure 2.2, combines both a standardprocessor and a reconfigurable hardware array, with reconfiguration costing only afew cycles of overhead. It has direct access to memory from the reconfigurable coreitself, with the standard processor being capable of operating at 1 million instruc-tions per second (1 MIP)—although the overall device operates at a clock speed ofonly 100 MHz.

The reconfigurable hardware within Garp consists of combinatorial logicblocks and programmable wiring (similar to FPGAs), with explicit move instruc-tions from the processor being required to move data between the processor andhardware array. Garp also features a high-level compiler, which can extract C-code


Memory

Instruction cache Data cache

Standard processor Configurable array

Figure 2.2 Garp processor architecture [10].

instructions and automatically implement sections of code with a high degree ofinstruction-level parallelism (ILP).

Although Garp was not designed explicitly for SDR applications, it containsmany of the features that are desirable in SDR applications (e.g., direct memoryaccess, hardware-to-processor transfer via memory, thereby keeping I/Obandwidths low). The main features which would need to be added to Garp, for anSDR application, revolve around the DSP and communications functionality forwhich the processor would need to be tailored.

2.4.3.2 Algorithm-Specific Instruction Set Processor (ASIP)

This hardware architecture moves away from the general-purpose reconfigurabledevice idea, realising that a more efficient approach is to utilise prior knowledge ofthe various standards in order to tailor a hardware accelerator. This accelerator canthen perform the highly computationally intensive tasks, required in a specific appli-cation, alongside a general-purpose DSP [11]. The architecture of this device isshown in Figure 2.3.

The ASIP hardware accelerator itself consists of a number of processing ele-ments, with each being designed to execute a specific class of algorithm (e.g., lineartransformations, orthogonal transformations, and so forth). The accelerator sharesa common bus with the DSP and any RAM and I/O modules present. These elementsmay be utilised more than once to compute a particular result (e.g., two passesthrough an 8-tap FIR to obtain a 16-tap FIR), with the intermediate results beingstored in RAM.

The configuration RAM provides both read addresses for the processing ele-ment data RAM and configuration instructions for the processing element itself. Afinite state machine provides the write addresses to the processing elements. The


Bus interfaceincluding DMA

Systembus

Configuration RAM Finitestatemachine

Data ram

Read addresses

Processingelement 1

Processingelement 2

Writeaddresses

Input Input

Output Output

µ/DSP

Figure 2.3 Architecture of the ASIP hardware accelerator [6].

ASIP can therefore operate stand-alone, executing loops as required and can use aninterrupt and direct memory access to supply results back to the DSP.

2.4.3.3 Field Programmable Function Array (FPFA)

The FPFA structure [12] forms part of a reconfigurable hardware platform, whichalso consists of FPGA and general-purpose processor (ARM core) elements. TheFPGA elements are intended for bit-wise functions (e.g., P-N code generation) andthe general-purpose processor for control functions (e.g., if/then or while/do loops).

The FPFA itself is intended for use in repetitive calculations within loops and forcomputationally intensive DSP tasks—particularly those involving a regular struc-ture. It consists of a number of processor tiles, as shown in Figure 2.4, each of whichhouses a number of simple processing elements, complete with its own instructionstream. This allows a large number of tasks to run in parallel and also improves theoverall chip clock speed and energy consumption. The basic architecture of a pro-cessor tile is outlined in Figure 2.5.

Each processor tile consists of a number of reconfigurable ALUs (five in the caseof Figure 2.5), with local memory, a control unit and a configuration unit. TheALUs are intended to execute the inner loops contained within a particular applica-tion and load their operands from neighbouring ALU outputs, local registers, or val-ues stored in a look-up table. Reconfiguration of the tile is enabled by storing theALU configuration in local memory.

In some respects this reconfigurable hardware concept is similar to that of themassively parallel processor array discussed in Section 2.4.2.3. A similar mapping


ProcessorTile

ProcessorTile

ProcessorTile

ProcessorTile

ProcessorTile

ProcessorTile

ProcessorTile

ProcessorTile

ProcessorTile

ProcessorTile

ProcessorTile

ProcessorTile

ProcessorTile

ProcessorTile

ProcessorTile

ProcessorTile

ProcessorTile

ProcessorTile

ProcessorTile

ProcessorTile

ProcessorTile

ProcessorTile

ProcessorTile

ProcessorTile

ProcessorTile

Figure 2.4 Architecture of an FPFA [12].

of the computational problem onto the processor array must also take place, with asimilar compromise between granularity (in terms of processor size/capability) andcommunications overhead, needing to be struck.

2.4.3.4 Raw

The Raw processor from Massachusetts Institute of Technology (MIT) [6] consistsof 16 identical programmable tiles (see Figures 2.6 and 2.7), each of which connectsonly to its four neighbours and consists of the following elements:

• A static communication router;• Two dynamic communication routers;• An eight-stage, in-order, MIPS-style processor;• A four-stage pipelined floating point unit;• A 32-kB data cache;• 96 kB of software-managed instruction cache.


Communication andreconfiguration unit

Control unit

Program memoryALU

Mem Mem

ALU

Mem Mem

ALU

Mem Mem

ALU

Mem Mem

ALU

Mem Mem

Figure 2.5 Internal architecture of a processor tile within a field programmable function array [12].

Raw Tile Raw Tile Raw Tile Raw Tile




Figure 2.6 Architecture of MIT’s Raw microprocessor [6].

The primary benefit of the Raw device architecture is that it can achieveASIC-like levels of latency from a reprogrammable processor. This is possiblebecause the interconnection between computational units within a microprocessoris exposed to the instruction set. The programmer is therefore given the ability toknow where the instruction will be physically executed and the number of transi-tions that are needed between tiles in order for it to be carried out. This permits thecompiler to control the transfer of data between tiles, in a similar manner to thatwhich occurs in an ASIC, and to enable tasks to run in parallel on different tiles.Through the ability to provide run-time reconfiguration, enabled by the dynamiccontrol of the system’s computational resources by software, the Raw processor istherefore able to provide ASIC-like levels of latency. It also provides some of thedesirable characteristics required by an SDR application, although power consump-tion also needs to be kept to a minimum for handset applications.

2.4.3.5 Stallion

The Stallion processor from Virginia Tech utilises stream-based processing in orderto realize a flexible, high-throughput, low power configurable computing machine.The concept of stream-based processing involves having a common port for bothprocessing and data packets, with a packet header indicating the type of packetbeing sent and the module to which subsequent packets should be routed.


Computeresources

Programmablerouters

32-bit full-duplexnetwork link To/from adjacent tile

To/from adjacent tile

To/fromadjacenttile

To/fromadjacenttile

Figure 2.7 Internal architecture of a Raw processor tile [6].

Although not specifically designed for low-power wireless communicationsdevices, simulations have shown that reasonable power consumption may beobtained from this architecture [13].

2.4.3.6 Adaptive Computing Machine (ACM)

This device, developed by Quicksilver Technology [14], is shown in Figure 2.8. It isan attempt to provide the computing flexibility of a DSP with the power consump-tion of an ASIC and is targeted primarily at handset applications, where power con-sumption is of paramount importance. It could be considered as an enhanced FPGAin that it has the ability to utilise on-board programmable logic to optimise the gaterequirement needed to fulfil a particular signal processing function, however unlikean FPGA it can reconfigure this functionality very rapidly. It also has the ability tocreate a custom data-path that will exactly fit the optimum instruction sequence,required to implement a given algorithm. This data path design can be stored in soft-ware and quickly downloaded, with the result that regular hardware optimisationcan occur, thereby cutting the number of execution cycles required for a given task.

Each node in Figure 2.8(a) consists of a number of computational units, witheach having its own local memory and a configuration memory element. A node isself-sufficient and can execute algorithms that are downloaded in the form of binaryfiles. The nodes are connected through a Matrix Interconnect Network (MIN),which carries data, control information and the binary algorithm files. Each ACM isalso market-specific, with the collection of node types on a given piece of siliconbeing determined by the needs of a particular market segment. Such a tailoredapproach avoids the one-size-fits-all philosophy of some processors and leads to animproved prospect of achieving appropriate power consumption levels for a givenhandheld application.

2.4.3.7 FastMATH™ Processor

The FastMATH™ Adaptive Signal Processor™ from Intrinsity [15] consists of thefollowing three elements:

1. A 2.5-GHz matrix and parallel vector maths unit. This unit provideshigh-speed parallel data computation for matrix and vector mathematicsdata types, which are commonly used in adaptive algorithms for wirelessapplications.

2. A 2.5-GHz MIPS32 processing core. This is a high-performance, industrystandard processor, with widely available design toolsets. It can be used foralgorithm adaptation, control, and general processing.

3. A high-speed I/O, using dual RapidIO ports. This primarily enables thepartitioning of complex designs across multiple processors—a feature moreappropriate for BTS designs than for handheld applications.

Together these elements enable the processor to provide very high-speed recon-figurable processing, which is tailored toward the types of algorithms commonlyfound in SDR and wireless communications applications.


It is clear from the above discussion that there exists a wide range of options tosolve the hardware-processing problem in a software defined radio. This range ofoptions is continually increasing and some of these options will undoubtedly findmainstream acceptance in one form or another.

2.5 Current Technology Limitations

2.5.1 A/D Signal-to-Noise Ratio and Power Consumption

2.5.1.1 Background

An ideal software-defined radio receiver is often considered as an A/D converterconnected directly to an antenna, as is shown in Figure 2.1. This section considersthis ideal approach and analyses it in terms of the power consumption of the A/D

2.5 Current Technology Limitations 41

Finite statemachine Scalar

Arithmetic Bit manipulation

(a)

(b)

Matrix interconectnetwork (MIN)

Matrix interconnect network root

Figure 2.8 Architecture of the Adaptive Computing Machine: (a) 4-node cluster and (b) Adapt2400ACM architecture [14].

converter. The aim of the analysis is to find the minimum possible value for thispower consumption and then to determine from this what levels of performance canrealistically be expected from this component in the short and medium term. Sincethe power consumption of the ADC is an important parameter in determining theoverall power consumption of a handset design, for example, it clearly needs to berelatively small for a generic SDR handset to become a realistic proposition.

This section will also examine how close state-of-the-art (monolithic IC) ADCshave come to the relevant ideal level of power consumption over the last 12 years orso. From this it can be surmised how quickly and easily it will be for technologicaladvancements to progress devices to become close to this ideal value and hencewhen suitably high-performance, low-power converters may become a reality.

2.5.1.2 A/D Performance

The specifications for an A/D converter, which would be appropriate for use in theideal software-defined radio shown in Figure 2.1 and summarised in Table 2.1, aregiven in Table 2.2. Note that these specifications are a compromise relative to thosein Table 2.1, yet are still extremely challenging.

Although the high sample rate specified in Table 2.2 could be used to effectivelyrealise an extra bit of resolution, it is assumed here that oversampling is necessary torelax the analogue anti-alias and/or IF filtering requirements. If this were notallowed for, the requirements on these components would be onerous, particularlywhen taking account of the gain and phase flatness requirements of most digitalschemes (to meet EVM requirements, for example).

The specifications detailed in Table 2.2 are clearly very exacting and are some-what in excess of those achievable with present technology. They do, however, illus-trate the level of ADC performance required for use in a software-defined radioreceiver, of the type shown in Figure 2.1, for an acceptable level of RF performance(i.e., a reasonable resistance to) blocking coupled with an adequate sensitivity.

2.5.1.3 Generic A/D Converter

A generic A/D converter consists of the elements shown in Figure 2.9 [16]. It con-tains four main elements:


Table 2.2 Specifications for an Ideal Software Defined Radio ADC

Parameter Value CommentsResolution 20 bits = 121.76-dB dynamic range, assuming a perfect converter; this

value results from assuming that >100-dB signal range isrequired (e.g., from −20 to −120 dBm) and that a 12-dBsignal-to-noise ratio is required at minimum sensitivity

Sample rate 40 Msps Based on 4× Nyquist sampling of a single UMTS WCDMAcarrier, with alias downconversion

RF Inputbandwidth

DC/100 MHz−2.2 GHz To cover PMR, cellular, PCN/PCS, UMTS, mobile satellite

Spurious-freedynamic range

>121.76 dB Assumed not to be the limiting factor in receiver sensitivity

• An anti-alias filter, to remove input signal frequencies which would otherwisealias into the wanted signal band, upon being digitised;

• A sample-and-hold circuit, to maintain the input signal to the quantiser at aconstant level during quantization;

• A quantiser, to convert the (now constant level) analogue voltage into a digitalword;

• A digital buffer.

The quantisation function may take place in a variety of ways, including flash,successive approximation, sigma-delta, bandpass sigma-delta, and subranging. Theanalysis presented in this section is independent of the implementation technologyand is based upon the power requirements of the sample-and-hold element alone. Itis therefore an extremely optimistic analysis and results in the calculation of apower consumption value well below that which could ever be approached in prac-tice. It is presented as a way of highlighting a fundamental point about the form ofA/D conversion currently used in virtually all converters, irrespective of the type ofquantiser they employ.

Note that although the anti-alias filter of Figure 2.9 is shown as a bandpass ele-ment (consistent with the requirements outlined in Table 2.2), it may be a lowpassdesign in many applications (in particular, if undersampling is not used).

2.5.2 Derivation of Minimum Power Consumption

The analysis presented in this section is based on [17] and assumes that the A/D con-verter itself consumes no power; therefore the only power supplied to it is in theform of its input signal. The resulting power consumption, calculated using thistechnique, is therefore a very optimistic minimum possible value for the power con-sumption of an ADC. In a practical ADC, the conversion circuitry, digital outputcircuitry and supervisory functions will all consume significant power, hence add-ing materially to the values calculated here. The analysis only serves, therefore, toillustrate the theoretical minimum power that a converter could possibly consume,and hence provides a power limit below which is it potentially not possible to go(other than with a radically different architecture—see Section 2.6).

The gap between the ideal power consumption presented here and that achiev-able by current (state-of-the-art) devices is over four orders of magnitude, thus indi-cating that technology is still some way from the ideal in this area. The figurespresented do, however, serve to indicate that the ideal software defined radio


Anti-aliasfilter

Sampleand hold Quantiser

Clock

Buffer

Analogueinput

Digitaloutput

Figure 2.9 Generic form of an A/D converter for wideband digitisation at IF or RF.

architecture, discussed above, may never be a practical reality for a handportable(i.e., battery powered) design.

2.5.2.1 Assumptions

The analysis is fundamentally based upon the use of a sample-and-hold devicewithin the converter and hence may not be valid for all converter types (e.g., flashconverters of the type reported in [18]). Given the complexity of flash converters formulti-bit designs, however, it is unlikely that device with 18-bit or more bits will beavailable in the foreseeable future.

The converter’s power consumption is assumed to come from the input signal,rather than from an external DC power supply, as it is this signal which is being usedto charge the capacitance in the sample-and-hold device. In general, the input signalwill be buffered within the ADC and hence it is this buffer that would, in practice,supply the power (deriving its power, in turn, from the power supply to the con-verter circuit). Note, however, that not all high-speed converters utilise buffers, asthese will often contribute to unwanted offsets; an example of this type of buffer-lessconverter is described in [19].

2.5.2.2 Analysis

The dynamic range of an A/D converter is determined by a combination of the peaksignal voltage which it can convert and the resolution (and hence quantisation noise)of the conversion process. The quantisation noise power must be equal to, or below,the thermal noise power present within the converter bandwidth, at the input to theconverter. If this is not the case, some of the available resolution will be wasted.Once the noise floor is determined, the minimum possible peak input signal level(i.e., the minimum possible full-scale voltage) for the converter then follows (see Fig-ure 2.10). From these two levels, it is possible to calculate the power consumption ofthe converter based on the minimum charging current of the converter input capaci-tance; the capacitance value itself is, in turn, based upon the thermal noise floor(kT/Ci, where k is Boltzmann’s constant = 1.38 × 10−23 J/K, T is the device tempera-ture in Kelvin, and Ci is the input capacitance of the converter in farads).

The signal to quantisation noise ratio (dynamic range) of an A/D converter isgiven by:

D nC = +6 176. dB (2.1)

where n is the resolution (number of bits) of the converter.The converter noise floor must appear at level of at least DC decibels below the

full-scale input voltage level, Vfs, in order for the converter resolution to be fullyrealised (see Figure 2.10). Hence:

DV

eCfs

nq

=

20 10log (2.2)

where enq is the noise voltage level of the quantisation noise floor.


Combining (2.1) and (2.2) gives:

eV

nq n

fs=+

2

6 1 76 2010( . )/(2.3)

The mean-square quantisation noise voltage is therefore:

eV

nqfs

n

2

6 1 76 1010=

+( . )/(2.4)

For the converter to be able to fully utilise this dynamic range, the quantisationnoise level must be greater than or equal to the thermal noise floor of the converter.This thermal noise floor is given by [20]:

ekTCnt

i

2 = (2.5)

Equating the two noise floors yields [from (2.4) and (2.5)]:

e eV kT

Cnq ntfs

ni

2 22

6 1 76 1010= = =

+( . )/(2.6)

Hence:

C kTVi

n

fs

=+10 6 1 76 10

2

( . )/

(2.7)

For the converter to accurately convert the input voltage it is presented with,this input capacitance must be capable of being charged to the full-scale voltage ofthe converter, within the converter sampling interval (and preferably well withinthis interval). A charge of Qi coulombs must therefore be transferred to the inputcapacitance within the sampling interval, ts, giving:


Thermal noisefloor (kT C/ i)

Signallevel

Peak signalvoltage, Vfs

Converterdynamicrange,DC

Figure 2.10 Dynamic range of an A/D converter.

Q I ti i s= (2.8)

where Ii is the converter input current and

Q C Vi i fs= (2.9)

Hence:

CI t

Vii s

fs

= (2.10)

Combining (2.7) and (2.10) gives:

IkTt Vi

s

n

fs

=+10 6 1 76 10( . )/

(2.11)

Finally, the power consumed in this process may be ascertained from:

P I Vi i fs= (2.12)

Giving:

PkTti

s

n= +10 6 1 76 10( . )/ Watts (2.13)

from (2.11). It is important to note that this power consumption is independent ofVfs, the full-scale voltage for the converter.

In many systems, the quantisation noise may be reduced, artificially, to a levelbelow that of the thermal noise floor (e.g., by decimation). As a result, it is the ther-mal noise floor, which is the ultimate limit on system performance. It is also possi-ble, however, to assess systems which employ a sampling rate too low to allowdecimation, using this analysis. Results for both are included in the following.

2.5.2.3 Factor of Merit for Converter Efficiency

The current generation of A/D converters are very far from meeting the theoreticallimit discussed above (by over four orders of magnitude, as has already been noted),thereby indicating that technology has a long way to go before the power consump-tion values derived above can be approached. Such values do, however, serve toindicate that the ideal software defined radio architecture, shown in Figure 2.1, maynever become a practical reality for a handportable (i.e., battery powered) device,without a revolution in A/D converter technology. Such a revolution may come fromthe use of Josephson junctions and superconducting technology (see Section 2.6),although this technology itself has many unresolved issues, even for base-stationdesigns, and hence also may never allow the ADC performance values outlinedabove to be realised in a handset design.


The power consumption performance of an ADC can be quantified by theenergy per conversion and per unit of resolution, calculated as follows. Combining(2.5) and (2.10) gives:

( )S NV

e

V I t

KT

P

KTffs

nt

fs i s i

s

22

2= = = (2.14)

Hence, for a non-ideal converter in which the conversion energy, ECR, exceedsthe ideal value of kT:

( )E

P

f S NCR

i

s

=2

Joules (2.15)

where fs is the sampling frequency and (S/N) is the signal to noise ratio of theconverter.

The ratio ECR/kT represents an excess power consumption factor for an ADC. Itcan therefore be used to define a power consumptionfactor of merit for an A/Dconverter:

ME

kTCR= (2.16)

An ideal converter would have a factor of merit of unity.

2.5.3 Power Consumption Examples

Taking the sample-rate shown in Table 2.2, the corresponding power consumptionfigures, for a range of values of ADC resolution, are shown in Figure 2.11. In gener-ating this figure, it was assumed that a 3-dB margin would be necessary between thequantisation noise floor and the thermal noise floor for the converter to operateover its full, usable, dynamic range (as defined by its resolution). This is an optimis-tic assumption, with a more realistic value being discussed later. An alternative wayof viewing this is to think of it as a 3-dB noise figure for the converter, assuming thatdecimation is employed to reduce the quantisation noise floor. The results shown inFigure 2.11 were derived from (2.13) with the sampling frequency set to 40 MSPS.

This graph shows that for the 20-bit resolution converter chosen in Table 2.2,the theoretical minimum power consumption would be around 500 mW whenoperating at 40 MSPS. This is a high value for potential application in a handsetdesign, particularly when considering the many other items which must also con-sume significant power in such an application (e.g., the fast DSP processor(s), mem-ory, linear transmitter, and so forth); it would probably be considered excessive inmost designs. Selecting a resolution above this value would obviously increase thepower consumption still further and this would certainly be unacceptable for hand-set applications. It may also be considered excessive for base-station use (particu-larly the consumption of a 24-bit device) due to the package cooling problems thatwould result and the consequent reliability issues.


In Figure 2.12 the impact of sample rate upon converter power consumption ishighlighted, for a range of values of converter resolution. This clarifies what couldbe expected to happen if direct sampling of the RF waveform (as opposed to aliasdownconversion) was employed. Direct sampling of the RF waveform has theadvantage of making the anti-alias filter design more realistic; this would result in asystem that is significantly closer to the ideal scenario.

Examining the 20-bit resolution discussed in Table 2.2, although now assuminga sample rate of around 5 GSPS to accommodate direct Nyquist sampling of thewhole of the frequency range discussed in that table (DC to 2.2 GHz), will result in apower consumption of around 50W. This is clearly excessive for a handset applica-tion and would also prove problematic from a packaging perspective if aimed atbase-station applications. Even by reducing the sample rate by a factor of 10, theresulting power consumption is too high for any modern handset application, whileproviding direct RF sampling of only HF and VHF waveforms.

This discussion has been based around the theoretical minimum power con-sumption values derived from this analysis and, as has already been noted, these arehopelessly optimistic figures when compared to current converter designs. As anexample, consider the ADS5500 from Texas Instruments. It is a 125-Msps, 14-bitdesign and consumes 750 mW, which is relatively good for such (at present) highperformance. Comparing this with the theoretical minimum power consumption forthis specification yields a figure of 3.77 × 10−4 W, which is around three orders ofmagnitude smaller. This device is close to the current state of the art in terms ofpower consumption versus speed and resolution, it therefore gives a good indicationof how far above the ideal power consumption level current devices are operating.

The earlier figures and discussion were deliberately optimistic in two areas:

1. The margin required between the thermal and quantisation noise floors wasset at 3 dB—a more realistic value would be 10 dB (giving the converter a


6 8 10 12 14 16 18 20 22 2410

10−8

10−7

10−6

10−5

10−4

10−3

10−2

10−1

100

10 1

102

103

Number of bits

Pow

erco

nsum

ptio

n(W

)

−9

Figure 2.11 Minimum theoretical power consumption for an A/D converter, operating at 40 MSPS,for various values of resolution.

theoretical noise figure of 10 log (1.1) = 0.4 dB compared to a noise figure of1.8 dB for the assumption used in deriving Figure 2.12) and this is assumedin Figure 2.13. This will allow a greater margin for added noise from, forexample, practical input buffer stages.

2. The whole of the sample time was allowed for input (sample and hold)capacitance charging—this is again optimistic, as the whole point of asample and hold is to provide a steady voltage to allow an accurateconversion process to take place. A more realistic assumption might be toallow 10% of the sample time for the input capacitance to charge—the effectof this is shown in Figure 2.14.

Comparing Figure 2.13 with Figure 2.12, again using the example of the 20-bitconverter highlighted in Table 2.2, it can be seen that the power consumptionincreases from 500 mW to almost 2.5W, at a sample rate of 40 MSPS. This repre-sents a 7-dB increase in power consumption, which is directly equivalent to the 7-dBchange in the noise floor differential. The relaxation in noise performance for theconverter therefore results in a substantial increase in its power consumption, lead-ing to the conclusion that it is well worthwhile attempting to minimise the differen-tial between the two noise floors whenever possible.

Figure 2.14 shows the impact of reducing the time allowed for capacitor charg-ing to one tenth of the sample time (with the remainder then being available for theconversion operation itself). Comparing this with Figure 2.12 shows that again, theincrease in power consumed is in direct proportion to the change (in this case, thechange in time), as the power required for the 20-bit, 40 MSPS converter hasincreased from around 500 mW to around 5W. This represent a substantial increase


Sample rate (Msps)

Pow

erco

nsum

ptio

n(W

)

1010

10

10

1010

10

10

10

10

10

10

10

10

10

10

10

10

10

1010 10 100 1 2 3 4

−11

−10

−9

−8

−7

−6

−5

−4

−3

−2

−1

0

1

2

3

4

5

24-bit22-bit20-bit18-bit16-bit14-bit12-bit10-bit8-bit6-bit

Figure 2.12 Minimum theoretical power consumption for an A/D converter over a range ofsampling rates.

in power consumed and indicates that the other aspects of conversion (i.e., allaspects excluding the sample and hold operation) should occupy the minimumamount of time possible, in a good design.

These discussions have assumed Nyquist sampling, with no account taken of theability to trade sampling rate for resolution. It is, of course, possible to achieve ahigher effective resolution using oversampling techniques and thereby gain an effec-tive increase in the number of bits of available A/D resolution. The additional num-ber of (effective) bits realised by this approach, Neb, is given by:

( )N

Feb

OS=10 2

6

log(2.17)

where FOS is the over-sampling factor, given by:

Ff

BOSs= (2.18)

and B is the RF channel bandwidth.It would therefore be possible, for example, to utilise a 200-MSPS, 16-bit con-

verter (not yet available, but potentially available in the near future) to sample aGSM-EDGE waveform (200-kHz bandwidth) and achieve an equivalent perfor-mance to a 20.5 bit converter operating at its Nyquist rate.

The increase in sampling rate does, however, lead to a proportionate increase inpower consumption [from (2.13)] and this negates the power consumption benefitsof the extra resolution. However, this method may well enable high-resolution


Sample rate (Msps)

Pow

erco

nsum

ptio

n(W

)

1010

10

10

1010

10

10

10

10

10

10

10

10

10

10

10

10

10

1010 10 100 1 2 3 4

−10

−9

−8

−7

−6

−5

−4

−3

−2

−1

0

1

2

3

4

5

6


Figure 2.13 Minimum theoretical power consumption for an A/D converter over a range ofsampling rates, assuming that a 10-dB margin is required between the thermal and quantisationnoise floors.

converters to be realised, at useable effective sampling rates, in the near term; con-ventional methods of achieving a similar resolution will probably take much longer(see Section 2.5.4.3).

2.5.3.1 Factor of Merit

The concept of a factor of merit was introduced in (2.16) and it is possible to use thisto compare the performance of a range of current and past state-of-the-art ADCdevices (i.e., devices that represented the state-of-the-art at introduction). Table 2.3details this comparison for converters available between approximately 1992 and2004 (many of the earlier converters are now no longer in production). It is evidentfrom this table that state-of-the-art devices, both past and present, are many ordersof magnitude above the theoretical performance level. This further underlines thefact that suitable high-speed, high-resolution converters appropriate for use in theideal software defined radio architecture are somewhat of a challenge, based oncurrent techniques and understanding.

2.5.4 ADC Performance Trends

2.5.4.1 Power Consumption

As has been noted above, all existing converters are many orders of magnitudeabove the theoretical minimum power consumption for their resolution and conver-sion speed. Power consumption does, of course, decrease over time (for a givenperformance level), as process evolution and design optimization help to bring


Sample rate (Msps)

Pow

erco

nsum

ptio

n(W

)

1010

10

10

1010

10

10

10

10

10

10

10

10

10

10

10

10

10

1010 10 100 1 2 3 4

−10

−9

−8

−7

−6

−5

−4

−3

−2

−1

0

1

2

3

4

5

6


Figure 2.14 Minimum theoretical power consumption for an A/D converter over a range ofsampling rates, assuming that only 10% of the sample time is available for charging of the inputcapacitance.

down the excess power consumed. This process will continue until the theoreticalminimum limit is approached, with excess power consumption levels in the order of10 to 100 times perhaps.

Examining the decrease of the energy spent by conversion per unit of resolution(ECR) by commercial high-speed ADCs during the last 12 years, it is evident that thefactor of merit has decreased almost consistently by a factor of 10 every 5 years.

Technologies exist that may overcome the minimum power consumption limita-tion outlined above. It is possible, for example, to make an ADC with a sample andhold circuit which does not need to reset between samples; such a device is describedin [21]. The same article does, however, also indicate that the sample-and-hold cir-cuit consumes a fraction of the power of the complete ADC at around 10–15%. Ittherefore indicates that the other technology areas contained within an ADC mustmake significant progress before the sample-and-hold circuit dominates powerconsumption.

2.5.4.2 Analogue Bandwidth

The analogue bandwidth of a converter is determined by the gate length of the activedevices used in its sample-and-hold circuit. It is given by:


Table 2.3 Factor of Merit for a Selection of High-Speed A/D Converter ICs (from 1992 to 2004)

Company Part Number Sample Rate Resolution Power Cons. ECR M

MSPS bits mW ×10−15 J/unit of SNR

Dimension-less

Maxim MAX1427 80 15 1970 0.62 1.55E+5

TexasInstruments

ADS5500 125 14 750 0.60 1.50E+5

ADI AD6645 105 14 1500 0.90 2.25E+5

ADI AD9245 80 14 410 0.23 0.579E+5

TexasInstruments

ADS5422 65 14 1200 1.16 2.91E+5

TexasInstruments

ADS5421 40 14 900 0.71 1.78E+5

Burr Brown* ADS800 40 12 390 0.58 1.40E+05

ADI AD9042 50 12 600 0.72 1.73E+05

Comlinear** CLC949 20 12 300 0.89 2.16E+05

ADI AD9220 10 12 250 1.49 3.60E+05

Burr Brown ADS802 10 12 250 1.49 3.60E+05

Analogic ADC3120 20 14 5000 0.93 2.25E+05

Harris HI5808 10 12 300 1.79 4.32E+05

Harris HI5810 20 10 150 7.15 1.73E+06

ADI AD9023 20 12 1500 4.47 1.08E+06

Comlinear CLC938 30 12 6570 13.05 3.15E+06

ADI AD9020 60 10 3400 54.04 1.31E+07

ADI AD9014 10 14 12800 4.77 1.15E+06* Now part of Texas Instruments. ** Now part of National Semiconductor.

Bk

La=2

Hz (2.19)

where L is the gate length of the active device and ka is a constant.Over recent years, this gate length has reduced by a factor of 2 every 4 years,

leading to an increase in the analogue bandwidth for an ADC of 4 times over thesame 4-year period. Typical analogue bandwidths for, say, 14-bit converters arecurrently in the low hundreds of megahertz. It is reasonable, therefore, to predictthat they will have reached the 2.2-GHz specification of Table 2.2 before the end ofthe current decade (i.e., before 2010).

2.5.4.3 Sample Rate and Resolution

Considerable research is being directed toward improved converter performanceand the large wireless marketplace for this type of technology will ensure that thisfocus continues. Examination of the state of the art for monolithic converter devicesover the past decade or so, indicates that for a given resolution, the available samplerate increases by roughly a factor of 10 for each decade. This is an indication of aform of Moore’s law [22] for ADCs, although it is not quite as straightforward as isthe case with processors. With processors, computational power (MIPS) is the mainjudgement criterion; in the case of an ADC, both resolution and sample rate are of(arguably equal) importance. Research and development are therefore devoted toboth aspects of performance and the emphasis of this R&D can change with timeand the perceived range of applications. On this basis, it can be predicted that a16-bit, 5GSPS ADC will be available within the next 20 years (i.e., before 2024).Such a part would be capable of sampling all existing PMR, cellular, PCS, andWCDMA RF waveforms directly, with a useful dynamic range.

Alternatively, it could be stated that: for a given sampling rate, ADC resolutionimproves at a rate of roughly 5 bits per decade. This means that the specificationoutlined in Table 2.2 will be met within the next decade (i.e., before 2014).

Combining both of the above, it could be predicted that a 20-bit, 5-GSPS ADCwill be available in around 25 years (i.e., before 2030). Such a converter would becapable of direct RF sampling of all existing PMR, cellular, PCS, and WCDMAstandards, without the need for analogue filtering (other than anti-alias filtering),with sufficient dynamic range for most civil radio applications. Of course, all ofthese existing standards will have been replaced (probably a number of times)within that period; however, the frequency bands may well remain allocated to civilpersonal communications, thereby allowing the new standards to benefit fromdirect RF sampling.

The only major issue is that of power consumption. The reasons behind thisissue have already been covered above and it may well prove to be the major prob-lem in realising the above goals, particularly for portable devices.


2.6 Impact of Superconducting Technologies on Future SDR Systems

The adoption of a superconducting technology brings the potential for a major shiftin the architecture and capability of a software-defined radio. This type of technol-ogy will only be credible for base-station applications for the foreseeable future,however it has some quite remarkable potential benefits in this application area. Theearlier discussions on technology development in silicon ADCs and the predictionsmade about when particular levels of performance will be reached did not takeaccount of the application of Josephson junctions and superconducting quantuminterference device (SQUID) architectures to the field of ADC design [23]. If suchtechniques are taken into account, the predictions made above may well be wildlypessimistic (in terms of pure technological ability, taking no account of cost).

For example, a sample rate of 20 GSPS was reported in 2001 [24] for adelta-sigma ADC, with rates currently in the range of 40GSPS being claimed [25].This latter part has a claimed specification which includes an SNR of >57 dB over a20-MHz bandwidth at 2.23 GHz (based around a bandpass sigma-delta architec-ture). These figures are not yet adequate for the levels of SDR performance outlinedin this chapter; however, the potential is there for this technology to meet therequirements outlined here, somewhat ahead of any silicon solution (if indeed sili-con products ever manage to meet such exacting requirements).

The main advantages claimed for a superconducting SDR solution include:

• Very high-speed digital logic (~50 times faster than silicon LSI);• Very low power dissipation (10,000 times lower than for conventional semi-

conductor technologies). This figure does not take account of the power con-sumption of the cryocooler and vacuum pump (if required).

• Very high accuracy (5 parts per billion accuracy at 10V);• Very high SFDR for both ADCs and DACs (due to the fundamentally different

way that quantisation takes place in a superconducting converter);• Very high sensitivity (claimed to be 60 dB better than a conventional semicon-

ductor front end);• Very low noise (system is essentially thermal noise-free);• Ideal digital interconnects within an LSI chip (no R-C delay, hence, speed of

light transmission);• Large feature size and hence low mask costs, simple fabrication, and so forth.

As an example, the 40-GSPS ADC discussed above was fabricated using 3-µmlithography (current silicon ADCs are fabricated using, typically, 0.25-µmlithography or less).

There are, however a number of obvious disadvantages (at least at present):

• Requirement for cryocoolers and (often) vacuum pumps. These are expensiveitems (particularly the cryocooler) and are also mechanical devices, leading toa reliability-cost compromise. Many studies, including some in which theauthor has had a peripheral involvement, have shown that cryocoolers can bemade to be extremely reliable (MTBFs of many tens of years), however these


have all tended to be expensive (often military) devices and certainly highercost than the wireless marketplace has traditionally accepted.

• Packaging costs. The requirement to maintain a temperature close to absolutezero (4.2–5k, in some cases [26]) or around 70 or 80k (for high-temperaturesuperconductors [27]) leads to a requirement for both airtight seals and goodthermal insulation. Both of these are expensive to achieve.

• Size. This has also, traditionally, been an issue, however the size of themechanical components involved has come down significantly in recent years,to the point where it is now close to being comparable with some largerbase-station installations. Size may therefore become less of an issue for super-conducting wireless solutions.

Essentially, the above disadvantages can be summarized as a major cost issue.At present, superconducting solutions are a very long way from the cost of equiva-lent (at least in terms of functionality) conventional solutions. If this issue can beovercome, however, they have the potential to be an excellent fit with the require-ments of all parts of an SDR base station (with the exception of the RF power ampli-fier): DSP, digital upconversion and downconversion, ADC and DAC, and LNA.

References

[1] Kenington, P. B., “Emerging Technologies for Software Radios”, IEE Electronics andCommunications Engineering Journal, Vol. 11, No. 2, April 1999, pp. 69–83.

[2] Trans-European Trunked Radio (TETRA): Conformance Testing Specification, Part 1:Radio, ETS 300 394-1, March 1996.

[3] Digital European Cordless Telecommunications (DECT) Common Interface, Part 2: Physi-cal Layer, ETS 300 175-2, October 1992.

[4] “Submission of Proposed Radio Technologies: The ETSI UMTS Terrestrial Radio Access(UTRA) ITU-R RTT Candidate Submission”, ETSI SMG2. Submitted on January 29, 1998;at http://www.itu.ch/imt/.

[5] Kenington, P. B., “Linearised Transmitters—An Enabling Technology for Software-Defined Radio”, IEEE Communications Magazine, Vol. 40, No. 2, February 2002,pp. 156–162.

[6] Srikanteswara, S., et al., “An Overview of Configurable Computing Machines for SoftwareRadio Handsets”, IEEE Communications Magazine, Vol. 41, No. 7, July 2003,pp. 134–141.

[7] Zhang, N., and R. W. Brodersen, “Architectural Evaluation of Flexible Digital Signal Pro-cessing for Wireless Receivers”, Proc. of 34th Asilomar Conference on Signals, Systems andComputers, Vol. 1, October 29–November 1, 2000, pp. 78–83.

[8] Baines, R., and D. Pulley, “A Total Cost Approach to Evaluating Different ReconfigurableArchitectures for Baseband Processing in Wireless Receivers”, IEEE CommunicationsMagazine, January 2003, pp. 105–113.

[9] Freescale Semiconductor: “MRC6011 Reconfigurable Compute Fabric”, Product Brief:MRC6011PB, Rev. 1, October 2004; http://www.freescale.com.

[10] Hauser, J. R., and J. Wawrzynek, “Garp: A MIPS Processor with a ReconfigurableCoprocessor”, Proc. of 5th Annual IEEE Symposium on FPGAs for Custom ComputingMachines, April 16–18, 1997, pp. 12–21.

2.6 Impact of Superconducting Technologies on Future SDR Systems 55

[11] Brakensiek, J., et al., “Software Radio Approach for Re-Configurable Multi-StandardRadios”, 13th IEEE International Symposium on Personal, Indoor and Mobile Radio Com-munications, Vol. 1, September 15–18, 2002, pp. 110–114.

[12] Heysters, P.M. et al, “A Reconfigurable Function Array Architecture for 3G and 4G Wire-less Terminals”, Proc. of 2002 World Wireless Congress, San Francisco, CA, May 2002,pp. 399–404.

[13] Srikanteswara, S., et al., “Soft Radio Implementations for 3G and Future High Data RateSystems”, IEEE Global Telecommunications Conference 2001, GLOBECOM 01, Vol. 6,November 25–29, 2001, pp. 3,370–3,374.

[14] Plunkett, B., and J. Watson, “Adapt2400 ACM: Architecture Overview”, Quicksilver Tech-nology; http://www.quicksilvertech.com.

[15] http://www.intrinsity.com.[16] Wepman, J. A., “Analog-to-Digital Converters and Their Applications in Radio Receivers”,

IEEE Communications Magazine, Vol. 33, No. 5, May 1995, pp. 39–45.[17] Kenington, P. B., and L. Astier, “Power Consumption of A/D Converters for Software

Radio Applications”, IEEE Trans. on Vehicular Technology, Vol. 49, No. 2, March 2000,pp. 643–650.

[18] Reyhani, H., and P. Quinlan, “A 5V 6-b 80 Ms/s BiCMOS Flash ADC”, IEEE Journal ofSolid-State Circuits, Vol. 29, No. 8, August 1994, pp. 873–878.

[19] Yuan, J., and C. Svensson, “A 10-bit 5-MS/s Successive Approximation ADC Cell Used in a70-MS/s ADC Array in 1.2-µm CMOS”, IEEE Journal of Solid-State Circuits, Vol. 29,No. 8, August 1994, pp. 866–872.

[20] Smith, J., Modern Communication Circuits, New York: McGraw-Hill, 1986, Chapter 3.[21] Kim, K. Y., N. Kusayanagi, and A. A. Abidi, “A 10-b, 100-MS/s CMOS A/D Converter”,

IEEE Journal of Solid-State Circuits, Vol. 32, No. 3, August 1997, pp. 320–311.[22] Moore, G. E., “Cramming More Components onto Integrated Circuits”, Electronics,

Vol. 38, No. 8, April 19, 1965.[23] Lee, G. S., and D. A. Petersen, “Superconductive A/D converters”, Proceedings of the IEEE,

Vol. 77, Iss. 8, pp. 1,264–1,273, August 1989.[24] Mukhanov, O. A., et al., “High-Resolution ADC Operation Up to 19.6 GHz Clock Fre-

quency”, Supercond. Sci. Technol., Vol. 14, 2001, pp. 1,066–1,070.[25] HYPRES Inc., “Benefits of Superconducting Microelectronics—Quantum Leap Increase in

Performance and Decrease in Cost: Commercial Wireless Base Stations”, February 2004;http://www.hypres.com.

[26] ter Brake, H. J. M., “Cryogenic Systems for Superconducting Devices”, in H. Weinstock,(ed.), Applications of Superconductivity, Boston, MA: Kluwer, 2000.

[27] Kenington, P. B., et al., “Transposer Systems for Digital Terrestrial Television”, IEE Elec-tronics and Communications Engineering Journal, February 2001, pp. 17–32.


C H A P T E R 3

Flexible RF Receiver Architectures

3.1 Introduction

The concept of flexibility in a receiver breaks down into two main areas: that offlexibility in the modulation format, coding, and framing and that of flexibility interms of RF frequency (i.e., the ability to cover multiple bands, or provide generalcoverage, which is defined as covering all bands between a declared minimum andmaximum frequency). This latter area, frequency flexibility, is certainly the morechallenging of the two and is a concept which is the subject of much research. Theformer area has been much more widely addressed and most commercial communi-cations receiver designs employ many of its basic principles, even if they do not aimto provide a wide choice of modulation formats.

Both concepts are covered in this chapter and Chapter 4, with a range of ideasbeing presented to enable the provision of frequency flexibility. Many of these havenot yet been implemented in commercial designs and are still the subject of ongoingresearch; however, they are presented here as a set of basic concepts for furtherdevelopment.

3.2 Receiver Architecture Options

3.2.1 Single-Carrier Designs

3.2.1.1 Analogue Quadrature Receiver Design

In contrast with the area of transmitter design, where the requirement for linearity isa relatively recent phenomenon, receivers have needed to preserve signal amplitudeinformation and, in particular, dynamic range in almost all designs over the years.Thus, most receivers, even those for FM and other constant-envelope systems, areinherently linear for the majority of their RF and IF paths. The translation from aconventional receiver design to a linear receiver design is therefore more straightfor-ward than for an equivalent transmitter and may only involve alterations to thedetection and (possibly) AGC stages.

A simplified, single-band flexible receiver architecture is shown in Figure 3.1.Its flexibility stems from the use of a DSP as the baseband demodulation function; itcan thereby demodulate any modulation format within its processing and data con-version bandwidth. Note that if a variety of different modulation formats are to bereceived by the same radio architecture, then the desired channel bandwidths mustbe carefully considered. For example, if the receiver is to handle both GSM(200-kHz bandwidth) and PDC (30-kHz bandwidth), then the IF filter, anti-alias

57

filters, and A/D input bandwidth (and hence sampling rate) must be chosen based onthe wider of the two bandwidths (more than 200 kHz for the IF filter and more than100 kHz each for the anti-alias filters and A/D converter input bandwidths).

If this is done, then it is possible for the IF chain and A/D converters to experi-ence a wide dynamic range of signals when in PDC mode, since at least six PDCchannels could appear in the IF bandwidth. This leads to a requirement for a greaterinstantaneous dynamic range in the IF and A/D converters than might otherwise benecessary. This problem may be overcome by the use of flexible baseband filteringemploying, for example, switched-capacitor techniques, although such techniquesbring their own problems (e.g., noise).

Note that the flexibility of the processing in the DSP allows many of the conven-tional receiver functions to be implemented in that part of the system. Examplesinclude:

• Detection/demodulation of the modulation format;• Fast AGC (e.g., by feedforward techniques);• AFC, either by the use of internal (to the DSP) oscillators for frequency trans-

lation, or by pulling of the external frequency standard (not shown in Figure3.1);

• Companding for analogue voice;• Deinterleaving and decoding/error correction of data;

3.2.1.2 Digital IF Receiver Architecture

An alternative, single-band flexible receiver architecture, is shown in Figure 3.2.Here the quadrature downconversion function is contained within the DSP, and thishas the advantage that perfect quadrature accuracy can be obtained, without thepresence of DC offsets. This is usually performed by ensuring that the final IF(labelled baseband IF in Figure 3.2) is at a frequency sufficiently high that somechannel selection can be performed, but sufficiently low that a sensible A/D and DSPprocessing bandwidth results. This compromise is currently around the 10−50-MHzregion, but continues to increase as A/D converter technology advances. The mini-mum frequency is determined by the requirement that at least a single channel must

58 Flexible RF Receiver Architectures

Low-noiseamplifier

Channel synth.(variable)

IF filter

LinearIF amp

I/Qdemodulator

Iout

Q

LO InIF In Anti-aliasfilter

Anti-aliasfilter

Fixedsynth.

A/Dconvertersand DSP

Iin

QinBand-selectfilter

AGC Basebandvoice/dataoutput

Mixer

out

90°

Figure 3.1 Simplified linear receiver architecture.

be capable of being Nyquist sampled at the A/D converter (10 MHz being the mini-mum requirement, approximately, for 3GPP WCDMA). Some allowance should, ofcourse, be made for frequency drift of the receiver local oscillator in selecting thisfrequency, if frequency correction is to be performed within the DSP. For widebandsystems (e.g., CDMA), this is generally negligible. Allowance must also be made forthe roll-off of the IF filter and hence the potential for adjacent-channel energy toenter the front-end. This will also force the baseband IF higher in frequency.

3.2.1.3 Digital Processing for Digital IF Reception

Having sampled the baseband IF in the above architecture, a digital IF is created.This must typically be mixed down to form a complex baseband signal (i.e., to formbaseband I and Q components). This can be performed as shown (conceptually) inFigure 3.3.

The digital IF signal, created by sampling the analogue baseband IF signal at arate fs, is mixed with a quadrature (numerical) oscillator running at exactly fs/4. Thiscan be achieved by multiplying the digital IF samples by the periodic sequences: [1,0, −1, 0] for the real channel and [0, −1, 0, −1] for the imaginary channel.

The resulting baseband I and Q streams are then filtered by separate finiteimpulse response (FIR) low-pass filters, to form the required baseband digital sig-nals. These can then be passed for subsequent processing (e.g., demodulation), asrequired.

In practice, it is more computationally efficient to remove the samples multi-plied by zero from the subsequent FIR filtering process. It is therefore possible to

3.2 Receiver Architecture Options 59

Low-noiseamplifier

Channel synth.(variable)

IF filter

LinearIF amp

Anti-aliasfilter


Band-selectfilter

AGCBasebandIF amplifier

Basebandvoice/dataoutput

Figure 3.2 Digital IF-based linear receiver architecture.

I/Qdemodulator

Iout

Qout

NCO In90º

FIRfilter

f /4s

IDBB

QDBB

FromADC

FIRfilter

Figure 3.3 Conceptual process of digital quadrature demodulation.

devise an architecture in which the complex mixing and FIR filtering processes aremerged [1]. This is shown in Figure 3.4.

In this architecture, two identical filters are shown in which the mixer is realisedin a manner such that for the real part, only even-order filter coefficients are used,and for the imaginary part, only odd-order coefficients are necessary. The requiredsigns for the coefficients, together with the use of double clock delays, are both alsoshown in Figure 3.4. Note that this structure dictates that the number of FIR filtercoefficients must be a multiple of 4.

3.2.2 Multi-Carrier Receiver Designs

The multicarrier receiver concept is an extension of the digital IF receiver shown inFigure 3.5. In this case, multiple quadrature downconversions are performed in thedigital domain using separate numerically controlled oscillators (NCOs). Channelselectivity is provided using digital lowpass filtering on the resulting I and Q base-band signals; as a consequence, the selectivity achieved can be very good. Thisapproach to a multi-carrier receiver problem, such as a cellular BTS, has the signifi-cant advantage of a considerable saving in RF hardware over an approach involvinga number of separate receivers. In the case of a military application, such as a sur-veillance receiver, it allows a large number of channels to be monitored simulta-neously at a relatively modest cost and with a small device. A multiple-receiverdesign would quickly become unwieldy in this case.

3.2.3 Zero IF Receiver Architectures

A single downconversion receiver was first proposed by Colebrook in 1924 [2], only6 years after Armstrong introduced the superheterodyne concept [3]. Colebrookalso coined the term homodyne to describe his single-downconversion concept,


IDBB

QDBB

FromADC

−a20 4 −a6 −a4 2N−+a +a

Z−2

+a3 −a5 +a7

Z-2

+a4 1N−−a1

Z−2

Z−2

Z−2

Z−2

Z−2

Z−2

Figure 3.4 Combined mixing and FIR filtering process for conversion from a digital IF to complex baseband.(From: [1]. © 2005 IEEE. Reprinted with permission.)

3.2Receiver A

rchitecture Op

tions61

Low-noiseamplifier

Band orchannelgroup synth.

Multi-channelIF filter

LinearIF amp

Anti-aliasfilter

Band-selectfilter

Fixedsynth.

BasebandIF amplifier

A/D

90°

0°In

In

In

NCO 1

NCO 2

NCON

Lowpass(channel-select)filters

Channel 1voice/dataoutput

Channel 2voice/dataoutput

Channel Nvoice/dataoutput

DSP

Base

band

pro

cess

ing

Base

band

pro

cess

ing

Base

band

pro

cess

ing

90°

0°

90°

0°

Figure 3.5 Multi-carrier receiver architecture, based on a digital IF.

although this differs from modern direct conversion receivers, in that a true homo-dyne receiver derives its LO (local oscillator) directly from, for example, the trans-mitter, or from self-oscillation of the active device, and does not use a separateoscillator. Most recent single conversion receivers, for SDR or other demandingcommunications applications, utilise a separate LO synthesiser and tune this inorder to receive the desired channel(s).

A single downconversion receiver, which is amenable to both single andmulti-carrier operation, is shown in Figure 3.6. Here a direct-conversion or zero-IFsolution is employed, with quadrature downconversion taking the RF signal directlyto baseband. This is potentially a very attractive option for the following reasons:

• Channel selection. The use of digital filters allows for the implementation offar better channel selection filters than could be implemented in hardware atIF. In particular, tight specification linear-phase filtering is possible, whichcauses minimal disturbance to digital modulation schemes.

• It is a simple architecture and hence potentially very low cost.• The image frequency is in-band and hence the required image-rejection, based

on the gain and phase balance of the I/Q demodulator, is considerablyreduced. Around 30−35 dB is acceptable for most systems.

• Only a single local oscillator signal is required.

• No IF filter is required, hence saving cost and space and increasing the likeli-hood of achieving a single-chip solution.

It does, however, have a number of fundamental problems, which largelyexplain its restricted use to date:

• A high accuracy quadrature network is required, which must be broadbandand require no tuning or setting-up. This is now possible to a limited degreewith a number of integrated parts.

• A DC offset appears at the centre of the baseband channel in I and Q and isusually quite high in level with respect to the weaker signals which the receivermay be required to demodulate. This is therefore a serious limitation on the


I/Qdemodulator

Iout

Qout

LO InRF In90°

Low-noiseamplifier

Channelsynth

Bandpassfilter


Figure 3.6 Zero-IF receiver architecture.

sensitivity of the receiver and proves very difficult to eliminate with mostmodulation formats, since they generally have a significant level of energy atthis point in their spectra.

• Radiation. As the local oscillator appears on the wanted channel frequencyand there is very little isolation between it and the antenna, significant levelsof the LO signal can be rebroadcast. This is one effect contributing to the DCoffsets mentioned in Section 3.2.3.3.

• Noise. The use of a baseband IF results in problems with low-frequency noiseappearing at the centre of the channel (1/f noise); this must be insignificantwith respect to the signal; otherwise, it will have a detrimental effect on over-all sensitivity.

• Second-order intermodulation. Second-order (or second harmonic) distortionin the LNA or mixers can result in significant levels of second-order distortionappearing at (and around) DC.

These issues have been highlighted and investigated by a number of authors(e.g., [48]), and will be discussed further in the following sections.

3.2.3.1 Quadrature Mismatch

The effect of quadrature mismatch on receiver performance can be described in anumber of ways, depending upon the modulation format (or carrier format in amulti-carrier receiver) in question. In the case of an SSB or AM system, for example,it will impact upon the signal to noise ratio and user acceptance of the demodulatedspeech signal. A large quadrature imbalance will result in a significant in-bandimage and since this falls on top of the wanted signal and has, typically, similar(audio) characteristics, its practical impact can be severe. In general, a poor SNR,where the unwanted component is white noise, is much more acceptable and under-standable than one in which the unwanted component is another speech signal orsimilar interferer.

In the case of a digital modulation format, quadrature mismatch will typicallyimpact upon error vector magnitude (EVM) and thereby the detectability of the sig-nal. Section 3.4.2 details the calculation of the impact of quadrature errors onEVM. In the case of a receiver, the noise already present on the received signal willcause a further EVM degradation and hence quadrature errors can be viewed ashaving an impact (ultimately) upon receiver sensitivity.

3.2.3.2 Quadrature Mismatch Compensation

There exists a range of mechanisms for overcoming quadrature errors and the selec-tion of an appropriate method (or none) is usually a compromise betweenimplementational complexity and cost. These methods have counterparts for trans-mitter (quadrature upconverter) compensation and are dealt with in more detail inChapter 5. A brief introduction only will be provided here.

In an analogue quadrature downconverter with two notionally equal-level out-puts, a small gain and phase error will inevitably exist between them. This error will


have two elements: a static (i.e., frequency invariant) component and a fre-quency-varying (ripple) component. Both will generate (if uncompensated) anunwanted in-band image signal or a signal vector error, depending upon how theproblem is viewed. In the case of the static component, it is possible to compensatefor this error by predistorting the I and Q signals, either internally within the DSP orexternally in analogue hardware. In either case, the form of compensation requiredis shown in Figure 3.7.

The required compensation may be achieved by modifying the I and Q basebandsignals in the DSP following the downconverter, in the manner shown in Figure 3.7.A small fraction of the I channel signal is added to the Q channel output, and byalteration of the variables KI1, KI2, KQ1 and KQ2, any amount of gain and phase mis-match may be accommodated. This process can be a manual calibration, under-taken upon manufacture, for example, or automated using a control scheme. Notethat this latter option is more difficult to realise than its upconverter counterpart,since the system has no knowledge of its input signal. Some form of known soundingsignal is therefore usually necessary and the generation and upconversion of this sig-nal usually negates many of the simplicity and cost benefits of the direct-conversionapproach.

Any frequency varying (ripple) component of the gain and phase imbalance willhave a similar impact to that described earlier (i.e., it will also contribute to theunwanted image or degradation of the signal vector error). In this case, however, theimpact will typically be an order of magnitude or more lower than that of theuncompensated static errors (and often much more for a IC implementation). This isdue to the amount of ripple typically being of a much smaller magnitude than thestatic errors. The other key difference is that it is much more difficult to compensate(either manually or automatically) for the effects of ripple and it is usually notnecessary (or economic) in most systems.


Quadratureinput signals

K Q1

K I2

I

Q

Compensatedquadratureoutput signals

I'

Q'

I

Q

Input signals Output signals

I

QQ'

K I1

K Q2

I'

Figure 3.7 Gain and phase error compensation in a quadrature downconverter.

Where a known digital format (or, potentially, a range of known digital for-mats) is being received, it is possible to utilise a pilot sequence, embedded within themodulation, to provide quadrature error correction. One form of this technique isoutlined in [6], for an OFDM system, in which a suitably chosen pilot sequence isapplied over two OFDM symbols. This provides a very rapid correction of the I andQ error, as complete correction takes place within the two pilot symbols. The use ofonly two pilot symbols is also a small overhead in a multi-carrier OFDM environ-ment. The main disadvantage with this approach is that it relies on the service pro-vider transmitting suitable pilot symbols for the receiver to utilise in itsquadrature-correction algorithm. Such symbols are available in some mobile com-munications standards and hence the use of pilot-symbol insertion techniques ispossible in these cases.

3.2.3.3 DC Offset Issues

The effect of DC offsets on the baseband I and Q signals is to shift the origin of thesignal constellation (see Section 3.2.3.5). This can lead to a degradation in bit errorrate, since the demodulation algorithm in the receiver will effectively be looking forconstellation points in the wrong place. It can also lead to saturation of the base-band A/D converters (or amplifiers) and hence an effective drop in dynamic range ofthe receiver. With most digital signals, it is not possible to filter the DC offsets (e.g.,using a highpass baseband filter in each of the I and Q channels) without alsoremoving some of the wanted signal energy. The DC offset must therefore beremoved by alternative means, or prevented from occurring in the first place. Someoptions for both of these approaches are discussed next.

There exists a range of sources for the DC offsets occurring within a direct-con-version receiver. These may be broken down into sources of static DC error andsources of dynamic DC error. Static DC errors are generally caused by LO leakageand self-mixing occurring within the receiver itself; dynamic DC errors are causedby inadequate compensation of time-varying effects within the receivers environ-ment. Examples of the latter are:

a. Local reflections of the receiver LO, which is reradiated from the receiverantenna (see the following), which are then picked up and downconvertedby the receiver.

b. Rapid increases in signal strength, such as those caused by Rayleigh fading,which are not tracked sufficiently quickly by the receiver AGC. The receiveris therefore effectively overloaded for a short period and the second-ordercomponent (and other even-order components) of the resulting non-linearitywill cause a DC signal to be generated.

Static DC Error

Figure 3.8 shows the main potential leakage paths, and hence, indirectly, sources ofDC offsets in a direct-conversion receiver. These may be summarised as follows:

1. Leakage within or around the downconversion mixers, for example due tothe imperfect LO-RF isolation within the mixer. The level of DC offset


generated by this mechanism is typically fairly constant across the operatingfrequency band, unless this band is very large.

2. Local reflections of the receiver LO (as “a” in Section 3.2.3.3).3. Direct leakage from the LO to the receiver input. This can be caused by either

radiation of the LO from the case of the unit which is then picked up by thereceive antenna, or by radiation across the receiver PCB. The level of DCoffset generated by this mechanism typically varies, sometimes markedly,across the operating frequency band. This is due to the frequency-varyingphase-shift (i.e., delay) through the various components between the filterinput and the mixer RF inputs. At some frequencies, this phase shift will be90º, thereby generating a (theoretically) zero DC voltage at the mixer output(for most mixer types). At other frequencies, the phase shift will be close to0º, thereby generating a maximum in the mixer output DC voltage.

4. Leakage of the LO to the LNA input typically through radiation from/toPCB tracks. Again, the level of DC offset generated by this mechanismtypically varies across the operating frequency band.

5. Leakage of the LO to the LNA output again, typically through radiationfrom/to PCB tracks. Here again, the level of DC offset generated by thismechanism also typically varies across the operating frequency band.

Whilst it is possible to minimise these sources, by careful layout and screening ofthe components, it is not usually possible to eliminate them entirely.

3.2.3.4 DC Offset Compensation

There exists a range of options to help alleviate DC-offset issues in a zero IF receiver,which are principally caused by self-mixing of the LO signal received at variouspoints within the analogue hardware, as outlined earlier.

Frequency Modification

One common method of solving local oscillator leakage problems is to remove thefrequency of the oscillator from the receive frequency range of interest. This is acommon technique in handset designs that do not utilise a direct-conversionapproach and is, arguably, even more beneficial in designs which do utilise this typeof architecture. The idea behind this approach is to ensure that the local oscillator


90°In

Bandpassfilter

LNA

I-channeloutput

Localoscillator

Q-channeloutput

2

13 4 50°

Figure 3.8 LO leakage paths in a direct conversion receiver.

VCO is not operating on (or near to) the desired receive channel (or band). It is, fre-quently, radiation from the VCO itself and its tuned circuits that leads to the largestleakage component. If the VCO is not operating on the receive channel frequency,therefore, this source of leakage, and hence DC offset, is eliminated. There will still,obviously, be the potential for the required LO signal, at the desired receive fre-quency, (which must be created at some point) to leak to an undesired location.However this final frequency generation step can take place physically very close tothe point at which the LO signal is required, thereby minimising leakage effects.

Figure 3.9 shows four options which can achieve the goal outlined above. Fig-ure 3.9(ac) [7, 8] shows various methods of multiplying, dividing, or prescaling thesynthesiser (VCO) frequency, thereby ensuring that it is far removed from thedesired receive frequency. Clearly these processes have the potential to generate asignificant number of spurs, particularly if their output signals are allowed to leakto any part of the original synthesiser, however they are relatively simple andlow-cost methods of generating the desired result.

In the case of Figure 3.9(d), a second (fixed) oscillator is added to offset themain synthesiser from the desired receive frequency. While this clearly appears tobe an additional cost, it can be arranged to be a cost-reduction (or at least cost-neutral) strategy in a transceiver application. In such a configuration, the mainsynthesiser can be designed to cover the transmit frequency range (assuming adirect-conversion or direct-modulation form of transmitter), with the offset oscilla-tor configured to cover the (duplex) split between the transmit and receive bands.Since this split is typically a constant value, irrespective of channel number, this off-set oscillator can be a fixed frequency device. The two oscillators are then mixedtogether and filtered, very close (physically) to the LO input of the quadraturedownconverter. Note that the filter can be a lowpass, highpass, or bandpass device,as appropriate.

Capacitive Coupling

Although capacitive coupling of the baseband signals (Figure 3.10) will removesome of the wanted signal energy in many systems, this may be acceptable in caseswhere significant energy is not present around the centre of the signal. This is true inthe case of CDMA and WCDMA, where capacitive coupling may be employedwithout significant degradation of the signal-to-noise ratio [8].

In the case of signals which, when downconverted, possess significant energy ator close to DC, capacitive coupling is not an option. GSM is an example of such asignal and alternative techniques must be used for its GMSK modulation format.

DC Calibration

In cases where capacitive coupling cannot be used, it is possible to perform a DCcalibration of the system and inject an appropriate DC (or carrier) level into the sys-tem, in order to cancel the DC offset. The measurement process for this system istypically performed in the digital part of the receiver, although analogue sam-ple-and-hold devices could also be used, prior to the analogue to digital converters.The measurements upon which the DC injection level is based can be taken duringan idle slot, or when the receiver is not actively receiving a signal (i.e., when thereceiver is standing by or roaming). Alternatively, a long-term average of the



90°

0°In

Bandpassfilter

LNA

I-channeloutput

Localoscillator

Q-channeloutput

Frequencydivider

xN

F = FVCO Rx/N

90°

0°In

Bandpassfilter

LNA

I-channeloutput

Localoscillator

Q-channeloutput

Frequencydivider

−1/N

F = FVCO Rx*n

(a)

(b)

90°

0°In

Bandpassfilter

LNA

I-channeloutput

Localoscillator

Q-channeloutput

Prescaler

−n/N

F = FVCO Rx*( / )n m

Bandpassfilter

LNA

I-channeloutput

Localoscillator

Q-channeloutput

FOffset

Fixedoscillator

Bandpassfilter

90°

0°In

F = F FVCO Rx Offset±

(c)

(d)

Figure 3.9 LO generation options to reduce leakage of the LO signal at the receiver input frequency. Utilising(a) a divider; (b) a frequency multiplier; (c) a prescaler; and (d) an offset oscillator.

received signal can be taken (e.g., over many seconds or minutes) and the result ofthis used as the DC value to be subtracted.

An architecture that shows the use of DC calibration and removal is illustratedin Figure 3.11. The operation of the calibration scheme is straightforward and isbased upon the digital sample and hold processes following the A/D converters.Both of these operate on either a long-term average of the A/D output or on an aver-age taken over the duration of a vacant slot (or similar idle period). The results ofthe averaging processes are held and fed to the (low-speed) D/A converters. Thesethen subtract the required value of DC from the I and Q channel outputs of themixers.

Clearly the subtraction process could equally well be carried out digitally; how-ever, this will utilise (waste) valuable bits on the A/D converters, since these mustalways convert the unwanted DC component of the baseband signals, prior to sub-traction. It is typically lower cost to utilise low-speed DACs and to convert the exist-ing ADC buffer amplifiers into summing amplifiers than it is to pay for extra bits on ahigh-speed ADC. Frequently these ADCs are already state-of-the-art regarding speedand resolution; hence, adding extra bits may not be an option at any (sensible) price.

The main drawback of a DC-calibration scheme is that it is unable to ade-quately compensate for dynamic DC offsets (unless the dynamic effects are slow andthe calibration update rate is rapid). This type of offset must either be removed bycapacitive coupling (described earlier) or by the use of a continuous-time feedbackcontrol scheme. An example of this type of scheme is the servo control loop and thisis described next.

Servo Control Loops

Figure 3.12 shows how the system of Figure 3.11 can be modified to providereal-time servo control for the DC-offset removal process. The sample-and-holdprocessing of Figure 3.11 has now been replaced by an integrator. The action of thisintegrator will be to ramp in the direction of the DC offset (i.e., increasing positiveoutput number for a positive input number and vice versa) until the DAC output issufficiently large to subtract the channel offset. The two loops, for the I and Q chan-nels, operate independently, since the DC values in each channel will be, to a degreeat least, independent.

Clearly other forms of controller are possible (e.g., integral and proportional),with potential benefits in dynamic operation over the simple integral controllerdescribed here.


90°

0°In

Bandpassfilter

LNA

I-channeloutput

Localoscillator

Q-channeloutput

Fvco =FRx

CC

CC

Figure 3.10 Capacitive coupling applied in the I and Q paths to remove unwanted DC offsets.

The main drawback with this technique is that the finite loop bandwidth of thesystem will inevitably result in some degradation of the receiver signal-to-noiseratio, due to the removal of some signal energy around DC. In this respect, the tech-nique has a similar drawback to that of AC coupling, discussed earlier, although theeffective coupling capacitor value obtained can be far higher than any sensible,physically small capacitor could achieve.

3.2.3.5 Combination of DC Offsets and Gain/Phase Error

Figure 3.13 illustrates the impact of DC-offsets, gain/phase errors, and both effectssimultaneously on a 64-QAM constellation when received by a zero-IF receiver. A


90°

0°In

Bandpassfilter

LNA

Localoscillator

Fvco = F Rx

Digitalreceiverprocessing

A/D

A/D

D/A

D/A

Summing amplifier

Summing amplifier

S/H

S/H

Figure 3.11 DC calibration used to remove offsets in a direct conversion receiver.

90°

0°In

Bandpassfilter

LNA

Localoscillator

Fvco = F Rx

Digitalreceiverprocessing

A/D

A/D

D/A

D/A

Summing amplifier

Summing amplifier

dt

dt

Figure 3.12 Use of a servo-type control loop to remove DC offsets from the I-and-Q basebandoutputs of a direct-conversion receiver.

DC offset alone will shift the constellation from being centred on the origin in theI/Q plane [Figure 3.13(b)], making detection of the individual symbols more diffi-cult. An error in both gain and phase [Figure 3.13(c)] will distort the constellation(making it wider and thinner or taller and narrower) and rotate it about the origin inthe I/Q plane. Again, this can result in a lower signal-to-noise ratio, or in theextreme, errors in the detection process.

Combining both effects [Figure 3.13(d)] further increases the distance of a givenconstellation point from its expected location. Without suitable compensation, it isclearly possible for significant errors to result, hence illustrating the need for tech-niques such as those discussed in this section to be applied to a direct-conversionreceiver.

Note that the DC offsets and gain/phase errors illustrated in Figure 3.13 aredeliberately severe and generally much higher than would be encountered in most


Q

I

(a)

Q

I

(b)

Figure 3.13 Illustration of the effect of DC offsets and I/Q imbalance on a 64-QAM constellation: (a)original constellation; (b) impact of DC offsets (Q-channel only); (c) impact of I/Q imbalance (gainand phase errors); and (d) combined effect of DC (Q-channel only) and I/Q errors.

practical systems (certainly at high signal strengths). This was intentional, sincemore realistic error levels would be much more difficult to detect by eye.

3.2.3.6 Impact of Quadrature Mismatch on an OFDM Signal

In an OFDM system, quadrature mismatch errors cause intercarrier interference(ICI) from the subcarrier located at the mirror-image frequency of the subcarrier inquestion [9]. The conjugate of the data transmitted on the kth subcarrier thereforeinterferes with the data contained on the (Ns − kth) subcarrier (and vice versa),where Ns is the number of subcarriers contained within the OFDM system.

In the case of an OFDM system, quadrature mismatch may be estimated andcorrected within the demodulation processing, as there exists a linear relationshipbetween the data present on a given subcarrier and the interfering frequency-mirrorsubcarrier. An adaptive equaliser, containing two taps, may therefore be used tojointly cancel both the effects of the channel and of the I/Q mismatch.


Q

Q

I

I

(c)

(d)

Figure 3.13 Continued.

3.2.3.7 1/f Noise

1/f, or flicker, noise is inherent in most semiconductor devices and its origins are notwell understood. Indeed, it was sometimes referred to as semiconductor noise in theearly years of semiconductor production because of its dominant effect in theseearly devices. The term 1/f noise comes from its power spectral density, which isgiven by:

S fk

fVn

n( ) =β

2 Hz (3.1)

where kn is a constant (equal to the power spectral density at 1 Hz), f is frequency,and is in the range 0.8 to 1.4 [10]. Typically, is approximated as unity, giving:

S fk

fVn

n( ) = 2 Hz (3.2)

The mean square noise voltage in the frequency range f1 to f2 is therefore:

ek

ff

k f f V

fn

f

f

n

2

2 12

1

2=

=

∫ d

ln( )

(3.3)

In a receiver, it is possible to define a point, fα at which the flicker noise equalsthe cascaded receiver thermal noise floor. This is illustrated in Figure 3.14 and var-ies depending upon the semiconductor process and device technology used. Forexample, in a BiCMOS process it is in the range ~48 kHz, whereas for a MOSFETdevice, it may be around 1 MHz [11].

In a direct conversion receiver, the IF is at baseband and stretches down to DC;1/f noise is therefore clearly a potential problem in the downconversion mixers andalso in any baseband amplification. The noise floor at the mixer output, includingthe effects of 1/f noise, may be calculated [based on (3.3)] as:

( ) ( )[ ]n t n f f f f f Va( ) ln= − +0 2 1 2 12 (3.4)

where n0 is the input-referred noise floor at the downconverter, the signal passbandof the baseband spectrum is defined by f1 and f2, and fα is as defined previously.

It is obvious from the above that narrowband signals, with significant energyaround DC (when downconverted), are most susceptible to this type of noise. SSBsignals in military systems, for example, along with GSM and GSM-EDGE aretherefore potentially susceptible. 1/f noise is much less of an issue for CDMA andWCDMA signals, due to their having relatively little signal energy close to DC.

3.2.3.8 Second-Order Distortion Requirements

Second-order distortion in a direct-conversion receiver can cause blocking or jam-ming signals (whether intentional or not) to degrade the receiver signal-to-noise


ratio. The mechanism by which this occurs, will be outlined in the followingparagraphs.

A transfer characteristic containing a second-order non-linearity may beexpressed as:

V t K V t K V tout in in( ) ( ) ( )= +1 22 (3.5)

Figure 3.15 illustrates an example characteristic for the case where K1 = 10 andK2 = 2 and demonstrates the effect of such a characteristic on a pure sinusoid in boththe time and frequency domains.

The larger the coefficient of the second-order term (K2), the more curved thetransfer characteristic will appear and hence the greater the distortion of the inputwaveshape. Note that in the frequency domain a second signal component has nowappeared at twice the original frequency (2f1) and this gives rise to the term secondharmonic distortion, used to describe the form of non-linear distortion introducedby the second-order term. Note further that a DC term also results from the sec-ond-order term in the transfer characteristic.

Examination of the amplitude of the second harmonic component indicates thatit will increase in proportion to the square of the input signal (and also in proportionto the constant, K2). The amplitude of the fundamental frequency component, how-ever, will only increase in proportion to the fundamental gain, K1. As a result, it isevident that the amplitude of the second harmonic will increase at a greater rate thanthat of the fundamental component. A point can thus be envisaged where the funda-mental and second harmonic components are of equal level; the signal level at whichthis would occur is termed the second-order intercept point, usually expressed as apower in dBm. This may be quoted as either an input or an output intercept point;with the former being most commonly found in receiver front-end specifications. Itis often designated as IP2 or IP2.

The characteristics of the fundamental and second harmonic amplitude levels,with varying input level, are shown in Figure 3.16 for the transfer characteristicillustrated previously (K1 = 10 and K2 = 2). The latter parts of the two characteristicsare shown dotted since the input and output levels required to obtain these parts of


Frequency

n t( )

GSM signal(100 kHz wideat baseband)

Flicker noise

f

Cascadednoise floor

CDMA signal(615 kHz wideat baseband)

f1 f2

a

Figure 3.14 Impact of 1/f noise emanating from a frequency mixer in a zero IF receiver. (From: [8].© 2005 IEEE. Reprinted with permission.)

the characteristics in practice would be impossible, without destroying the device.In this example, the second-order (input) intercept point may be quoted as approxi-mately 5V, corresponding to the output signal level where the two characteristicscross, divided by the linear gain (K1=10).


−2 −1 1 2

−15

−10

−5

5

10

15

20

25

30

Input voltage (V)

Output Voltage (V)

(a)

(b)

(c)

−5

5

10

15

Input Output

+1V

−1V

Time Time

Output voltage (V)

Input voltage (V)

f

Amplitude

Frequency f

Amplitude

Frequency2f

Input Output

Figure 3.15 Transfer characteristic (a) and effect on a sinusoid in the time domain (b) andfrequency domain (c) of an amplifier with transfer characteristic V t V t V tinout in( ) ( ) ( ).= +10 2 2

Note that intercept point values are more commonly quoted in dBm. For theabove example, assuming a 50-Ω system, the second order input intercept point istherefore +27 dBm.

If a sinusoidal input signal, Vin(t) = Acos(ωt), is fed into a receiver with a sec-ond-order non-linearity described by (3.5), then the resulting (distorted) output sig-nal will be:

[ ]V t AK t K A t

A K A Kt

out ( ) cos( ) cos( )

cos( )

= +

= +

1 2

2

22

22

2 22

ω ω

ω(3.6)

This signal has, in addition to the wanted, linearly amplified signal, a compo-nent at DC and a component at double the input frequency (the second harmonic). Ifthis input signal is an unwanted CW jammer, then the DC term it generates canpotentially exacerbate the DC offset problems discussed above. If it is a modulatedsignal, then it will generate a spectrum around DC and this will appear as unwantednoise or interference to the wanted receive signal. This in turn will lower the receiverSNR. Both of these effects are illustrated in Figure 3.17.

A second effect of a finite IP2 in a direct conversion receiver is that ofdownconverting the leakage of the transmitter output signal which leaks through oraround the duplex filter. Clearly this is only an issue in a full-duplex, frequency-divi-sion duplex, system, with the mechanism being that illustrated in Figure 3.18. Thetransmitter output signal is similar, in virtually all respects, to a blocker as describedearlier and unwanted downconversion occurs by the same means. In this case, how-ever, there are two means of alleviating the problem: improving IP2 (as before) orincreasing the transmit-receive isolation, using better filtering or circuit layout.

The question of which, if either, of these two issues is the dominant requirementon receiver IP2 performance, is not straightforward. In a hostile radio environment,


0.5 1 2 3 5 101

2

5

10

20

50

100

200

Input voltage (volts peak)

Fundamental

Output voltage (volts peak)

Secondorderintercept

Second harm

onic

Figure 3.16 Illustration of the second-order intercept point of a non-linear receiver.

such as one in which multiple, uncoordinated services occupy the same band (e.g.,the situation which existed with CDMA and AMPS at 800 MHz in the UnitedStates), or on a battlefield, where the jammers are likely to be intentional and tohave originated from the enemy, then the first scenario is likely to be dominant. In amore benign radio environment, where terminal cost or size are more of an issue(e.g., consumer walkie-talkies), then sacrifices may need to be made in duplexer per-formance or circuit layout, making the second scenario more likely.

In the case of a WCDMA handset application, it has been suggested that Tx-Rxleakage is the dominant requirement [12]. In either case, the method for calculatingthe required IP2 level is the same, with the exception that a jammer received powerlevel is substituted for the transmit interferer power level discussed next.


Second-ordernonlinearity

Jammer

Wanted

Jammerat DC

fw fj

2fj

Jammer

WantedJammerenvelope atDC

fj fj 2fj

fj

f w 2fw

fw f w 2fw

Figure 3.17 Impact of second-order distortion on CW and modulated jammer signals.

90°

0°In

Duplexfilter

LNA

I-channeloutput

Localoscillator

Q-channeloutput

Transmitter PA

From Txupconverter

Tx

Rx

Tx envelopeat DC

Rx envelopeat DC

TxRx

Figure 3.18 Effect of second order distortion in a direct conversion receiver upon transmit signalsleaking to the receiver input.

The permitted noise power at the input to the receiver is given by:

P P G S G Mn rx s s QPSK C. ,min= + + + − dBm (3.7)

where:

Pn,rx is the permitted receiver noise power (noise floor).

Ps,min is the reference sensitivity required to meet a 10−3 BER.

Gs is the spreading gain (=10log(128)) for WCDMA.

SQPSK is the signal-to-noise ratio required to achieve a BER of 10−3 for anuncoded bitstream.

GC is the expected coding gain.

M is a margin to allow for IP2 degradation and other performance/implementation limitations in the system (assumed to be 0.5 dB, below).

If the coding is assumed to be 1/3-rate convolutional, with constraint length 9,its gain will be 9 dB. Equation (3.7) therefore yields:

Pn rx. .

.

= − + − + −= −

117 21 10 9 05

97 5 dBm(3.8)

The resulting receiver noise figure is therefore:

F P BW kTrx n rx= − −

= − − ×. log( ) log( )

. log( .

10 10

97 5 10 384 106 ) .

.

− −=

17383

105 dB

(3.9)

This is quite a straightforward requirement to meet with current handset chiptechnologies.

If it is assumed that the transmitter is utilising a large number of active channelson the uplink (say, >10), then it is possible to show that this will result in a maxi-mum filtering benefit from the baseband RRC filters of 4.2 dB [12, 13]. This resultsfrom the fact that such a large number of active channels effectively appear as aGaussian noise-like signal. The effects of a smaller number of active channels on theuplink will be considered later.

The assumption, stated earlier, that the allowable degradation (or implementa-tion margin, M) is 0.5 dB, results in a requirement for the second-order distortioncomponents to be at least 10 dB below the receiver noise floor (assuming that all ofthe implementation margin is taken up by the second-order distortion). The sec-ond-order distortion level must therefore be at a maximum level of −107.5 dBm.

If it is assumed that the transmit output power is +21 dBm (class 4 WCDMAhandset), then it is reasonable to assume a worst-case Tx-Rx leakage level of−30 dBm (i.e., 51 dB of isolation in the duplex filter and associated circuit layout).The required receiver dynamic range is then:

PDR = − − − =30 107 5 77 5. . dB (3.10)


The required second-order intercept point is then:

P P PIP DR2

30 77 5

47 5

= +

= − += +

leakage

dBm

.

.

(3.11)

where Pleakage is the power of the transmit signal leaking to the receiver input and PDR

is given in (3.10). The above calculation is also illustrated in Figure 3.19.The IP2 figure presented in (3.10) is quite a tough requirement for a handset,

but does stem from a set of worst-case assumptions (many active channels, only 0.5dB of implementation margin, and so forth). The sensitivity figure calculated in(3.9) is quite easy to achieve in most handset designs and could be tightened up toleave a greater margin for second-order distortion (i.e., a greater implementationmargin, M).

If the number of active transmit channels is only assumed to be 2, simulationspresented in [12] show that a further 9.3 dB of relaxation in IP2 can be allowed. Theresulting IP2 requirement is then a much more reasonable +38.2 dBm.

3.2.3.9 Gain Control Requirements

The lack of channel filtering, prior to baseband, in a direct-conversion receiver,makes the application and design of the receiver AGC system more critical than in


−117.0

Power(dBm)*

Wanted signal power

*All powers are specified with regards to a bandwidth of 3.84MHz unless otherwise indicated.**QPSK SNR coding gain implementation margin.***Required margin to meet 0.5-dB max degradation (implementation margin).

+ +

−107.5

Max level of second-orderdistortion power (without filtering)

−30Interferer (Tx leakage) power

+47.5Second-order intercept point

77.5 dB

77.5 dB

Equivalent wanted signal power(in 3.84 MHz bandwidth)

−96

21dB(spreading gain)

−97.5−1.5 dB**

−10 dB***

Figure 3.19 Derivation of the IP2 requirement in a direct-conversion receiver.

super-heterodyne receivers. The various locations typically used to apply gain con-trol are summarised in Figure 3.20. The precise locations chosen, and the range ofcontrol applied at each point, will depend upon the application and, in particular,on whether the receiver is designed for single-carrier (e.g., handset) or multi-carrier(e.g., base-station) use.

The AGC system is designed primarily to make optimum use of the ADCdynamic range available and to prevent saturation of any of the gain or mixingstages. In a handset (typically, integrated) application, AGC may well be applied ateach of the locations shown in Figure 3.20 and possibly also to the downconversionmixers themselves [14]. Essentially the task of the AGC in this case is to maintain themaximum signal level at each location, while preventing saturation of the signalpeaks. Such saturation, if it occurs, would significantly degrade the BER (or SNR) ofthe system.

In the case of a multi-carrier BTS design, it is likely that higher dynamic rangecomponents can be used and hence incorporating AGC at each location shown inFigure 3.20, is unlikely to be necessary. In this case, however, the setting of the AGCand the dynamic range required from each of the components requires much morecareful consideration. Not only must the signal statistics (e.g., fading) be consideredfor one channel, but the instantaneous dynamic range, for the composite spectrumof all channels to be received simultaneously, must be addressed. In this case, AGC istypically only provided at the LNA (or elsewhere in the RF path), with the remainingcomponents designed to have a high dynamic range. This AGC may also be switchedrather than continuous in nature, with a threshold (or thresholds) and appropriatehysteresis levels chosen, based upon the anticipated signal environment.

3.2.3.10 Multi-Mode Issues with Direct Conversion Receivers

In a multi-mode receiver and, in particular, for handset applications, the ADCdynamic range must be considered carefully. The main issue occurs where the airinterface standards to be received differ significantly in channel bandwidth, therebyrequiring differing baseband channel-selection filter bandwidths. While it is possibleto implement a number of channel selection filters and to switch between these for


90°

0°In

Bandpassfilter

LNA

ToI-channelADC

Localoscillator

ToQ-channelADC

Lowpassfilter

Lowpassfilter

AGC

Figure 3.20 Possible locations for the gain control elements in a direct-conversion receiver.

the different modes, it is more common to utilise a single filter bandwidth, designedfor the widest band signal of interest. In this case, when a narrower band signal isreceived, multiple carriers may be incident on the ADC and the desired carrier maywell not be the strongest of these. This would be true, for example, when a receiveris designed for both WCDMA and GSM. In this case, approximately 19 GSM carri-ers can pass through the baseband filter bandwidth, assuming that it is designed tojust pass the 3.84-MHz WCDMA spectrum.

In this scenario, any of the 18 unwanted GSM carriers could be significantlystronger than the wanted carrier, thereby necessitating the AGC level to be set forthat strong carrier (to prevent saturation of any of the components). The ADC alonemust therefore deal with the strong, but unwanted, carrier and still resolve theweaker, but wanted, carrier. The required dynamic range may therefore be veryhigh in a mobile fading environment.

Providing higher dynamic range in a handset application usually increases thepower consumption of the system and hence multi-mode operation can result in asignificant power-penalty being imposed upon the resulting product. This is in addi-tion to any extra signal processing required to support multiple modes, althoughthis can usually be powered down when not required.

3.2.3.11 Baseband Filter Implementation for an Integrated Direct-ConversionReceiver

The baseband filters employed in a direct-conversion receiver need to have a largedynamic range, as discussed earlier, in order to cope with both strong jammer andweak wanted signals. The noise floor of these filters (and associated basebandamplification) must be sufficiently low that it does not significantly impact upon theoverall cascaded noise figure of the receiver system.

There are three main filter technologies employed in this part of a DCR system:switched capacitor, active RC, and gmC. These three options have various relativemerits in the key specification areas of tuning capability, noise performance,and strong signal handling (i.e., dynamic range) [8]. These relative merits aresummarised in Table 3.1. Filter tuning may be performed on power-up, in any sys-tem, or by utilising vacant time slots in TDMA or TDD systems.

3.2.3.12 Direct Conversion Receiver Employing Both Baseband and Digital IFs

The architecture shown in Figure 3.21 [14] is a novel variation on the direct-conver-sion format discussed above. It is arguable whether it should be described as directconversion at all, since it uses, effectively two baseband IFs and a digital IF. The first


Table 3.1 Relative Merits of Various Baseband Filter Technologies for Use in IntegratedDirect-Conversion Receivers

Filter Type Tuning Capability Noise PerformanceStrong SignalHandling

Switched capacitor Excellent Poor (~20 nV/√ Hz) Good

Active RC Moderate Moderate (~6 nV/√ Hz) Excellent

gmC Good Excellent (~2–4 nV/√ Hz) Poor

downconversion process, at least, is however, direct and hence it is probably mostappropriately discussed here.

Referring to Figure 3.21, the input signal is converted directly to baseband, fol-lowing bandpass filtering and low-noise amplification. The resulting quadraturebaseband signals are then lowpass filtered to define the channel or subband of inter-est, prior to quadrature upconversion to a suitable (low) IF. This IF is chosen tobe appropriate for a low-cost/power consumption A/D converter and is alreadyband-limited by the action of the baseband lowpass filters following the quadraturedownconverter. The resulting digital IF can then be quadrature downconverted,with high accuracy, by the digital downconverter within the digital receiver process-ing block. The primary benefit of this architecture is that it allows the selection of anappropriate IF for use with low power consumption ADCs, in handportable termi-nals. It also requires only a single ADC; a conventional direct-conversion receiverrequiring two.

There are clearly potential issues with quadrature errors in the analoguedownconversion and upconversion processes in this scheme, however these arelikely to be minimised by an integrated (ASSP) implementation of the technique, dueto the high-degree of component matching which can be achieved using this methodof fabrication. The additional complexity and power consumption of the analogueparts of this architecture may also be justifiable, due to the overall reduction inpower consumption, afforded by the optimal choice of ADC and sampling rate,which it affords.

3.2.4 Use of a Six-Port Network in a Direct-Conversion Receiver

A novel, alternative form of direct conversion receiver involves the use of a six-portnetwork (SPN). This type of network was first proposed for use in vector networkanalysers [15, 16] and has since been suggested for use in very high frequency receiv-ers [17]. It is this latter application which is of potential interest in a softwaredefined radio application, since this form of receiver utilises broadband incoherentdetection and passive RF components, thereby making it, to a large extent, modula-tion format and channel bandwidth agnostic. It is also potentially capable of


90°

0°In

Bandpassfilter

Low-noiseamplifier

90°

0°In

Lowpassfilter

Lowpassfilter

A/D

A/Dconverter

Quadraturedemodulator

Quadraturemodulator

In

Digitalquadraturedemodulator

Digitalfilter

Digitalfilter

To I-channelprocessing

To Q-channelprocessing

Digital receiverprocessing block

NCO

First localoscillator

Second localoscillator

90°

0°

Figure 3.21 Direct-conversion receiver architecture employing both an analogue baseband IF and adigital IF. (From: [14]. © 2005 IEEE. Reprinted with permission.)

operation over many decades of frequency. For example, [18] demonstrates the useof a 6-port network for reflection coefficient measurement over the range 2 to 2,200MHz. This range would cover virtually all military and civilian portablecommunications bands in a single receiver.

The format of a basic 6-port discriminator (SPD) is shown in Figure 3.22. As isevident from this figure, the basic discriminator consists entirely of passive couplersor hybrids and diode-based detectors. It is therefore both simple and inherentlybroadband (within the bandwidth limitations of a quadrature hybrid, in the case ofFigure 3.22, although other implementations are possible).

The six-port discriminator, together with its associated A/D converters, replacesthe quadrature downconverter required in a conventional direct conversion receiver.The format of the complete receiver is shown in Figure 3.23. It does not suffer fromthe image or adjacent channel issues inherent in conventional superheterodynereceivers, hence allowing the required (analogue) channel filtering to be relaxed incomparison to those systems. It is reported to be much less susceptible to I/Q errors(gain and phase imbalance in the quadrature hybrids) and also has a superior orequivalent immunity to DC-offsets in the detection system (mixers in a conventionaldirect-conversion receiver, diode detectors in the case of an SPD). The potential for asuperior immunity to DC-offsets arises from the fact that, in an integrated imple-mentation of the SPD (including detectors), it is likely that the DC drift in the detec-tors would occur in the same direction for each of them. In this case, although theoffsets would not necessarily track perfectly, the difference in the DC levels fromeach detector will be smaller than if the drift was random for each detector.

The SPN technique operates by detecting the relative amplitude, phase, and fre-quency (i.e., the frequency offset) of the received signal relative to the local oscilla-tor signal. To do this accurately, the system must be calibrated; however, this isreported to be possible utilising the received signal itself [17]. Calibration must alsobe undertaken at each frequency of interest, for optimum results. An automated cal-ibration scheme is proposed in [19].

The DSP unit performs the necessary calculations in order to provide a demodu-lated signal output and also to provide signal correction, based on the results of thecalibration process.

The main drawback of the technique (other than its requirement for calibration)is that it requires four high-speed analogue-to-digital converters in place of the two


Quadraturehybrid

Quadraturehybrid

Quadraturehybrid

Quadraturehybrid

50ΩDetector

3-dBAttenuator

Localoscillator

Detector

Detector

Detector

RF input

Rx Ouput 1

Rx Ouput 2

Rx Ouput 3

Rx Ouput 4

Figure 3.22 Basic 6-port discriminator.

required in a conventional direct-conversion receiver. The use of diode-based detec-tors is likely, however, to result in better strong-signal handling characteristics andhence this type of receiver may find favour in military SDR applications, where costis less of an issue. It is also easier to use at higher frequencies (e.g., millimeter-waveand above), where conventional mixers are more difficult to fabricate.

3.3 Implementation of a Digital Receiver

3.3.1 Introduction

There are a number of unique aspects of a digital radio implementation which allowa wider choice of options in a receiver design. These options include the use ofoversampling to achieve a lower noise floor than the chosen converter resolu-tion would normally allow and the use of undersampling as a method ofdownconversion. These techniques, together with a range of new mechanisms whichcan add to both spurious and noise specifications, make the design of a digitalreceiver somewhat different to its analogue counterpart. This section will cover themajor aspects of a digital receiver design, suitable for use in a software defined radioapplication.

3.3.2 Frequency Conversion Using Undersampling

Undersampling is the act of sampling a signal at a sampling rate much lower thanone quarter of the Nyquist rate (i.e., much lower than half of the signal frequency). Ifthe signal frequency is, for example, 100 MHz, then the minimum required samplefrequency, the Nyquist sample rate, is 200 MHz (although practical converterswould require this to be at least 250 MHz). This signal would be undersampled byemploying a sample rate of <50 MHz.

Undersampling is an important technique as it effectively performs a frequencymixing function on the input signal, downconverting the signal and, at the same


Low-noiseamplifier

Localoscillator

Bandpassfilter

Basebandvoice/dataoutput

6-portnetwork

Rx ouput 1A/D

Rx ouput 2A/D

Rx ouput 3A/D

Rx ouput 4A/D

A/Dconverters

DSP

Frequency control

6-port discriminator

Figure 3.23 Digital receiver employing a 6-port discriminator.

time, performing the required (pseudo-Nyquist) sampling. The signal is converted(aliased) down to baseband or the first Nyquist zone and sampled as if it had origi-nally been a baseband signal. The process can be described mathematically as:

( )f f fBB IF s= Rem (3.12)

where fIF is the IF input frequency to the A/D converter, fS is the sample rate and fBB isthe resulting baseband frequency. The ‘Rem’ function returns the remainder fromthe division of the items within the brackets, provided that the remainder lies in thefirst Nyquist zone. If the result does not lie within the first Nyquist zone, then itmust be subtracted from the sample rate, fS, to yield the correct baseband frequency.This can be illustrated using the example above: if the 100-MHz input (IF) signal issampled at 15 MHz, the result of the Rem function is:

( )100 15 6

100 15 10

/ ,== =

remainder 10

Rem MHzfBB

(3.13)

Since the remainder in (3.13) falls outside of the first Nyquist zone, which has amaximum frequency of 7.5 MHz for a 15-MHz sample rate, the result must be sub-tracted from fS:

fBB = − =15 10 5 MHz (3.14)

The process of aliasing can also cause spectral reversal, and this needs tobe taken into account when designing the subsequent baseband signal processing.Alternate spectral zones will be reversed and unaltered, starting with the sec-ond Nyquist zone (which will be reversed). This can be summarised as shown inTable 3.2.

3.3.3 Achieving Processing Gain Using Oversampling

Section 3.3.2 considered the benefits which can be gained by undersampling a sig-nal. It is also, of course, possible to oversample a signal (i.e., to sample at a rategreater than that required to fulfil the Nyquist criterion). While this may seemwasteful, it is an important technique as it allows an improvement in signal-to-noiseratio (SNR) to be achieved in the digital domain. It is also worth noting that it is the

3.3 Implementation of a Digital Receiver 85

Table 3.2 Effect of Undersampling on an Input Signal

Nyquist Zone ofInput Signal

FrequencyRange of Zone

SpectrumReversed?

FrequencyTranslation

First DC–fS/2 No None

Second fS/2–fS Yes fS–fIF

Third fS–3fS/2 No fIF– fS

Fourth 3fS/2–2fS Yes 2fS– fIF

Fifth 2fS–5fS/2 No fIF–2fS

Sixth 5fS/2–3fS Yes 3fS–2 fIF

Seventh 3fS–7fS/2 No 2fIF–3fS

bandwidth of the signal that is important. A signal with a bandwidth of 5 MHz willbe oversampled by any sample rate >10 MSPS (SPS = samples per second), althougha practical converter will usually require some overhead on this value (i.e., adequateperformance will probably only be achieved for bandwidths less than about 0.4fS). Itis therefore possible to oversample and undersample simultaneously, sinceoversampling is defined with respect to the signal bandwidth and undersamplingwith respect to its absolute frequency.

The SNR gain which can be achieved in the digital domain results from the factthat the available noise power is now spread over a wider range of frequencies. Theactual amount of noise (or integrated noise) over the whole bandwidth isunchanged, however it is spread more widely and hence the spectral noise densityreduces. It is possible to take advantage of this reduction using digital filtering; thenoise within the bandwidth of the digital filter will be lower than the integratednoise of the original signal, hence providing an effective improvement in SNR.

It is important to note that anti-alias filtering is important in preventing SNRdegradation. It is common to think that an IF filter, which removes any image orspurious products which could fall in-band after sampling, is all that is required inorder to create an uncorrupted spectrum. While this is true for unwanted interferingsignals, it is not necessarily true for noise. It is possible to design a receiver frequencyplan with a relatively wide IF filter (to save cost or reduce size) which adequatelysuppresses images, but which still passes noise in the second Nyquist zone. Thisnoise will be aliased into the wanted band (first Nyquist zone) and will reduce theSNR by 3 dB. A good anti-alias filter can help to reduce this figure.

Assuming that aliased noise is not an issue, the converter noise floor is given by:

( )N N fC s= + +18 602 10 2. . log dBc Hz (3.15)

where N is the converter resolution (number of bits). Thus for every doubling of thesample rate, the converter noise power spectral density reduces by 3 dB.

If a digital filter is employed to remove the unwanted noise surrounding thewanted signal, the processing gain achieved by oversampling can be found from:

GB

fSNRIF

s

=

10log dB (3.16)

This equation assumes that the filter perfectly fits the wanted signal and is ‘brickwall’ in nature. Both of these assumptions can be quite close to reality in the case of adigital filter (unlike their analogue counterparts).

3.3.4 Elimination of Receiver Spurious Products

It is possible, in many designs, to carefully plan the sample rate and the IF spectralposition, to ensure that converter and buffer amplifier harmonics do not cause inter-ference to the wanted signals. All converters will create harmonics and the level ofthese increases the closer the input signal appears to the top of its dynamic range.While these harmonics are unavoidable, careful frequency planning can ensure thatthey are not problematic. Again, the application of near-perfect digital filtering can


help to eliminate these unwanted signals and ensure that the maximum possiblebandwidth is available for wanted transmissions. These techniques can be appliedalongside oversampling and this process extends further the areas of the spectrum inwhich harmonics may fall, without compromising receiver performance.

Note that the other main consequence of amplifier and converter non-linearity,namely, intermodulation distortion, must also be considered carefully, as this is anin-band distortion. It may be possible to eliminate the more problematic effects ofthis by means of digital filtering (i.e., signals appearing around, rather than on topof, the carriers); however, this becomes more difficult as the number of signalsincreases.

As an example of frequency planning, consider the following scenario. A con-verter with a maximum sample rate of 80 MSPS is to be employed to sample a signalwith a bandwidth of 10 MHz. It is possible to determine a suitable IF centre fre-quency which allows the second and third harmonics to be placed out of band, andthis is illustrated in Figure 3.24. The IF needs to be placed between 10 MHz and20 MHz (i.e., the IF centre frequency needs to be 15 MHz). In this case, the secondharmonic will fall between 20 MHz and 40 MHz and the third harmonic between30 MHz and 60 MHz. The top 20 MHz of the third harmonic exceeds fS/2 andhence will wrap around and sit on top of the top 10 MHz of the second harmonicand the lower 10 MHz of the third harmonic. In both cases, this is not a problem, asit does not impinge upon the wanted band. Note that this example takes no accountof the required digital filter roll-off, nor of the practical analogue sampling band-width limitations of a real converter (typically 0.4fS, not the ideal 0.5fS assumedhere). These would both reduce the IF bandwidth which could be employed at thissample rate.

An alternative frequency planning technique is to utilise undersampling andmove the filtering burden from the digital domain to the analogue domain. The key


0 10 20 30 40 50 60 Frequency(MHz)

fS/2

Wanted signal

Second harmonic

Third harmonic

Aliased Third harmonic

Amplitude(dB)

Superimposition of third harmonicand aliased third harmonic

Figure 3.24 Frequency planning to ensure converter harmonics do not intrude on the wantedreceive band.

advantage of this technique is that it allows the whole of the Nyquist bandwidth ofthe converter to be used for the wanted signal—none of it is wasted in frequencyplanning, as was the case in the earlier example. This technique is illustrated in Fig-ure 3.25, where an example is chosen placing the IF in the third Nyquist zone. Sinceharmonic distortion is largely caused in the analogue parts of the converter (bufferamplifiers and analogue input circuitry for the sampling process), it is placed wellaway from the wanted band by this technique. Intermodulation distortion, however,must again be considered carefully, as it will not be alleviated in the same mannerand could cause significant, unwanted interference. If the conversion process itselfstill generates harmonics, these can be dealt with by the first technique, although thisis at the expense of useable converter bandwidth.

In the example shown in Figure 3.25, an 80-MSPS converter is again chosen,however the IF input is now full-band [i.e., it covers the maximum possible (theoret-ical) sampling capability of the converter, 40 MHz]. The IF input to the system isnow in the third Nyquist zone, from fS to 3fS/2 (80–120 MHz) and this places the sec-ond harmonic between 160 MHz and 240 MHz, giving the analogue IF filter 40MHz (between 120 and 160 MHz) within which to roll off to an acceptable level.This is well within the capability of, for example, surface acoustic wave (SAW) filterdevices. The third harmonic falls between 240 and 360 MHz and hence is of littleconcern.

3.3.5 Noise Figure

3.3.5.1 Overall System Noise Figure

The noise factor of a system element (e.g., an amplifier or mixer) is defined as theratio of the signal-to-noise present at the output of the system to that at its input,that is,


0 40 80 120 160 200 240 Frequency (MHz)

fS/2Aliased wanted signal

Second harmonic

Amplitude(dB) Wanted signal (IF input signal)

Analoguefilter passband

Figure 3.25 Using alias downconversion to ensure that converter harmonics do not intrude on thewanted receive band.

F out

in

=SNR

SNR(3.17)

Note that the input and output signal to noise ratios are specified in linear units(not decibels). If the input and output signal-to-noise ratios are identical, then thesystem element has added no noise and its noise factor is unity. All practical ele-ments will add at least some noise and hence F > 1.

The noise factor of a cascaded system (e.g., a receiver) is given by:

F FF

G

F

G G

F

G G GRXn

n

= +−

+−

+ +−

−1

2

1

3

1 2 1 2 1

1 1 1L

L(3.18)

where the various noise factors and gains are defined in Figure 3.26. This equationassumes that all elements of the system are perfectly matched and hence that maxi-mum power transfer occurs. The noise figure of the system can then be found from:

NF FRX RX= 10log( ) (3.19)

In order to determine the receiver performance which can be achieved from agiven system, it is necessary to know the available noise power and the detectionbandwidth (i.e., the bandwidth of the narrowest-band part of the system, typicallythe detector for the modulation). The available noise power from the source (typi-cally an antenna in the case of a receiver) is given by:

P kTBN = (3.20)

where k is Boltzmanns constant (1.38062 × 10−23 J/K), T is the temperature of thesource (in Kelvin), and B is the system bandwidth. At room temperature (290K), ina normalised system (1-Hz bandwidth), this equates to approximately −174dBm/Hz.

Having obtained the cascaded noise figure for the receiver, it is now possible todetermine the noise power obtained at its output, from:

P P NF GN out N dB RX dB, ,= + + (3.21)

where PN,dB is the available noise power (in decibels) and GdB is the system gain(again in decibels). Thus for a receiver with a noise figure of 10 dB and a gain of 40dB, the output noise power at room temperature would be −124 dBm/Hz. This canbe converted to a noise power by adding the logarithm of the detection bandwidth:


G1F1

G2F2

G3F3

GnFn

Figure 3.26 Cascaded noise figure calculation.

P P NF G BN tot dBm N dB RX dB d, , , log( )= + + + 10 (3.22)

where Bd is the detector bandwidth. In the above example, with a detection band-width of 200 kHz, the total output noise power, PN,tot,dBm, is then −71 dBm.

When considering passive elements, including some mixers (e.g., mostdiode-ring based designs) in these equations, their noise figure is equal to their lossand a cascade of lossy elements may be treated as a single element with a loss equalto the combined loss of the individual elements. A common example is a mixer fol-lowed by a filter—the total loss of the two elements should be used.

3.3.5.2 ADC Signal-to-Noise Ratio and Effective Number of Bits (ENOBs)

The signal-to-noise ratio of an ideal N-bit analogue to digital converter is given by:

SNR ideal N= +602 176. . (3.23)

from this it is possible to derive the effective number of bits for a practical ADC:

ENOB measured=−SNR 176

602

.

.(3.24)

The ENOB value for a converter is a much more useful specification than is thearchitectural (designed) number of bits. The ENOB value for a 12-bit, high sam-ple-rate ADC will typically be around 10.5, indicating that the available SNR will bearound 65-dB, not the almost 74-dB value which could be assumed from its 12-bithardware design.

3.3.5.3 Inclusion of ADC Noise

As an ADC is a voltage-driven device, typically with a relatively high input imped-ance, it is usually simpler to deal with it in terms of input-referred noise voltages,rather than assigning it a noise figure. There are therefore three stages to computingthe overall noise floor for the complete receiver, including the converter and itsquantisation noise:

1. Calculate the noise power from the RF and IF parts of the system (asdescribed above) and convert this to a noise voltage.This conversion should be performed based upon the input impedance of theconverter (typically not 50Ω). The noise voltage squared, from the RF and IFparts of the system, is given by:

V P RN IF N tot ADC, ,2 = (3.25)

where PN,tot is the RF/IF output noise power (in watts) and RADC is the inputimpedance of the analogue-to-digital converter in ohms.

Since the converter impedance is normally high (perhaps 1,000Ω), it istypical to lower this impedance using a shunt resistance (say, 200Ω) and thento match the 50Ω output of the RF/IF part of the system to this using a 4:1


impedance transformation. This is illustrated in Figure 3.27. Note that thetransformer also serves a second useful function, namely that of convertingthe single-ended 50-Ω RF/IF subsystem into a differential (balanced) form,as is typically required by an A/D converter.

Taking this example, a total noise power of −71 dBm equates to 7.943 ×10−11 W. The 1:4 impedance transformation in matching this to 200Ωproduces a voltage gain of two times. The rms noise voltage developedacross the A/D input terminals is therefore:

V P R

V

N IF N tot ADC, ,

.

=

= × ×=

−

2

2 7943 10 200

252

11

µ

(3.26)

2. Calculate the ADC input-referred noise (including the effect of quantisationnoise).

The ADC input-referred noise is given by:

V VN ADC FS rmsSNR ADC

, ,= × −10 20 (3.27)

where VFS,rms is the rms value of the full-scale voltage capability of the ADCand SNRADC is the quoted converter signal-to-noise ratio at full scale.

Taking a typical example for a high-performance 14-bit converter, thefull-scale voltage is 2.048-V peak-to-peak and the signal-to-noise ratio atthis input level is 72 dB. The rms noise voltage contribution of the converteris therefore:

V

V

N ADC,

.= ×

=

−2048

2 210

182

72 20

µ

(3.28)

3. Sum the RF/IF and ADC noise voltage contributions (square-root of asum-of-squares).

The two noise contributions may now be combined using:

V V V

V

N RX N IF N ADC, , ,= +

=

2 2

311µ rms(3.29)


ReceiverRF/IF stages 50Ω A/D

converter200Ω 1000Ω1:4 Digital

interface

Figure 3.27 Impedance matching for a receive A/D converter.

This result provides the total noise present at the ADC, including all RF,IF, analogue baseband, and quantisation noise sources.

3.3.6 Receiver Sensitivity

Now that the receiver noise voltage at the ADC input is known, it is possible to cal-culate the overall receiver sensitivity. There are two different scenarios here: singlecarrier reception and multi-carrier reception.

3.3.6.1 Single-Carrier Reception

The signal-to-noise ratio for the receiver is given by:

( )SNR dBRX S N RX SNRV V G= +20log , (3.30)

where VS is the ADC wanted input signal voltage (2-V pk-to-pk in the followingexample), VN,RX is given by (3.29) and GSNR by (3.16). In the latter case, the signalbandwidth, fS , is that of the single carrier being received.

Taking the above example, and assuming that the receiver is only required toprocess a single channel with a bandwidth of 200 kHz (e.g., in a handset applica-tion), the receiver signal-to-noise ratio is then:

( )( )

SNRRX S N RX SNRV V G= +

= × +

=

−

20

20 0707 311 10 699

74

6

log

log . .

,

.12 dB

(3.31)

This assumes that digital filtering is used to select only the wanted channel,hence realising the processing gain in signal-to-noise ratio. This is valid since all ofthe noise present at the input to the ADC (i.e., RF/IF noise and ADC-generatednoise) will be filtered in the digital domain.

This signal-to-noise ratio can then be used to calculate the receiver’s sensitivity,i.e., the minimum received signal power from which a useable signal can beextracted. For a digital modulation format, the minimum carrier to noise ratiorequired for an acceptable bit-error rate (BER) is typically around 10 dB. Based onthe earlier example, the received signal can therefore drop by 64.12 dB while stillallowing the receiver to generate an acceptable BER.

The ADC full-scale input power is +4 dBm (2-V pk-to-pk into 200 ohms); hence,the signal power at the input to the ADC to just achieve an acceptable BER is+4–64.12 = −60.12 dBm. If the gain of the RF and IF stages totals 40 dB (as set previ-ously), then the overall receive sensitivity would be −100.12 dBm.

3.3.6.2 Multi-Carrier Reception

Multi-carrier reception is frequently required in base-station applications and mayalso be required in some remote/portable applications (e.g., for broadcast OFDM).The major difference in this case is that an amount of headroom is required to copewith the fact that the signals could sum in phase and hence produce large peaks.


The theoretical peak voltage level for n carriers, all of equal amplitude, is givenby:

V nVpk n pk, = (3.32)

where Vpk is the peak voltage of any single carrier.Clearly, this indicates that a large headroom may be required in a multi-carrier

base-station application (e.g., 15.6 dB for 6 carriers). This could significantly com-promise the received signal to noise ratio and hence the overall system sensitivity.

In practice, however, each of the carriers typically comes from an independentsource, since the clocks of the transmitting stations (e.g., handsets) are unlikely to besynchronised with each other. The statistical likelihood of the carriers aligningin-phase is therefore very low and hence a more realistic headroom assumption maybe made. A more typical allowance is 3 dB, particularly given that the carriers arealso likely to be identical in power. An exception to this is in CDMA systems, how-ever even here, the high peak-to-average ratio ensures that the likelihood of peaksboth aligning in phase and coinciding in time, is small. In the event that the signalsdo align, the converter will clip and this will cause a momentary overflow conditionto occur. This will, however, be very brief (and infrequent) and the system shouldrecover quickly.

3.3.7 Blocking and Intercept Point

3.3.7.1 Cascaded Intercept Point

In a similar manner to that described above for noise figure, it is possible to calcu-late the effective third-order intercept point of a cascade of elements (amplifiers,mixers, and so forth) from the intercept points of the individual elements. This canbe used to determine an approximate value for the intercept point of a completereceiver front-end as illustrated in Figure 3.28.

The third-order intercept point of the complete signal processing chain is givenby:

IP

IP IP IP IP

31

13 3 3 31

1

2

1 2

3

1 2tot

n

n

G G G G G G=

+ + + LL

(3.33)

where each of the IP3 and gain terms is expressed in linear units (not decibels), thatis,

Gn

G

n

n dB

n dB

=

=

+

+

10

3 10

2

2

10

3 10

, .

, .

/

/IP

IP(3.34)

It is important not to forget about the intercept point units used initially, asthese will usually be specified in dBm, hence producing an intercept point inmilliwatts in linear units. Note also that the above intercept points are at the inputto each stage and that the overall result is therefore an input intercept point. This is


what is typically specified for a receiver system (output intercept point is more typi-cally used for a transmitter or power amplifier).

Converting this input intercept point into an IMD level is achieved using:

( )P P PIMD dB dBm rd dBm, , ,= −2 1 3 (3.35)

where P1,dBm is the power of one tone in a two-tone test, P3rd,dBm is the third-order inter-cept point expressed in dBm and PIMD,dB is the relative power of the third-order (i.e.,largest) IMD products in dBc. In other words:

( )P rd dBm tot3 10 3, log= IP (3.36)

Note that (3.33) assumes that the intermodulation products add in phase (i.e., avoltage addition). If this is not the case, such as for third-order products appear farfrom the carrier (e.g., those around the third harmonic), when significant AM-PMdistortion is present, or where the block non-linearities possess significant memory(with a non-uniform distribution over frequency), then the above becomes (for atwo-stage system):

( )1

3

1

3

1

32

2 1

222OIP OIP OIPtot G

= + (3.37)

This equation is more likely to be appropriate for relatively non-linear poweramplifier systems (hence it is expressed as an output intercept point and is basedupon output intercept point values for the individual blocks). The former equation ismore appropriate for the relatively well-behaved non-linearities present in receiversystems.

Note that where a non-linearity has significant AM-PM and/or memory, theconcept of an intercept point is not necessarily helpful, as it will not readily prove tobe an accurate predictor of IMD performance. The concept of adding IM powers, ina cascaded system, is therefore of relatively limited use, in practice, with (3.33)therefore being by far the most commonly used equation.

3.3.7.2 IMD Level in a Receiver Design

It is typical to design the RF parts of the receiver system to achieve an IMD levelequal to the noise floor at the input to the ADC. In this way, neither parameter dom-inates and the system could not be said to have been over-designed in either area.Like most rules of thumb, however, there are exceptions. In this case, for example,systems in which the signal can be integrated in order to resolve the required


G 1IP31

G2IP32

G3IP33

GnIP3n

Figure 3.28 Cascaded intercept point calculation.

information, should be designed with an IMD performance below the expectednoise floor. This is necessary since integration will not reduce the level of the IMDand hence this will ultimately dominate.

In the case of the example used earlier, the maximum input-referred IMD levelshould be −110.12 dBm measured in a 200-kHz bandwidth and assuming the same10-dB minimum SNR. If the maximum useable RF received signal strength isrequired to be −25 dBm, the resulting input intercept point must be:

P PP

rd dBm dBmIMD dB

3 1 2

2511012 25

217 5

, ,,

( . ( ))

.

= −

= − − − − −

= 6 dBm

(3.38)

This value can then be used in (3.36) and subsequently (3.33) in order to findthe intercept point requirements of the various system blocks.

3.3.8 Converter Performance Limitations

It is instructive at this point, to examine, briefly, the main assessment criteria foranalogue-to-digital converter performance. These criteria are also valid for assess-ing digital-to-analogue converter performance, with similar definitions also apply-ing to that type of component.

Both ADC and DAC components have imperfections which limit their practicalperformance. While many of these issues are present in all converters (bothDC/low-speed and high speed/bandwidth), they are usually most evident in thedemanding high-speed applications associated with software defined radio. Evenwithin a purpose-designed high-speed converter, many aspects of its dynamic per-formance degrade with increasing clock frequency (but still within its specifiedlimit) and with increasing input signal frequency, for a given clock frequency. Eventhe usage recommendations for a good converter (ADC or DAC) will only counte-nance its use with an input frequency up to 0.4fs (where fs is the frequency of thesampling clock)—in other words, up to 80% of its Nyquist frequency.

3.3.8.1 SINAD

SINAD is used as a specification in receiver systems in general as well as specificallyfor A/D and D/A converters within transceiver systems. It stands for signal-to-inter-ference, noise, and distortion (i.e., the ratio of the wanted signal to any form ofundesirable contamination). In the case of data converters, interference is not typi-cally an issue and hence SINAD becomes the ratio of the wanted signal to theunwanted noise and distortion.

For an ideal converter, SINAD is related only to the number of bits present inthe converter:

SINAD dB= +176 602. . N (3.39)


where N is the number of bits. For an ideal 12-bit converter, the SINAD is 74 dB;however, a typical high-speed (100-MHz sampling) A/D converter, for example,may manage a SINAD of only 60 dB.

Equation (3.39) above may be rewritten as:

ENOB SINAD= −( . ) / .176 602 (3.40)

where SINAD in this case is the actual measured value from a given converter. N hasnow become the effective number of bits (ENOB) for the converter. For example, theabove 100-MHz sampling ADC would have an ENOB value of 9.76 (somewhat lessthan the 12 bits it physically produces).

3.3.8.2 Signal-to-Noise Ratio (SNR)

In the case of an ideal converter, SINAD and SNR are interchangeable, since an idealconverter would add no distortion and the only source of noise would be that result-ing from quantisation. In reality, however, the SINAD figure for a converter willalways be poorer than its SNR, due to the presence of distortion in the analogueparts of the system. SNR alone will specify the noise floor of the system, includingdistortion, analogue noise, and quantisation effects, and the latter two can typicallybe improved by the use of oversampling, as discussed in Section 3.3.3.

SNR may be defined as:

SNRSignal Power at FSD

Power of (total) Resid= 10log

ual ErrordB

(3.41)

where FSD is the full-scale deflection (maximum input) of the converter and thepower of the total residual error is the power present in the full Nyquist band of theconverter, other than the wanted signal power. This includes analogue noise,quantisation noise, spurious signals, harmonic and intermodulation distortions, andso forth.

3.3.8.3 Spurious-Free Dynamic Range (SFDR)

Spurious-free dynamic range is defined as the ratio of the rms voltage of an inputsinewave to the rms value of the largest spur, measured using an FFT in the fre-quency domain. The spur need not be a harmonic component of the originalsinewave and could arise as a result of interaction between the sampling clock andthe input waveform. SFDR is normally specified in decibels.

SFDR may be defined as:

SFDRRMS Signal Voltage at FSD

RMS Voltage of the L= 20log

argest SpuriousProductdB

(3.42)

or, in power terms:


SFDRSignal Powerat FSD

Powerof theLargest Spuri= 10log

ousProductdB

(3.43)

SFDR is useful in assessing how well a given ADC will perform when attempt-ing to detect a weak signal in the presence of a strong interferer. It is therefore animportant specification for an ADC that is intended for use in a radio receiver.

The SFDR and SNR of an ADC will almost never be equal, in a practical con-verter. The SNR value incorporates analogue noise and quantisation effects, inaddition to distortion power, and is measured in the entire Nyquist band; it willtherefore result in a value which is typically much poorer than that of the SFDR.SFDR includes only the power of the highest spurious product and hence willalmost always yield a higher value.

SFDR is a useful measure of ADC performance in cases where the signal band-width of interest is less than the full Nyquist band. As has already been outlined inSection 3.3.3, digital filtering may be utilised to improve SNR in this case and henceSFDR becomes a more meaningful method of assessing ADC performance. In par-ticular, a spurious product may fall in the digital filter passband and hence will notbe improved by the filtering process; the SFDR specification for the converter willtherefore predict the converter performance in this case.

There are a number of techniques for improving the SFDR performance of aconverter and these will be discussed later in Section 3.3.10.

In the case of an ideal ADC, the maximum value of SFDR occurs at the convert-er’s maximum input level (i.e., full-scale deflection, FSD). In a practical converter,however, the maximum value of SFDR often occurs at an operating point wellbelow full scale (i.e., several decibels below FSD). This occurs due to the fact that asthe input signal level approaches full-scale, the converter’s transfer characteristicbecomes increasingly non-linear and the advantage of the additional signal power ismore than outweighed by the resulting added distortion.

Furthermore, inevitable fluctuations in the input signal level in a practical cir-cuit, have a much more pronounced effect when operating close to full-scale. This isdue to the fact that small increases in the input level will result in clipping and thiswill lead to a significant increase in distortion. For these reasons, it is important topoperate ADCs a few decibels backed off from their full-scale value, in order toachieve optimum performance.

3.3.9 ADC Spurious Signals

ADC spurii are typically a far greater limitation on receiver sensitivity than straight-forward noise and signal-to-noise ratio. These spurii are caused by eithernonlinearity in the conversion process (traditionally specified as differentialnon-linearity, DNL or integral non-linearity, INL) or slew-rate limitations, whichare generally introduced in the sample-and-hold device on the front end of the con-verter. Sample-and-hold device technology has improved to the extent that this is nolonger typically a major issue in modern high-speed converters operating in the firstNyquist zone, particularly when they are not being utilised at full scale (as is usuallythe case in a radio receiver application). Non-linearities in the conversion processitself are therefore the major problem and the evaluation of these problems in radio


receivers must extend beyond the traditional DNL and INL specifications, in orderto be useful.

The key issue in a receiver ADC is the location of the non-linearity within theADC transfer characteristic. A typical receiver design will not operate the ADC closeto its full-scale limit, other than in very strong signal conditions. A relatively severenon-linearity, say, +1 LSB, occurring at this point, is therefore much less of an issuethan a smaller error, say, +0.25 LSB, half way along the transfer characteristic. Thereason for this is simply that the converter will spend much more of its time with theinput waveform repeatedly transitioning this middle part of the characteristic—anon-linearity here is therefore a much more significant problem.

These issues lead to two different methods of specifying non-linearity in convert-ers: static performance measures and dynamic performance measures. Note that thesame issues are common to both ADCs and DACs and hence the following discus-sions are equally applicable to both. Static performance measures, including INLand DNL, are useful to provide an overall indication of converter non-linearity. It isthe dynamic measures, such as SINAD and SFDR, however, which provide the mostuseful indication of ADC performance in a receiver application.

The impact of ADC spurious signals can be severe and it is this, and not noiseperformance, which is frequently the limitation on receiver dynamic range. Continu-ing the above example, and assuming that the A/D converter has a spurious-freedynamic range of −76 dB relative to full scale (i.e., 76 dBFS), this equates to a spuri-ous level of −72 dBm (for a full-scale input of +4 dBm, i.e., 2-V pk-to-pk into 200ohms). If an acceptable carrier-to-interference (C/I) ratio is 18 dB (note that this istypically greater than the required carrier-to-noise ratio for most systems), thenthe minimum acceptable ADC signal level is −54 dBm. Adding to this the 40 dBof RF/IF gain gives a receive sensitivity of −94 dBm, which compares to thenoise-based receive sensitivity of −100.12 dBm. In other words, noise is clearly notthe limiting factor in this example and a better-designed converter, with animproved SFDR specification relative to its (good) SNR specification, would allowthis SNR to be fully utilised. In this example, the SFDR specification would have toimprove to 83 dBFS or better for converter SNR to become the limiting factor.

3.3.9.1 DNL in a Dynamic Environment

As was indicated above, DNL errors occurring in the middle of an ADC transfercharacteristic are much more significant in a receiver application than those occur-ring close to full scale. The dynamics of radio signal reception are such that opera-tion close to full scale is likely to also result in clipping of the signal and this will, inmost cases, produce much more in the way of spurious products than will the DNLerror. A basic illustration of DNL occurring at different parts of an ADC transfercharacteristic is shown in Figure 3.29. The impact of this upon an input waveform isillustrated in Figure 3.30 for the case where the input signal amplitude is < ±0.375fS.

To understand why DNL errors in high-speed communications converters com-monly occur in the middle portion of the transfer characteristic, it is necessary tounderstand a little of their construction. The use of traditional flash converter tech-niques (see Section 3.3.9.2), for a high-resolution converter, would require a very


large number of high-speed comparators to be fabricated and these would occupy alarge silicon area (hence making the resulting device very expensive). High-speedcommunications converters therefore typically employ multi-stage techniques, withportions of the converter being reused, thereby saving significant silicon area. Thisreuse, however, means that DNL errors present in the reused portion of the con-verter are repeatedly encountered throughout the voltage range of the input signal.Even though these errors may be small (say, 0.25 dB or less), they can still have a sig-nificant impact upon the practical SFDR seen in a radio reception environment.


Input

Codeoutput

(a)

Input

(b)

Codeoutput

0.5fs0.125fs 0.25fs 0.375fss−0.25fs−0.375fs−0.5fs

0.5fs0.125fs 0.25fs 0.375fss−0.25fs−0.375fs−0.5fs

−0.125f

−0.125f

Figure 3.29 DNL occurring in different parts of an ADC transfer characteristic: (a) DNL at mid-scale,and (b) DNL at ±0.375fS.


Codeoutput

Input

Input

(a)

(b)

Codeoutput

0.125fs 0.25fs 0.375fs−0.25fs−0.375fs−0.5fs

0.125fs 0.25fs 0.375fss−0.25fs−0.375fs−0.5fs −0.125f

−0.125fs

Figure 3.30 Effect of DNL upon an input waveform with an amplitude of <±0.375fS: (a) DNL atmidscale, and (b) DNL at ±0.375fS.

3.3.9.2 High-Speed A/D Converter Architectures

Low-Resolution Converter Architecture

A basic high-speed A/D converter architecture, as typically used in low-resolutionvideo applications, is known as a flash converter and is shown in Figure 3.31. It canbe seen from this figure that the operation of this type of converter is essentially par-allel in that all of the output bits are decoded simultaneously. This fact, combinedwith the simple architecture, yields a very low-delay conversion process; it cantherefore be made to operate at very high sampling rates. This type of converterdoes, however, have the drawback that its complexity is proportional to 2N, whereN is the number of bits. As a result, high-resolution converters are either impracticalor uneconomic, when compared to the alternative architectures available. Flashconverters do, however, provide the basis for many of these alternative architec-tures and hence it is useful to understand their operation.

The analogue input signal is fed to a series of comparators, each of which is setto a progressively higher threshold by the resistive ladder network. This ladder net-work sets the thresholds to differ by one LSB of the converter and 2N − 1 compara-tors are required for an N-bit converter. For a 14-bit converter, therefore, 16,383comparators are required; this would clearly yield a large and expensive device.


Analogueonput

Decoder logic Digitaloutput

VREF+

VREF−

Figure 3.31 Flash converter architecture for an ADC.

The results from the comparators must be decoded to provide a usable binaryoutput and this is performed by a fast logic block connected to the comparator out-puts. This decoder logic has 2N −1 inputs and N outputs.

Communications Converter Architectures

In order to overcome the size and complexity issues of flash converters, as discussedearlier, a number of alternative architectures are emerging for high-resolution com-munications converters. A typical high-speed communications converter architec-ture is shown in Figure 3.32. This type of architecture is known as a subranging orpipelined converter and can consist of two or more stages (two are shown in Figure3.32). It operates by re-using the design of a relatively simple n-bit (or n+1 bit) flashconverter (where n is 6, for example, for a 12-bit ADC). The two ADCs operate ondifferent parts of the input waveform, with the first (#1) operating at the higheramplitudes and the second (#2) operating at lower amplitudes. The linear gain stageis a precision amplifier with a carefully controlled gain. It acts to raise the input sig-nal by an amount precisely equal to the range of the first flash converter, therebyallowing the second converter to operate at signal levels below that of the firstconverter.

The purpose of the second (and third) sample-and-hold devices, along with thebuffer following the first flash converter, is to ensure that the samples from the twoconverters arrive at the same time; these two blocks are therefore acting as delay ele-ments. These delays lead to an overall delay between the sample clock edge and thesampled data which results from it. The sample clock for sample, S, will result indata for sample S − L, where L is the number of clock cycles of latency within theconverter. This latency is typically small, at around two or three cycles.


S/H

A/D

n-bit flashconverter (#1)

D/A

n-bit precisionDAC

Sample andhold #1

Buffer

Analoguesignals

n-bit digitalsignals

A/D(n+1) bit flashconverter (#2)

Error correction register

Output register2n-bit digitalsignals

Analogueinputsignal

S/H

Sample andhold #2

Linear gainstage

(n+1) bitdigital signals

Sample andhold #3

S/H

Figure 3.32 Architecture of a typical high-speed communications converter.

The error correction register ensures that the two converters mesh together cor-rectly, and will correct for errors made in the first conversion process. The types ofproblems which can be corrected include gain, linearity, and offset errors within thefirst ADC, so long as they fall within the range of the second ADC. It will not, how-ever, correct for errors in either the DAC or the linear gain stage, both of which willresult in non-linearities in the output (digital) waveform, nor will it correct forerrors in the second ADC. These will again translate directly as errors in the com-plete ADC characteristic.

The DAC following the first flash converter must be a high precision compo-nent, as it must be accurate to at least the resolution of the complete ADC (i.e., 12bits for the n = 6 example above). This is important, as the signal it produces is sub-tracted from the input signal, to leave the lower level portion of the input signal tobe sampled by the second converter. Any inaccuracy in this DAC, even below itslevel of operation, will result in severe errors in the second converter. This is again apotential source of DNL error. Note that the first flash ADC must also have at leastthe precision of the complete ADC, for the same reason.

It is possible to extend the pipelining principle to multiple stages, therebyachieving higher resolution performance from relatively simple ADC buildingblocks.

Sigma-delta converters are also emerging from the audio field, where they havebeen in use for many years, and are seeing applications in communications designs.They are particularly useful in bandpass sampling applications, where they may beused to select and alias-downconvert a single channel or group of channels. Theyhave yet to achieve the effective sampling rates available from other converter archi-tectures, but significant work is being directed in this area with a view to resolvingthe issues involved.

A converter is reported in [20] which operates with an input frequency range ofbetween 10 and 300 MHz and a channel1 bandwidth of between 10 kHz and 200kHz. The reported SNR reduces from 88 dB to 75 dB across this range. This con-verter would be adequate for use in an SDR receiver application, based aroundnarrowband channels (e.g., TETRA, GSM, EDGE, DAMPS, and PDC). It wouldstill, however, require an initial downconversion stage, due to the more than400-MHz and above frequency allocations of these systems.

More recently, a sigma-delta converter designed for single-channel CDMAreceivers has been reported [21]. The converter has an RF input capability of up to 2GHz, with a signal to noise ratio of 79 dB when operating on a channel bandwidthof 1.23 MHz. This device was fabricated on a 0.18µ CMOS process and occupiedan area of less than 0.9 mm2.

Finally, a recent converter [22] has been described for multi-mode operation inUMTS, CDMA2000, GSM-EDGE and GSM applications. The receiver architecturewithin which the converter was designed to operate employed a zero-IF in UMTSand CDMA2000 modes and a low IF (100 kHz) in GSM and EDGE modes. Thespecifications required of the ADC, for each mode of operation, are summarised inTable 3.3.


1. Channel bandwidth in this case refers to the instantaneous passband bandwidth over which signals can beconverted this bandwidth may, in fact, contain a number of adjacent or near-adjacent channels (e.g., 8 × 25kHz channels in the reported 200-kHz maximum bandwidth).

This latter device utilised a fifth-order feedforward Σ∆ modulator anda switched-capacitor feedback DAC; the latter to reduce the negative effectof pulse-width jitter on the dynamic range of the converter. The final reported per-formance of the ADC is outlined in Table 3.4, with the device having been fabricatedin standard 0.18µ CMOS.

It is clear from the advances in this technology, which have occurred over thelast 3 years (as illustrated by the above three examples) that sigma-delta techniquesare now at the point of warranting serious consideration for use in generic softwaredefined ratio applications, particularly for single-carrier handset applications.

3.3.9.3 Using Probability to Assess Converter Dynamic Performance

As is evident from the earlier discussion, the impact of DNL errors upon the perfor-mance of an ADC in a radio reception application will depend critically upon thefrequency of transition of the input waveform across the non-linearity. This isclearly a probabilistic situation and can be examined in two ways.

The simplest assumption is that the converter is being fed with a sinewave with apeak amplitude, Apk, which is less than the full-scale voltage capability, Vpk, of the


Table 3.3 Performance Requirements for a Multi-Mode Σ∆ ADC [22]

Mode UMTS CDMA2000 EDGE GSMReceiver topology ZIF ZIF LIF LIF

Channel bandwidth (kHz) 3840 1228 270 190

SNR specification (dB) 70 80 87 90

Noise density [nV/√Hz] (Vin,max = 1Vrms) 228 128 85 72

ADC sample rate (MSPS) 153.6 76.8 26 26

Calculated thermal SNR (dB) 78 85 88 90

Calculated quantisation SNR (dB) 82 103 102 105

Calculated total SNR (dB) 76 85 88 90

Table 3.4 Measured Performance from a Multi-Mode Σ∆ ADC [22]

Mode UMTS CDMA2000 EDGE GSMReceiver topology ZIF ZIF LIF LIF

Channel bandwidth (kHz) 3840 1228 271 200

Dynamic range (dB) 74 83 90 92

Noise density [nV/√Hz](Vin,max = 1Vrms)

228 128 85 72

ADC sample rate (MSPS) 153.6 76.8 26 26

Oversampling ratio 40 64 48 65

IM2 suppression (dB) >110* >98 >110* >110*

IM3 suppression (dB) >87 >91 >97 >97

Image rejection (dB) >50** >50** >50** >50**

Input voltage range 1V rms, differential

Total silicon area 0.55 mm2

*Result limited by measurement noise floor. ** Measurement limited by test setup.

converter. In this case, the probability of any code (the Ith code) appearing at theoutput to the converter is given by [23]:

( ) ( )P

V I

A

V I

AI

pkN

pkN

pkN

=−

−

− −−

−−

−1 2

2

1 21

1

1

1

πsin sin

pkN2

(3.44)

where N is the converter resolution (bits) and I is the code under consideration.The probability of the converter operating in a given top percentile of its range,

based upon a full-scale sinewave input, is given by:

PV

TT= −

−1001

2001

πcos (3.45)

where VT is the upper percentile in question.Conversely, for operation in the middle of the converter range, the probability is

given by:

PV

MM=

−100200

1

πsin (3.46)

where VM is the mid-percentile in question.If these two equations are evaluated for a percentile value of 0.1%, the corre-

sponding values for the two probabilities are PT = 1% and PM = 0.016%. It is clearfrom this that the converter is much more likely to be generating a code close to fullscale than it is to be generating a code around mid-scale. The conclusion here is thatDNL problems with mid-scale codes are likely to be less of an issue than those withfull-scale codes.

However, as discussed earlier, a converter in a radio receiver is likely to operatefor most of the time significantly backed off from full scale. For example, a con-verter operating at 25-dB backoff will only be utilizing approximately 5.6% of theavailable codes (assuming that the converter has a large number of bits). For a14-bit converter, assuming that it has four bad codes in the middle of its range, thepercentage of the time during which these codes are utilised for varying degrees ofbackoff are presented in Table 3.5. It is evident from this table that the higher thedegree of backoff, the more frequently the bad codes are exercised and hence thegreater the amount of distortion generated. Bad codes occurring close to full scale,by contrast, would not be utilised at all in most cases, and hence would contributenothing to the overall distortion characteristic.

The alternative method of evaluating this problem is to assume that the inputsignal to the receiver is noise-like, with either a Gaussian distribution (e.g., forCDMA) or a Rayleigh distribution (e.g., for a narrowband single-carrier receiveroperating in a mobile environment, a good example being GSM). The earlier argu-ments still apply, although the transitions through bad codes lower in the ADCtransfer characteristic may be more frequent due to the high peak to mean of thistype of signal.


3.3.9.4 Impact of DNL on a High-Speed Converter

Section 3.3.9.2 described a typical converter architecture for a high-speed communi-cations converter. It is clear from the operational description of this converter thatthe second ADC is used many times over the full-scale range of the complete con-verter. Any DNL errors in this converter will therefore appear many times within thefull-scale range of the complete converter −2n times in fact, where n is the number ofbits in the first converter. Thus, in a 12-bit converter, consisting of a 6-bit first con-verter and a 7-bit second converter, the DNL errors in the second converter willrepeat 26 = 64 times over the range of the complete 12-bit ADC.

The impact of this on the signal-to-noise ratio for the converter (assuming that itis the dominant effect) is given by:

SNRDNL, logdB N= − +

201

2

ε(3.47)

where is the average DNL of the converter and N is its resolution (number of bits).This equation is illustrated in Figure 3.33, for a range of values for DNL error andconverter resolution.

It can be seen from this figure that the signal-to-noise ratio degrades from itsideal value (based on quantisation noise, at 0 LSBs of DNL error) to a lower value asthe DNL error increases. The effect is gradual, but very important, as it reduces theeffective number of bits (ENOBs) of the converter. For example, a 12-bit converterwith 3 LSBs of DNL error effectively becomes a 10-bit converter in terms of the sig-nal-to-noise ratio.

3.3.9.5 INL Error

Intergral non-linearity (INL) is the deviation from an ideal straight line in the staticinput-output transfer characteristic of a converter. The overall shape of this charac-teristic can be analysed to yield the harmonic and intermodulation characteristicsfor the converter. It may also be possible to use this information either to predistortor postdistort the converter characteristic in order to minimise the impact of the INLerror upon system performance. This is most easily undertaken in the digitaldomain, where predistortion of a DAC or postdistortion of an ADC is possible. Theaim of both techniques is to yield an overall cascaded linear transfer characteristic


Table 3.5 Effect of Bad Codes with Backoff for an A/D Converter

Degree of Backofffrom Full Scale (dB)

Utilisation ofConverter Range (%)

Utilisation ofBad Codes (%)

10 31.6 0.077

20 10 0.244

30 3.16 0.772

40 1.00 2.44

50 0.316 7.72

60 0.1 24.4

for the system (composed of two complementary non-linear characteristics). Thistechnique is illustrated in Figure 3.34.

3.3.10 Use of Dither to Reduce ADC Spurii

The dynamic problems with DNL highlighted earlier can lead to a significant num-ber of spurs appearing in the output spectrum of a communications ADC. While it isnot possible to reduce the overall energy of the distortion caused by DNL errors, itcan be distributed across the frequency band of the converter, thereby eliminatingdiscrete spurii and replacing them with a slight overall increase in noise floor. Thisincrease in noise floor is usually much more acceptable in a radio receiver applica-tion than discrete spurii, since a badly located spurious signal can severely compro-mise a receiver’s dynamic range performance.

The method of achieving this is called dither and it involves the addition of anoise source to the ADC input signal. The result of this is to effectively randomisethe DNL errors in the ADC characteristic, thereby spreading the converter spuriiand creating a uniform noise floor. A range of methods exists to achieve this andtwo of these are illustrated in Figures 3.35 and 3.36.

The method shown in Figure 3.35 places the dither signal entirely within theADC operating bandwidth, thereby decreasing the SNR of the resulting system.This is overcome by digital subtraction of the pseudorandom binary sequence(PRBS) from the ADC output signal, thereby removing the added noise (but leavingthe additional noise created by the spreading of the spurious signals). This method isuseful when either large amounts of dither are required to overcome the (large)DNL errors within the ADC, or the entire input frequency range of the ADC isrequired for wanted signals. If there is a small amount of unused input frequencyrange (say, a few hundred kilohertz), then it is possible to arrange for the dither sig-nal to appear in this range. This has the advantage that the dither signal does notrequire subsequent subtraction, hence making the additional circuitry required to


4 bit6 bit8 bit

10 bit12 bit14 bit16 bit18 bit20 bit

0 1 2 3

DNL error (LSBs)

Sign

al-t

o-no

ise

ratio

(dB)

20

30

40

50

60

70

80

90

100

110

120

Figure 3.33 Effect of DNL errors upon signal-to-noise ratio for an ADC.

implement dithering very simple. Furthermore, it does not require any additionalDSP overhead, thereby enabling the design to be purely analogue.

There are two obvious locations for the out-of-band noise signal in a receiverapplication: around DC (shown in Figure 3.36) and around fS/2. Either or both ofthese locations are commonly unused in receiver designs, since they can cause prob-lems in the remainder of the system (e.g., swamping the ADC with carrier leakage atDC). They are therefore ideal locations for placement of the dither spectrum.


A/Dconverter

D/A

D/Aconverter

Postdistorter

Predistorter

A/D

(a)

(b)

Digital domain Analogue domain

Digital input Analogue output

Digital domainAnalogue domain

Analogue input Digital output

Figure 3.34 INL correction of a data-converter:(a) predistortion of a DAC; and (b) postdistortion ofan ADC.

A/D

Receiver ADC

D/A

Analoguesignals

N-bit digitalsignals

Analogueinputsignal

DigitalPRBSgenerator

Dither source DAC

ADC outputsignal

Figure 3.35 Wideband dither approach employing subtraction to remove in-band noise.

The addition of the dither signal effectively randomises the DNL errors withinthe converter dynamic range. This eliminates the repeated nature of the DNL codes,discussed in Section 3.3.9.4, and enables them to resemble a more uniform distribu-tion. A given input voltage level will not, therefore, result in a specific good or badcode, but instead will produce a random distribution of both good and bad codes.

The amount of dither required for a particular converter is usually best arrivedat experimentally. Alternatively, manufacturers data sheets or application noteswill sometimes indicate the optimum number or range of codes of dither for theirproducts or an equivalent dither power. Some are even beginning to incorporateSFDR optimisation circuits within their converters.

It is important to note that dither will only improve SFDR up to the point wheretrack-and-hold device errors dominate. Dither is therefore typically of value atlower frequencies, where track-and-hold errors will be small. What constituteslower frequencies will depend upon the converter in question. Many modern com-munications converters are designed with track-and-hold devices that operate wellbeyond the first Nyquist zone; indeed, such converters are typically intended foralias downconversion applications. In this case, lower frequencies may actuallyrefer to many times the Nyquist frequency, and hence track-and-hold device errorsmay not be an issue in practice.

The broadband Gaussian noise source shown in Figure 3.36 can be realised ina number of ways. Perhaps the simplest method is to use a noise diode, followedby a fixed or variable gain amplifier. An outline of this solution is provided inFigure 3.37. In this case, D1 is the noise diode, with R2 and C (primarily) form-ing a highpass filter for the noise, prior to amplification and level control. Thehighpass filter is largely concerned with DC removal, but may also be used forrudimentary noise shaping.

3.3.11 Alternative SFDR Improvement Techniques

Although dither is a commonly used technique for improving SFDR, a number ofother options exist. These options typically involve processing of the digital infor-mation, following digitisation by the ADC. They include:

1. Phase-plane compensation [24];2. State-variable compensation [25];3. Projection filtering [26].

3.3.12 Impact of Input Signal Modulation on Unwanted Spectral Products

The increasing application of wideband modulation formats, such as spread-spec-trum and OFDM, has an impact upon the way spurious products can be treated inan ADC. The harmonics generated by an ADC are harmonics of its input signal; as aresult, they will occupy a bandwidth related to that input signal. For a second har-monic, the input signal bandwidth is doubled and for a third harmonic it is trebled,and so forth. Since these wideband signals are effectively noise-like, their harmonicswill also be noise-like and of a wider bandwidth. It is therefore more appropriate totreat them as a noise signal and examine their impact as a degradation in SNR


performance (often referred to as SINAD-signal to interference, noise, and distor-tion). The same is also true for intermodulation products and ADC spurii (e.g.,created by DNL errors).

3.3.13 Aperture Error

The term aperture error refers to the imperfections present in the actual samplingprocess itself. In an ideal converter, the sampling process is instantaneous, with nosignal leakage occurring during its operation. In a practical converter, however, thesampling process takes a finite time and hence the input signal is not convolved withan ideal impulse function it is, instead, convolved with a one-sided triangularimpulse function (see Figure 3.38). This results in a sampling error which is depend-ant upon the frequency of the input signal; at low input frequencies, the imperfectimpulse function mentioned earlier is sufficiently narrow to appear perfect, andhence sampling occurs normally. At high input frequencies the input signal leakage


A/D

Receiver ADC

AnaloguesignalsN-bit digitalsignals

Analogueinput signal

BroadbandGaussian noisesource

ADC outputsignal

Low-passfilter

Figure 3.36 A simple out-of-band dither technique to reduce the effect of ADC spurii.

A

R1

C

+VCC

R2

VR

1

Vn

D1

Figure 3.37 Simple analogue noise generator to provide dither for an ADC.

referred to earlier occurs, yielding (potentially) a different output code for the sameinput voltage as was applied in the low-frequency case.

In practice, such errors have a similar impact to those of slew rate limitationsand are indistinguishable in the output spectrum. They are also generally small andare therefore masked by slew-rate limitations in most converters.

3.3.14 Impact of Clock Jitter on ADC Performance

One of the principal factors which can degrade SNR, from that based onquantisation alone, is clock jitter. The result of jitter is an uncertainty (error) in thevoltage at the sample point, as illustrated in Figure 3.39. Although this figure refersto an ADC, a similar mechanism occurs in a DAC.

Jitter in a clock oscillator is the time domain representation of phase noise in thefrequency domain. In common with low-phase noise requirements in conventionalhigh-frequency oscillators, the best low-jitter sources are quartz crystal based.These are typically capable of better than 0.2 ps of jitter.

The other main source of clock jitter is the buffer between the clock source andthe ADC or DAC. The use of an AC-coupled, differential ECL/PECL buffer is onegood solution, as it has very fast outputs, matched in terms of slew rate.

The impact of clock jitter is related to the slew rate of the input signal. Thegreater the slew rate, the greater the error voltage for a given amount of jitter; thegreatest slew rate occurs at the zero crossing of the highest-frequency sinewave ofinterest (as shown in Figure 3.39). A perfect clock would sample at the ideal pointshown, with the impact of jitter being to cause the actual sampling point to shifteither side of this point (randomly) by an amount determined by the jitter. Theresulting voltage error is given by:

V S terr R jitter= (3.48)


(a)

(b)

Time

Time

Figure 3.38 (a) Ideal and (b) practical sampling impulse functions for an ADC.

where SR is the maximum slew rate of the input sinusoid and tjitter is the timing uncer-tainty of the clock.

In the case of a sinusoidal input signal:

ν πs M int V f t( ) sin( )= 2 (3.49)

The slew rate can be found from:

ddt

t f V f ts in M inν π π( ) cos( )= 2 2 (3.50)

This reaches its maximum when t = 0, giving:

ddt

t f Vs in Mν π( )max

= 2 (3.51)

The impact of clock jitter upon the SNR of the converter is therefore:

SNRj,dB = −20 2log( ),πf tin j rms (3.52)

where fin is the maximum input frequency of interest (in hertz) and tj,rms is the rmsvalue of the jitter (in seconds). This equation assumes that jitter is the limiting factorand not quantisation noise. If the SNR derived from jitter alone is below the theoret-ical SNR from quantisation noise, then (3.47) will take precedence. Equation (3.52)is illustrated in Figure 3.40 at a range of values for jitter and input frequency. Notethat this figure only provides an accurate idea of SNR in the case where apertureuncertainty is the dominant source of SNR degradation (i.e., it dominates both ther-mal noise and DNL).

The greatest impact of jitter occurs in an IF sampling (alias downconversion)system. In this case, the input frequency to be used in (3.52) is potentially high (hun-dreds of megahertz, perhaps), hence making the jitter of the sampling clock a criticalparameter. As a typical example, a 100-MHz analogue input signal, being sampled


Inputwaveform

Intendedsamplepoint

Actualsamplepoint

Verr

∆t

Figure 3.39 Effect of clock jitter on the conversion process for an analogue-to-digital converter.

using a clock with a jitter of 0.8-ps rms, would yield a maximum possible sig-nal-to-noise ratio of 66 dB. This is equivalent to an ENOB of 11 bits, and hence anexpensive 14-bit converter, for example, would be wasted in this scenario. For a14-bit converter to be potentially useable (to its full dynamic range capability), theclock jitter would have to reduce to 0.1 ps. This is a very challenging figure to meetin a practical clock source at present.

The theoretical phase noise performance of an RF oscillator is governed byLeesons equation [27] and further details of this model, and its implications foroscillator circuit design, are provided in Appendix B.

3.3.14.1 Combined Noise Performance

Clock jitter (or aperture uncertainty) alone is not the only limitation on the noiseperformance of a converter. As has already been discussed, DNL and thermal noiseboth contribute to the overall noise and hence all three effects must be analysedtogether. This results in an overall signal-to-noise ratio given by [28]:

( )SNRtot,dB = − + +

+176 20 21

2

2 222

. log ,πε

f tV

in j rms N

n ,rms

N2

2

(3.53)

where:

fin is the maximum input frequency of interest (in hertz).

tj,rms is the rms value of the jitter (in seconds).


10 20 30 40 50 60 70 80 90 100Frequency (MHz)

Sign

al-t

o-no

ise

ratio

(dB)

10

20

30

40

50

60

70

80

90

100

110

120

1300.1 ps0.3 ps

1 ps3 ps

10 ps30 ps

100 ps300 ps

1000 ps

Figure 3.40 SNR degradation caused by clock jitter for a selection of input frequencies.

is the average DNL of the converter (in LSBs).

Vn,rms is the thermal noise (in LSBs).

N is the number of bits for the converter.

Evaluating each of the three terms in the above equation separately allows anassessment to be made as to which is dominant (if any). Clearly it is potentiallyextravagant to specify a clock jitter such that DNL and/or thermal noise dominatesto a significant degree.

Figure 3.41 illustrates the impact of clock jitter on the signal-to-noise ratio avail-able from a range of ADCs [based on (3.53)]. The parameters are selected to be typi-cal of a current digital-IF receiver, using a current-generation of ADC, namely, aDNL error of 0.5 LSB and an input frequency of 20 MHz. In this example, the effectof thermal noise is neglected, although clearly this would degrade the figures pre-sented, in a practical application.

It is evident from Figure 3.41 that an extremely low-jitter clock is required if thefull performance from a high-speed, high-resolution converter is to be realised. Forexample, a 16-bit converter requires the jitter present on the clock to be better than0.1-ps rms, in order to avoid significant degradation of the signal-to-noise ratio. Ifthe clock jitter is increased to 1 ps, the SNR performance of an ideal 16-bit converterbecomes almost identical to that available from an ideal 14-bit converter; the addi-tional resolution available from the 16-bit device is therefore wasted.

Turning now to a potential future requirement and looking at the case of anRF-sampling ADC, with an input frequency of 2 GHz (and the same DNL of 0.5LSB), the jitter requirement changes dramatically, as is illustrated in Figure 3.42. Inthis case, even a 12-bit ADC will require a clock jitter of 0.01-ps rms, or better, inorder to achieve its full (theoretical) performance. For the 16-bit example used


10−2.00 2 3 4 5 6 7 2 3 4 5 6 7 2 3 4 5 6 7

40

60

80

100

120

RMS Jitter (ps)

Sign

al-t

o-no

ise

ratio

(dB)

20

10 1010−1.00 0 0. 0 1 0. 0

20-bit18-bit16-bit14-bit12-bit10-bit

8-bit6-bit4-bit

Figure 3.41 Impact of clock jitter on ADC signal-to-noise ratio for a range of values of converterresolution. DNL error = 0.5 LSB; input frequency = 20 MHz. Thermal noise contribution is assumed tobe negligible.

earlier, the required jitter must now improve to 1fs—an extremely difficult value toachieve, particularly given the high clock frequency (>>4 GHz), which would berequired for Nyquist sampling of the high input frequency.

To gauge how realistic these specifications are, in practice, it is worth examiningthe jitter specifications for current, high-quality crystal oscillators. A brief examina-tion of commercially available parts indicates that for a 1-GHz output frequency(still far from the more than 4 GHz required), a clock jitter of 13 ps is realistic. Thisis a long way from the 1fs requirement discussed earlier, thus illustrating the extremetechnological challenges which must be overcome before high-resolution RF sam-pling techniques can become a reality. This issue is, of course, in addition to the con-siderable challenge of designing and fabricating the converter itself a feat which isalso some way from being achieved (as was discussed in Chapter 2).

3.3.14.2 Impact of Clock Oscillator Phase Noise on Jitter

The phase noise present on a clock oscillator will clearly impact the amount of jitterit suffers. There is a direct relationship between the two parameters and this is givenby [29]:

( ) ( )[ ]σ τπ

π τpn

fTL f foffset2 0

2

2

2

0

2( ) sin= ∫ df (3.54)

where:

pn ( ) is the rms jitter (in seconds).


10−1.0 0.02 3 4 5 6 7 2 3 4 5 6 7 2 3 4 5 6 7

s

20

40

60

80

100

120

20-bit18-bit16-bit14-bit12-bit10-bit8-bit6-bit4-bit

RMS Jitter ( )f101010

1.0 2.0

Sign

al-t

o-no

ise

ratio

(dB)

Figure 3.42 Impact of clock jitter on ADC signal-to-noise ratio for a range of values of converterresolution. DNL error = 0.5 LSB; input frequency = 2 GHz. Thermal noise contribution is assumed tobe negligible.

T0 is the period of the clock oscillator (in seconds).

≅ NT0 is the time after the Nth period.

foffset is the maximum offset frequency of interest (in hertz).

L(f) is the phase noise spectral density relative to the carrier at an offset f(usually expressed in dBc/Hz).

This equation is typically evaluated by numerical integration based on a plot ofphase noise taken from the clock oscillator. It is usually beneficial to calculate jitteron an oscillator in this manner, since jitter measurement equipment is usually muchless sensitive than phase noise measurement equipment. It is therefore possible toarrive at a jitter figure for a very high performance oscillator, via (3.54), when it isnot possible to measure it directly.

3.3.14.3 Impact of Clock Oscillator Spurs on Jitter

A practical clock oscillator may well have one or more spurs forming a part of itsphase-noise characteristic. These spurs can occur anywhere in the spectrum sur-rounding the oscillator and may arise from a variety of causes, such as modulationappearing on the oscillator supply, breakthrough from other oscillators or signalswithin the unit, and so forth. An illustration of the typical form of an oscillator char-acteristic is shown in Figure 3.43, with the spur in this case occurring where theclose-in phase noise characteristic meets the broadband noise floor of the oscillator.

Clearly these spurs are an undesired component and they will have an impactupon the jitter resulting from the clock oscillator. It is possible to calculate theimpact of spurs upon jitter, using [29]:


Phase noise(dBc/Hz)

Offset frequency(log scale)

Close-inphase noise

Spuriouscomponent

Noisefloor

Figure 3.43 Typical phase-noise characteristic for a clock oscillator, incorporating spuriouscomponents.

( ) [ ]σ τπ

π τs m mm

TL f f2 0

2

2

2( ) sin= ∑ (3.55)

where:

s ( ) is the rms jitter (in seconds).

T0 is the period of the clock oscillator (in seconds).

≅ NT0 is the time after the Nth period.

L(fm) is the spurious amplitude relative to the carrier (usually expressed indBc).

fm is the offset from the oscillator (centre) frequency (in hertz) at which thespurious component occurs.

m is the number of spurious products—note that the spurious products arenot assumed to be symmetrical and hence the impact of those above andbelow the carrier must be assessed separately (i.e., m = 2 for a pair of spuriousproducts, one above and one below the carrier).

For a typical spur level of −75 dBc, at on offset up to 1% of centre frequency, theimpact upon clock jitter is negligible (many orders of magnitude less than theimpact of phase noise) [30]. Even higher spurs or a greater number of spurs is likelyto have little impact, unless very low jitter (say, less than 0.1 ps) is being considered.

3.3.14.4 Combined Thermal and Quantisation Noise

The ADC noise voltage may also be computed, for any signal level within the ADCinput range (i.e., not just at full scale), using (3.56):

V Zn tq in

FS SNR SdBm dBc dBFS

, = ×−

− −

10 103 10 (3.56)

where Zin is the input impedance (Ω), FSdBm is the converter full-scale power (indBm), SNRdBc is the measured signal-to-noise ratio at the chosen input level (in deci-bels, relative to the signal level), and SdBFS is the chosen input signal level (in decibels,relative to the converters full-scale input capability).

The converter full-scale power, FSdBm, may be calculated using:

FSV

ZdBmFS rms

in

=

10

103 2

log , (3.57)

where VFS,rms is the converter full-scale voltage input, expressed in volts rms.

3.3.15 Impact of Synthesiser Phase Noise on SDR Receiver Performance

In many respects, synthesiser phase noise is similar to clock jitter in its impact uponreceiver performance (i.e., it imposes a degradation on the signal-to-noise ratio).


The key difference is that phase noise has a non-uniform distribution around theoscillator frequency. It is typically severe close to this frequency and reduces as fre-quency separation increases. Clock jitter, on the other hand, results in a uniform dis-tribution (and hence a uniform SNR degradation). The impact of synthesiser phasenoise on EVM performance is considered elsewhere in this chapter and hence thissection will concentrate on SNR issues.

The local oscillator is mixed (multiplied) with the input signal in thedownconversion mixer; this results in a convolution of the input signal and LO spec-tra in the frequency domain. The result of this is that both adjacent signals and partsof the wanted signal are mixed with the phase noise and this leads to an increasedin-channel noise floor. This process is known as reciprocal mixing.

Continuing the earlier example of a handset application with a receiver channelbandwidth of 200 kHz and assuming that the design goal with respect to phase noiseis that it should be similar to, or lower than, the thermal noise power from theantenna (at 290K):

N kTAnt,dBm

dBm Hz

=

= −174(3.58)

Assuming that the maximum wanted signal power is as stated previously (−25dBm) and that this signal is noise-like, with a uniform distribution over its 200-kHzbandwidth, then the signal power per unit bandwidth is −78 dBm/Hz.

The maximum permissible phase noise power at an offset of 200 kHz (first adja-cent channel), assuming a uniform phase-noise distribution across the 200-kHz sig-nal bandwidth, is then:

PN

dBm Hz

= − − −= −

174 78

96

( ) (3.59)

This latter assumption is clearly somewhat optimistic, as most phase-noise pro-files show a decreasing phase noise power with increased separation from the carriercentre frequency. This result (and method) could, however, be used as either aworst-case figure (to specify the phase noise requirement at the channel edge closestto the receiver centre frequency, in the case of reciprocal mixing) or to inform anestimate for the offset-channel (unwanted channel) centre frequency. A much bettermethod is to consider the effect of the phase-noise on error vector magnitude(EVM), as will be outlined later in this chapter. This method allows the designer toassess the impact of phase noise on the actual signal quality and hence demodulatederror performance and should be used in preference to the above, rather simplisticmethod whenever possible.

3.3.16 Converter Noise Figure

In a cascaded system analysis, it is sometimes useful to be able to calculate the noisefigure of the ADC, as the final element in the receive chain. A key difference with anADC is that the noise figure varies with a range of ADC operating parameters (e.g.,


sample rate, input impedance, and so forth) and is not a constant, as it is with mosttraditional RF/IF signal processing elements.

Noise figure for an ADC is given by [28]:

NFV

ZSNRADC dB

ADC rms

in

ADC,,log l=

⋅

− −

−10

1010

2

3og log

fs

BkTB

210

10 3

−

−

(3.60)

where:

VADC,rms is the rms value of the ADC input voltage range.

fS is the sampling frequency (in hertz).

Zin is the converter input impedance.

SNRADC is the signal-to-noise ratio of the converter.

B is the bandwidth (in hertz).

T is the system temperature (in Kelvin).

k is Boltzmanns constant (1.38 × 10−23 J/K).

Take, for example, a converter with a maximum input voltage of 1-V pk into aninput impedance of 200Ω. If this converter operates with a signal-to-noise ratio of76 dB, at a sample rate of 100 MSPS (at room temperature, 290K), then its noise fig-ure (in a 1-Hz bandwidth) will be 25 dB. A plot of the range of noise figures avail-able from this example converter for different sampling frequencies is provided inFigure 3.44. Although this plot is mathematically correct, it should be borne inmind that, in the case of a real converter, the converter SNR is likely to improve at


10 20 30 40 50 60 70 80 90 100Sampling frequency (MHz)

Noi

sefig

ure

(dB)

25

27

29

31

33

35

37

39

41

43

Figure 3.44 Noise figure (in a 1-Hz bandwidth) of an ADC, for a range of sample rates and anintrinsic SNR of 76 dB.

lower sampling rates. This is not taken into account in Figure 3.44, where a constant76 dB is assumed for the SNR. It can be seen from this plot that lowering the sam-pling rate has a dramatic effect on noise figure; this is likely to be only partly com-pensated by any SNR improvements at these sample rates.

3.4 Influence of Phase Noise on EVM for a Linear Transceiver

Signal vector error (SVE) and its consequent error vector magnitude (EVM) arecommonly used parameters in specifying the degree of corruption a data constella-tion point undergoes, in various parts of a transmitter or receiver architecture. Inthis way various effects may be taken into account, in terms of what is important tothe processes of detection of the wanted data (i.e., the deviation of the data pointfrom its anticipated position). The two primary corruption mechanisms in mosttransmitter and receiver systems are the vector errors present in the quadrature mod-ulator and demodulator and the phase noise present on the local oscillator (LO) ofeach. PA non-linearity can also be an issue, but adjacent-channel and other similarrequirements usually dictate that the PA’s linearity is sufficiently good such that ithas a relatively negligible impact upon EVM. Analysis of the impact of quadraturemodulator errors is relatively straightforward; however, incorporation of theimpact of LO phase noise is usually undertaken only as a part of complex systemsimulation. This section presents a simple, deterministic method of analysing theeffect of both gain/phase errors and LO phase noise on the error vector magnitude ofa transmitter or receiver. Some practical results are also presented, to illustrate theaccuracy of the predictions achieved.

3.4.1 Introduction

Error vector magnitude is now a commonly quoted specification for both transmitterand receiver performance evaluation (e.g., TETRA [31] and UMTS [32]). Typical fig-ures are in the range of 5 to 17.5% for most mobile radio systems (e.g., TETRA [33]and UMTS [32]) and various test instruments now incorporate the measurement ofthis parameter as a standard feature. There are potentially a large number of factorsin the design of the transmitter or receiver which can contribute to the final measuredvalue; however, in practice, in a well-designed system, most are usually negligible.Examples include problems with the receiver detection process (normally performeddigitally), transmitter non-linearities (see earlier comments), synthesiser frequencyerrors (normally tracked out), and errors in modulation generation (normally per-formed digitally with very little resultant error).

There are two sources of SVE that are generally non-negligible in a systemdesign and affect both the transmitter and receiver. The first is the gain and phaseimbalance present in the quadrature modulator in the transmitter [34] and the corre-sponding quadrature demodulator in the receiver [35] (assuming that both are per-formed by some analogue means, for example, as shown in Figure 3.45). Theseerrors result from imperfect matching between the two mixers (or analogue multi-pliers) and an imperfect 90° split in the local oscillator path. Together these result ina distortion of the vector in the I/Q plane, as illustrated in Figure 3.46.


Although these errors may be corrected digitally [36], this would typicallyinvolve a degree of individual testing during production and this is generally unde-sirable. Figures presented in [35] indicate that a phase error of 1° can be achieved asa typical specification for an IC implementation, although currently available com-mercial devices [34] specify 0.2 dB of amplitude error and 3° of phase error.

The effect of quadrature modulator and demodulator errors on the adaptivepredistortion method of RF power amplifier linearisation has been studied in somedetail [37]. This study indicates the detrimental effect of such errors on predistorterperformance and also highlights some methods for overcoming them. An earlierstudy highlights the detrimental effect of quadrature errors on the spectral charac-teristics of a power amplifier [38]; quadrature errors are therefore clearlyundesirable in many areas.

The second major contributor to SVE is phase noise present on the local oscilla-tor. This results in a random rotation of the signal vector around the I/Q plane, witha mean error determined by the synthesiser characteristics and the characteristics ofthe detection and tracking filtering present in the receiver. The detail of this will becovered later in this section. Phase noise is present on all signal sources andalthough it is technologically possible to reduce it to a degree whereby it would have

3.4 Influence of Phase Noise on EVM for a Linear Transceiver 121

I in

Qin

LO In RFout

I/Q modulator

90°

I/Q demodulator

I out

Qout

LO InRF In 90°

(a) (b)

Figure 3.45 Quadrature (a) modulator and (b) demodulator using analogue hardware.

Error vector

Referencesignal(ideal signalvector)

Measuredsignal

Phaseerror

GainerrorQ

I

Figure 3.46 Illustration of signal vector error in the I/Q plane.

a negligible effect on EVM (over and above that generated by the I/Q modulationand demodulation process), this is not usually economic in mobile and handportableradio designs. It must therefore be incorporated into any study on EVM in aparticular design.

The traditional method of studying the effects on EVM of phase noise and mod-ulator/demodulator errors is by means of a block-level simulation of the completetransmitter or receiver system (or both). This is a relatively complex and costly pro-cess and relies on the availability of sophisticated simulation tools of sufficient accu-racy and of operators skilled in the use of these tools and interpretation of thesubsequent results. Care must be taken to ensure that sampling rates are chosenappropriately and that blocks are being used as intended and not beyond theircapabilities.

The effect of phase noise on a received carrier, as a result of mobile propagationeffects, has been studied in detail [37]; however, this analysis is long and complexand does not lend itself easily to adaptation as a design tool for the system designerof a transmitter or receiver.

The purpose of this section is to present a simple, deterministic technique foranalysing the combined effect of phase noise and gain/phase errors on EVM forboth transmitter and receiver systems. The technique could be written into a simula-tion, if desired, or used as a stand-alone tool to allow the required phase-noise andgain/phase balance parameters to be determined at the system design stage. Verifica-tion of the accuracy of the model used is provided by means of practical measure-ments on a π/4-DQPSK system, utilising various gain and phase errors and withdiffering phase-noise characteristics.

3.4.2 SVE Calculation Without Phase Noise Disturbance

With reference to Figure 3.46, the magnitude of the signal error vector may be deter-mined using the cosine rule as:

[ ]E R M RMV e= + −2 2 2 cos( )φ (3.61)

where R is the magnitude of the reference (ideal) vector, M is the magnitude of themeasured (actual) vector, and e is the phase error between them. The measured vec-tor magnitude, M, is composed of the reference vector magnitude, R, plus a compo-nent resulting from the gain error present in the system, Ge:

M R Ge= + (3.62)

If the reference vector magnitude is set to unity, then the resultant error vectormagnitude (in percent), EVM, may be found from:

[ ]E M MVM e= + −100 1 22 cos( )φ (3.63)

The EVM may be plotted as a family of curves over a range of values for the gainand phase errors. Two examples are shown in Figures 3.47 and 3.48, with Figure3.47 representing a general overview for a wide range of errors and Figure 3.48


showing a detailed view of the range of errors generally encountered in most com-mercial quadrature modulator and demodulator subsystems, whether integratedcircuit or hybrid based.

A typical specification, for example, is a gain error of 0.3 dB and a phase errorof 3°; using Figure 3.48 indicates that this results in an error vector magnitude of9%. A given component is unlikely to be at both extremes simultaneously and hencemay well be acceptable (on a statistical basis) with this specification, despite the rel-atively high EVM figure. A more acceptable figure for many systems would bearound 6% and this can be guaranteed with, for example, gain and phase error val-ues of 0.2 dB and 2°, respectively.


0 5 10 15 20 250

10

20

30

40

50

60

Phase error (degrees)

Erro

rve

ctor

mag

nitu

de(%

)

1.0 dB0.5 dB0.2 dB0.1 dB0.05 dB0.02 dB0.01 dB

Figure 3.47 Error vector magnitude for a wide range of gain and phase errors.

0 1 2 3 4 50

2

4

6

8

10

12

14

16

18

20


Erro

rve

ctor

mag

nitu

de(%

)

0.7 dB0.6 dB0.5 dB0.4 dB0.3 dB0.2 dB0.1 dB

Figure 3.48 Error vector magnitude for a range of gain and phase errors typically found incommercial quadrature modulators and demodulators.

As was stated earlier, it is possible to predistort the input signal vectors in orderto compensate for the errors present in an upconverter [40]; however, this usuallyrequires some form of calibration on a per-unit basis and this is generally undesir-able in a production environment, unless absolutely necessary.

3.4.3 Approximation of a Local Oscillator Phase Noise Characteristic

In order to analyse the effect of local oscillator phase noise on EVM, it is necessaryto be able to satisfactorily approximate the SSB phase noise characteristic. Thesecharacteristics may be measured using a phase noise measurement apparatus, pre-dicted from the design equations for a phase-locked loop frequency synthesiser, forexample, or obtained from manufacturer’s data sheets. The method outlined nextallows any of these sources to be used, hence giving the technique wide application.

The basis of the technique is to employ a piecewise linear approximation to thelogarithmic plot of the SSB phase noise characteristic, as this is the form most com-monly used and quoted on data sheets. It may also be predicted with ease from asynthesiser design [41, 42] or from an oscillator design [43]. The form of the charac-teristic is essentially a series of components of the form:

Φαα

= K

f n(3.64)

where is an integer indicating the segment number of the linear segment in ques-tion and n determines the slope of that segment. The complete characteristic istherefore a summation of these segments, so arranged to ensure that they join end toend and form a quasi-continuous characteristic. This may be accomplished using theHeaviside step function as follows (based on four segments):

( ) ( ) ( ) ( )ΦSSB n n n f nf

K

fH f f

K

fH f f H( )

log= − − +

− −

−1 1 2 1 21 2

10δ δ ( )

( ) ( ) ( ) ( )[ ] ( ) ( )

f f

K

fH f f H f f

n n f n n f n

−

+

− − −

− + −

1

3 210 1 2 1 2 3 2 3log log

δ

( ) ( ) ( ) ( ) ( ) ( )[ ]+

−

− + − + −

K

fH f f

n n f n n f n n f n10 1 2 1 2 3 2 3 4 3 44log log log

( ) ( )− −δ H f f 3

(3.65)

where f is the frequency offset from the carrier frequency, K is a scaling constant (toplace the characteristic at the correct dBc value), f1 to f4 are the breakpoints of thesegments (in hertz), n1 to n4 determine the gradients of the segments, and is a smallfrequency offset to ensure that the Heaviside functions do not coincide at the break-points and thereby create a spurious value.

An illustration of the use of this technique is provided by Figure 3.49. Thisshows an SSB phase noise characteristic from an 850-MHz synthesiser with a nar-row loop bandwidth. The measured data points are shown (dotted line) along withthe piecewise approximation (solid line). It can be seen that if the frequency responsepeak occurring at low frequency is ignored, then the piecewise approximation is a


very close fit to the measured characteristic. The values used in (3.65) in this case areshown in Table 3.6.

3.4.4 Incorporation of the LO Phase Noise into the EVM Calculation

The basis of the method is to calculate the root mean square (rms) value of the phasejitter from a carrier corrupted by DSB phase noise, within a given measurementbandwidth, and then to combine this error with that already present due to thephase error from the quadrature upconverter or downconverter. This additionalphase error will then add to the overall EVM for the system. The measurementbandwidth will be determined by an equivalent brick-wall filter, corresponding tothe detector bandwidth for the system and modulation format in question. As an


1 2 3 2 2 3 3 2 3 4 2 3 5 2 3 6-120

-110

-100

-90

-80

-70

-60

-50

-40

Frequency (Hz)

Phas

eno

ise

rela

tive

toca

rrie

r(d

Bc/H

z)

10 10 10 10 10 10

Figure 3.49 Piecewise approximation to a practical 850-MHz, single-loop frequency synthesiser.Dotted line: measured characteristic; solid line: piecewise approximation.

Table 3.6 Parameters Used in (3.65)to Provide a Piecewise Approximationto the 850-MHz Synthesiser

Parameter Valuen1 0

n2 2.4

n3 1.55

n4 0.3

f1 90 Hz

f2 10 kHz

f3 150 kHz

f4 1 MHz

δ 0.001 Hz

K 10−5

example, a TETRA system may be approximated using an 18-kHz bandwidth for aperfect filter.

The method assumes that no AM noise is present on the local oscillator; this is areasonable assumption in a well-designed system. It also takes no account ofsynthesiser spurs, which fall within the measurement bandwidth; these should againbe negligible in a well-designed system.

Consider a perfectly clean carrier with a power level, C, and a superposed singlenoise sideband in a 1-Hz bandwidth at a certain offset frequency from that carrier. Ifthe long-term mean value of the sideband power is No, then it can be shown that thephase modulation index, , is given by [44]:

θ ≈N

Co (3.66)

An LO spectrum will normally consist of two equal sidebands, hence giving:

θ ≈2N

Co (3.67)

Hence the rms phase deviation (jitter) per Hz (of DSB noise), assuming theabove approximation to be true is:

φο =2N

CHzop rads rms per (3.68)

where Nop is the single-sideband phase noise density per hertz of RF bandwidth at agiven offset frequency from the carrier. The mean-square phase jitter at a given off-set frequency from the carrier is therefore given by:

φο2 =

22

N

CHzop rads per (3.69)

To analyse the effect of all of the phase jitter, and hence the completephase-noise corruption of the carrier, it is simply necessary to integrate the aboveover the frequency range of interest:

φ 2 =

∫

20

2N

Cdfopb

f

rads (3.70)

In the case of the SSB phase noise characteristic given by (3.65), this becomes:

φ 2 = ∫ ΦSSB

bf df

0

2( ) rads (3.71)

and hence the equivalent mean phase deviation is:


φ φ2= = ∫ ΦSSB

bf df( )

0rads (3.72)

The use of segmented 1/f-based approximations to the phase noise characteris-tic makes the evaluation of this integral relatively straightforward, as it is simply thesummation of a series of definite integrals, one for each segment, up to the maxi-mum bandwidth of interest. Segments beyond this maximum may be ignored com-pletely, as they will have no effect on the resulting EVM.

3.4.5 Example Results

The results presented here are based on the comparison of measured and predictedperformance for a range of signal source characteristics, four of which are presentedhere. The modulation format used was unfiltered QPSK, which was simulated in amanner which eliminated, as far as was practicable, upconversion gain and phaseerrors. The measurement of EVM was taken from a commercial vector signal ana-lyzer, which provides both graphical output of EVM versus time (symbol) and anumerical value averaged over a number of symbols (user definable and set at 2,048for the tests shown here).

The unfiltered QPSK modulation was simulated by means of a frequency offsetbetween the synthesiser under test and the measurement frequency of the vector sig-nal analyser. This was set to 5 kHz for the tests shown below and this correspondsto a data rate of 20 k-symbols/sec. Since no quadrature upconverter is present in thesystem, the errors recorded can only be due to amplitude and phase noise present onthe synthesiser. The level of amplitude noise was measured on the vector signalanalyser and found to be negligibly small for each of the cases under consideration.

3.4.5.1 Measured Results

The four test signals shown here were chosen to represent a range of EVM values,from almost zero up to approximately 13%. This covers most of the range normallyspecified in the majority of mobile radio systems in existence at present and is there-fore a reasonable range over which to demonstrate the validity of the model. At thetop end of the range, the value of EVM varies significantly between different sam-ples of 2,048 symbols, and exhibited a range of 8.49 at the minimum extreme up to17.42 at the maximum. The results at this end of the measurement range are there-fore less accurate than at the other values.

In all cases, 20 measurements were taken, each of 2,048 symbols and an averagevalue of EVM computed. These results appear in Table 3.8. The results presented inFigures 3.50 to 3.53 represent a snapshot of this process, with only a single sampleof 2,048 symbols being represented in the numbers in the top right-hand corner.

Figure 3.50 shows four results from the first local oscillator test source, result-ing from measurements made on the vector network analyser. The top left-handcorner plot shows the instantaneous EVM value at each symbol point, showing thevariation over a number of symbols. This is then averaged to produce the valueshown in the top right-hand corner (0.2% rms), along with other numerical infor-mation relating to the error vector. The bottom left-hand corner plot shows the



(c) (d)

(a) (b)

Figure 3.50 SVE results using the first LO test signal: (a) error vector magnitude: vertical scale: 0 to20%, horizontal scale: 0 to 2,048 symbols; (b) numerical readout of average and peak error vectorstatistics; (c) QPSK constellation in I/Q plane; (d) and instantaneous phase deviation of constellationpoints: vertical scale: −10º to +10º, horizontal scale: 0 to 2,048 symbols.

(c) (d)

(a) (b)

Figure 3.51 SVE results using the second LO test signal: (a) error vector magnitude: vertical scale: 0to 20%, horizontal scale: 0 to 2,048 symbols; (b) numerical readout of average and peak error vectorstatistics; (c) QPSK constellation in I/Q plane; and (d) Instantaneous phase deviation of constellationpoints: vertical scale: −10° to +10°, horizontal scale: 0 to 2,048 symbols.


(c) (d)

(a) (b)

Figure 3.52 SVE results using the third LO test signal: (a) error vector magnitude: vertical scale: 0 to50%, horizontal scale: 0 to 2,048 symbols; (b) numerical readout of average and peak error vectorstatistics; (c) QPSK constellation in I/Q plane; and (d) Instantaneous phase deviation of constellationpoints: vertical scale: −25° to +25°, horizontal scale: 0 to 2,048 symbols.

(c) (d)

(a) (b)

Figure 3.53 SVE results using the fourth LO test signal: (a) error vector magnitude: vertical scale: 0to 50%, horizontal scale: 0 to 2,048 symbols; (b) numerical readout of average and peak error vectorstatistics; (c) QPSK constellation in I/Q plane; and (d) Instantaneous phase deviation of constellationpoints: vertical scale: −25º to +25º, horizontal scale: 0 to 2,048 symbols.

constellation and transitions between the four points in the QPSK signal. Finally, thebottom right-hand corner plot shows the phase deviation (jitter) present on the indi-vidual symbols, over a number of symbols (and hence time). It is clear from the lowlevel of the response in each of these plots that this first source has a very high spec-tral purity and is, indeed, better than the reference oscillator in the vector signalanalyser (which is itself very good).

Figure 3.51 shows the results from a more typical local oscillator source for amobile radio system. The average EVM in this case (over 20 × 2,048 symbols) is4.80% and the effect of the noise can clearly be seen on each of the traces. The con-stellation diagram shows thicker transitions between points and a blurring of thepoints themselves, while both the phase deviation and EVM traces show distinctivepeaks.

Figure 3.52 shows an LO source toward the middle of what would normallybe considered acceptable in most systems (and would prove unacceptable in some).The clearest distinction may be seen in the constellation diagram, with very poorlydefined points and thick transitions being the obvious hallmarks of a noisy signal.

Finally, Figure 3.53 shows a system operating toward the upper end of whatwould normally be considered acceptable, in most mobile radio specifications.Here, the constellation points are very indistinct and the phase deviation plot, inparticular, demonstrates the presence of a significant degree of corruption of thesignal phase.

3.4.5.2 Comparison with Predicted Performance

As an illustration of the effect of the modelled behaviour of phase noise, in additionto gain and phase errors in an upconverter, consider the example of Figure 3.49; thepredicted results, from this local oscillator, are shown in Figure 3.54. These shouldbe compared to Figure 3.48, in which no phase noise was assumed to be present.

In order to demonstrate the validity of the model, a range of local oscillator sig-nal characteristics are modelled and the corresponding practical results measured asoutlined above. A summary of the model parameters derived for the four LO signalsused is given in Table 3.7. The measured characteristics, together with the relevantpiecewise approximations, are shown in Figures 3.55 to 3.58. It can be seen that themodel closely approximates the measured characteristic in all cases, hence eliminat-ing this as a major source of error in the comparison.

The model was used to predict the EVM in each case and this can be comparedto the average measured performance; the results are presented in Table 3.8. Thepredicted results are based on a lower limit of integration in (3.72) of 10 Hz, sincethe measurement system will track (using an estimation technique) phase deviationrates at or below this value. It can be seen from this that the accuracy of the model isgenerally very good, if a little pessimistic in some cases (~10% overestimate in twocases). Measurement uncertainties at the highest value of EVM will lead to a pooreraccuracy at this extreme. These uncertainties are due to the wide variation in EVMexperienced at these high values of phase noise and the consequent requirement for alarge number of values to be averaged in order to yield a consistent result. It is likelythat in a practical design, which could tolerate these high levels of EVM, other pro-cesses (such as amplifier non-linearity) would be dominant.


The results are based on an assumed perfect upconversion process (zero gainand phase error), since there was no upconverter present (or necessary) in themethod used for simulating the QPSK. If upconverter errors are incorporated, a newversion of Figure 3.48 can be generated, incorporating the EVM contribution(in terms of phase error) for the local oscillator. An example of this is shown inFigure 3.54.

3.4.6 EVM Performance of a Multi-Stage System

The derivation and method outlined earlier deal only with a single-stage system,and also assume that the system is frequency and phase flat (any deviation from thisideal will also add to the output EVM). In the case of a multi-stage network (again


0 1 2 3 4 55

7

9

11

13

15

17

19

21

23

25


Sign

alve

ctor

erro

r(%

)

0.7 dB0.6 dB0.5 dB0.4 dB0.3 dB0.2 dB0.1 dB

0 dB

Figure 3.54 Error vector magnitude for a range of gain and phase errors, incorporating the effect ofa local oscillator with a phase noise characteristic represented by Figure 3.49.

Table 3.7 Parameters Used in (3.65) to Provide a Piecewise Approximationto the Four Local Oscillator Test Signals

Parameter LO 1 LO 2 LO 3 LO 4n1 0.3 0 0.4 0

n2 3.2 1.95 1.85 1.8

n3 2.35 3.1 4 4.15

n4 0 1 1.1 1.2

f1 100 Hz 50 Hz 60 Hz 45 Hz

f2 1 kHz 4 kHz 4 kHz 3.5 kHz

f3 3 kHz 20 kHz 20 kHz 20 kHz

f4 1 MHz 1 MHz 1 MHz 1 MHz

δ 0.001 Hz 0.001 Hz 0.001 Hz 0.001 Hz

K 10−8.1 10−4.8 10−3.8 10−4.0

frequency and phase flat), the EVM values for the individual stages must be added inan rms sense; that is:

EVM EVM EVM EVMtot = + + +12

22 2L n (3.73)


1 2 3 2 2 3 3 2 3 4 2 3 5 2 3 6−140

−80

−90

−100

−110

−120

−130

Frequency (Hz)

Phas

eno

ise

rela

tive

toca

rrie

r(d

Bc/H

z)

10 10 10 10 10 10

Figure 3.55 SSB phase-noise characteristic of a high-quality multi-loop signal generator (first localoscillator test signal). Dotted line: measured characteristic; solid line: piecewise approximation Notethat the specified and modeled characteristics are superimposed (almost perfectly), and hence themodelled characteristic only can be seen.

1 2 3 2 2 3 3 2 3 4 2 3

ModelActual

5 2 3 6

−110

−100

−120

−40

−50

−60

−70

−80

−90

Frequency (Hz)

Phas

eno

ise

rela

tive

toca

rrie

r(d

Bc/H

z)

10 10 10 10 10 10

Figure 3.56 SSB Phase noise characteristic of the second local oscillator test signal. Dotted line:measured characteristic; solid line: piecewise approximation.

where EVMtot is the total EVM at the output of the system, and EVM1 to EVMn arethe EVM values for the various stages in the system (e.g., local oscillators, if they arethe dominant sources of EVM at each stage).

This method must also be used (in a modified form) in order to assess theamount of EVM added by a network or system (i.e., to remove the effects of thesource EVM). In this case, (3.73) becomes:


1 2 3 2 2 3 3 2 3 4 2 3 5 2 3 6

ModelActual

−110

−100

−120

−40

−50

−60

−70

−80

−90

Frequency (Hz)

Phas

eno

ise

rela

tive

toca

rrie

r(d

Bc/H

z)

10 10 10 10 10 10

Figure 3.57 SSB Phase noise characteristic of the third local oscillator test signal. Dotted line:measured characteristic; solid line: piecewise approximation.

1 2 3 2 2 3 3 2 3 4 2 3 5 2 3 6

ModelActual

−120

−60

−50

−40

−70

−80

−90

−100

−110

Frequency (Hz)

Phas

eno

ise

rela

tive

toca

rrie

r(d

Bc/H

z)

10 10 10 10 10 10

Figure 3.58 SSB Phase noise characteristic of the fourth local oscillator test signal. Dotted line:measured characteristic; solid line: piecewise approximation.

EVM EVM EVMDUT Meas Source= −2 2 (3.74)

where EVMMeas is the measured EVM (displayed on the test instrument), EVMSource isthe EVM measured from the source alone and EVMDUT is the EVM resulting from thedevice under test.

3.5 Relationship Between EVM, PCDE, and

Peak code domain error (PCDE) [45] is used as a specification, similar to EVM, forWCDMA systems. The advantage of a peak code domain error requirement, overrelying solely on EVM, is to ensure that modulation errors are spread evenly overthe codes. This prevents errors from disproportionately impacting a few codes, forwhich performance would be degraded. This phenomenon cannot be detected usingan error vector magnitude test, as this is measured before despreading. PCDE isspecified in the WCDMA specifications published by the Third Generation Partner-ship Project (3GPP).

If the error is evenly distributed across the codes, the PCDE is given by:

PCDEEVM=

10

2

2log

S(3.75)

where EVM is the error vector magnitude and S is the spreading factor. For exam-ple, if EVM is 12.5%, with a spreading factor of 256, the resulting peak codedomain error is −42.14dB. Since the error is assumed to be evenly distributed, this iseffectively the mean code domain error and not strictly PCDE.

Rho (ρ) is the ratio of correlated power to total transmitted power for a CDMAsignal (i.e., the degree of correlation between a perfect reference signal and theactual signal generated by the transmitter). It is specified in the IS-95 andCDMA2000 standards. This correlated power is derived following the removal offrequency, phase, and time offsets and subsequently performing a cross-correlationbetween the corrected, measured signal and the ideal reference. Any of the transmit-ted energy that does not correlate appears as added noise, and this may interferewith other users of the system. Rho (ρ) can therefore be written as:


Table 3.8 Comparison Between Measured and PredictedEVM Performance

LO TestSignal Source

Measured EVMPerformance (%)

Predicted EVMPerformance (%)

LO 1 0.2 0.1

LO 2 4.80 5.47

LO 3 9.10 9.17

LO 4 12.22 13.42

ρ =

=+

P

P

P

P P

C

T

T

T E

(3.76)

where PC is the power which correlates with the ideal reference signal, PT is the totaltransmitted power, and PE is the error power. For IS-97 ([46], superseded by [47]),the value of for the transmitter must be less than 0.912, indicating that up to8.88% of the transmitted power can be wasted and appear as a potential interfererto the other channels within the system.

There are a number of relationships between ρ, EVM, (mean) code domainpower ( i), spreading factor, and (mean) code domain error:

ρ = − − ≈ −11

12 2SS

( ) ( )EVM EVM (3.77)

ρρ

i S S= −

−

≈

10

11

102

log logEVM

(3.78)

CDEEVM=

≈ −

10 1012

log logS S

ρ(3.79)

Note that EVM is expressed, here, as a pure ratio, not a percentage (i.e., anEVM of 10% would be entered as 0.1 in the above equations). Note that (3.79) issimilar to (3.75), dealing with the mean code domain error and not its peak value.

In the 3GPP standard, peak-code-domain-error, PCDE, is the specified parame-ter. As a rule of thumb, the PCDE is 5–7 dB above the mean code-domain-error.There is unfortunately no corresponding rule of thumb in 3GPP2, since it does nothave a well-defined test model; hence, the result is dependent upon the codeselected. Note also that in 3GPP2, ρ is only defined for the pilot and not for a fully(or even partially) loaded system. It is typically measured with all of the other codesturned off, with the pilot therefore taking only 20% of the total system power (i.e.,7 dB of backoff). Furthermore, the peak-to-mean ratio of the pilot is only 6 dB, notthe 9.5 dB of the system in normal operation, making the ρ specification relativelyeasy to meet in most cases.

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3.5 Relationship Between EVM, PCDE, and ρ 137

C H A P T E R 4

Multi-Band and General CoverageSystems

4.1 Introduction

Current radio receiver designs are, in general, inherently narrowband and can onlyachieve general (or broadband) coverage by the switching or alteration ofnarrowband elements. Certain designs, such as those used in many scanning receiv-ers, do not attempt to overcome some of the fundamental receiver problems, such asblocking and image rejection, but rely on the user being able to eliminate interfer-ence by positioning of the set, or some other mechanism such as the use of a direc-tional antenna. Where this is not possible, the user must tolerate the problem andthe restriction in frequency usage whichensues, as the price of achieving widebandcoverage.

The aim of the ideas presented in this section is to propose systems and tech-niques for the elimination of many or all of the fundamental problems which pre-vent the truly universal radio receiver from becoming a reality. The ideas presentedare not fully developed solutions, currently in production, but more a series of pro-posals as to how some of these fundamental issues might be addressed.

There are three basic problems which need to be solved:

1. The diplexer filter required in a full-duplex transceiver must be specificallyand carefully designed for its intended band of operation. This filter isusually either a helical component or formed from a dielectric (such asceramic) and hence is almost impossible to tune in any sensible fashion overa reasonable range of frequencies. A multiple-band transceiver wouldtherefore require a number of diplexer filters and this would very quicklybecome prohibitive, both in terms of cost and size.

2. The front-end preselect filter (also known as the band-select or cover filter),utilised to reject the image signal and other particularly strong out-of-bandsignals, must also be either tunable or eliminated in order to allowmulti-band coverage. Electronic tuning of this filter is a more realisticproposition than that of the diplexer filter mentioned earlier; however, thechange in technologies (from, perhaps, lumped-element to dielectric-based)across, say, 100 MHz to 2 GHz, would make this difficult, if not impossible.The alternative to the use of such a filter would require the front-endamplifier [or low-noise amplifier (LNA)] to be able to handle the fulldynamic range of signals within the broad coverage range. This may includeTV transmissions of many kilowatts and microcellular transmissions of a

139

few milliwatts, and hence a very high dynamic range amplifier is required.Such an amplifier could be created by backing off a high-power linearamplifier (of, say, 10W), but this is unrealistic in a hand portable radio. It istherefore necessary to utilize a more conventional low-noise amplifier andeliminate its distortion when dealing with high input signal strengths.

3. A further consequence of eliminating the front-end filter is that the imagesignal is no longer suppressed and hence has the potential to interfere directlywith the wanted signal in the receiver. This image signal must therefore besuppressed by some other mechanism which does not involve filtering at theinput signal frequency.

4.2 Multi-Band Flexible Receiver Design

As was hinted earlier, the addition of wide channel bandwidths and, in particular,multiple operating bands significantly increases the difficulty of producing a flexi-ble receiver design. The widening of the channel bandwidth has the followingconsequences:

• The number of narrowband carriers which can enter the IF and basebandchains is significantly increased, thus increasing the potential dynamic rangerequired in these parts of the system. In going from an IF of, say, 200 kHz (forGSM) to 4 or 5 MHz (for UMTS in Europe), the number of 25 kHz channels(e.g., for TETRA) that could enter the IF increases from 8 to 200.

• The sampling rate and dynamic range required of the A/D converter also bothincrease significantly. This may well make the A/D an unrealisable part usingcurrent technology (or indeed, following medium-term advances in currenttechnology).

In going from a single-band to multiple bands, the receiver faces a number offurther problems:

• RF preselection filtering becomes difficult or impossible, since the filter mustnow be tuned to each band of interest. Alternatively, a bank of switched filtersmay be employed, but this can quickly become unwieldy for a truly flexiblesystem. This latter technique has been used in a number of military systems inthe past.

• The channel synthesiser must tune over a far wider range than for a sin-gle-band system.

• The diplexer in a full-duplex transceiver must have a variable frequency ofoperation and a variable transmit/receive frequency split. Since the diplexeris currently realised in ceramic, SAW, or helical resonators in most portablesystems, this is clearly impossible with current techniques. Again, the mainobvious alternative is the use of multiple units, with switching to determinewhich is in use at a given point in time. As before, this can quickly becomeunwieldy.

140 Multi-Band and General Coverage Systems

It is worth examining the consequences of eliminating the inflexible compo-nents mentioned above on the overall receiver performance, since the only option isto design without these components and utilise alternative means of solving theresulting problems (if possible).

If the front-end preselect and diplexer filters are removed, then three main prob-lems result:

1. All image rejection from this filter is lost, thus leaving the receiver prone tosignals appearing at its image frequency.

2. All radio signals within the bandwidth capability of the antenna willimpinge upon the front-end low-noise amplifier in the receiver. Thisamplifier will therefore require a very high dynamic range to preventoverload from strong, unwanted signals (e.g., broadcast TV transmissions ina handportable communications receiver).

3. Without a diplexer, the full power of the transmitter output signals mayimpinge upon the receiver input (depending upon what is used to replace thediplexer). The receiver must therefore be able to cope with these signals, orelse utilise an alternative method of eliminating them.

One possible approach to solving these problems is shown in Figure 4.1. At firstglance, the only major difference between this figure and Figure 3.1 is that thefront-end filter has been removed. The consequences of this act have, however, beenincorporated in the labelling of the various system components. The front-endamplifier is now required to have a high dynamic range and this will have implica-tions for either its power consumption (if conventional techniques are used) or com-plexity (if a linearisation technique is used) or possibly both.

The mixer must now incorporate the image-rejection capability originally pro-vided by the front-end filter; hence, some form of image-reject mixer will be neces-sary. It too will experience the full dynamic range of the input signals and hencemust be able to cope with this without introducing undue levels of distortion andhence possibly blocking weak, wanted signals.

The other significant difference is the introduction of variable-bandwidthanti-alias filters prior to the A/D converters. These can then effectively perform thechannel-selection filtering in the receiver and hence significantly reduce the dynamicrange required of the A/D converters. The only remaining dynamic range

4.2 Multi-Band Flexible Receiver Design 141

High-dynamicrange RF Amp

High-dynamicrange, controlledIR mixer

Channelsynth.

IF filter

LinearIF amp

Broadband I/Qdemodulator

Iout

Qout

LO InIF In90°

VariableLP filter

VariableLP filter

Fixedsynth.


I in

Q inAGC Baseband

voice/dataoutput

Figure 4.1 Possible universal receiver architecture.

requirement would then be that necessary to cope with fast-fading of the wantedchannel, slow fading having been eliminated by the AGC on the IF amplifier (assum-ing that it has sufficient dynamic range to cope). This filtering may be implementedusing switched-capacitor techniques, for example, with the clock frequency (andhence filter bandwidth) being under software control.

Note that the use of anti-alias filtering as a channel filter is only possible in a sin-gle-channel application (e.g., a portable receiver). An architecture more akin to thatof the right-hand side of Figure 3.5 would be required in a multi-carrier base-stationapplication.

It is clear from this discussion that a number of these components have yet to berealised, although research is currently underway to solve these problems, as theyare potentially key to the practical realisation of a multi-band flexible architectureradio.

4.3 The Problem of the Diplexer

The diplexer filter in a mobile radio transceiver has, for many years, been the solemethod of achieving the necessary removal of the transmitter output signal from thereceiver input, in a full-duplex radio. This component is normally essential in orderto realise the benefits of a standard telephone conversation in an FDD system (i.e., tobe able to speak and listen simultaneously). In addition, it has been a feature ofmany TDD and TDMA systems, due to the requirement for the transmit and receiveframes to overlap, when a long turnaround time for the transmit/receive signals ispresent (e.g., when the user is close to the edge of a cell).

The use of a diplexer (or duplexer1) filter has a number of significant disadvan-tages that must either be tolerated or circumscribed in order to enjoy its benefits.These may be summarised as follows:

• Size: Their physical construction is such that they are often bulky, and even inhandportables they can consume a relatively significant amount of space.

• Construction: Their function, and hence their required form of construction,means that it is unlikely that they will be successfully integrated along with thesilicon components within a transceiver (in the short or medium term). Theyare therefore a barrier to achieving a single-chip, full-duplex radio.

• Frequency spacing: The operation of current diplexer filters dictates that a sig-nificant frequency spacing between transmit and receive bands is required.This split is, for example, 90 MHz for 1,800-MHz cellular equipment and anyattempt to reduce it would result in a significant increase in size for thediplexer.

• Spectrum inefficiency: The use of a diplexer requires a frequency split betweentransmit and receive bands. The proposed technique to eliminate the diplexershould mean that this split could be eliminated, thus allowing both transmis-sion paths to operate on the same frequency (known as on-frequency duplex).This in turn could lead to a doubling of the number of channels available in a


1. The names diplexer and duplexer are used interchangeably and refer to the same component.

given bandwidth. Note that the required performance from the techniqueincreases markedly when attempting to achieve on-frequency duplex, as theperformance requirement changes from one of eliminating overload in thereceiver path to one of suppressing the transmit signal to a level below theminimum required receive sensitivity, by more than the cochannel protectionratio of the modulation format in question. This is an extremely toughrequirement in most systems.

One example of a problem in the transmit-receive frequency split occurs in the220-MHz SMR band in the United States. The issue is that of a small split betweentransmit and receive bands within the 220-MHz allocation; a given pair of transmitand receive channels is only separated by 1 MHz and this is a very small percentageof the frequency of operation.

As a comparison, take the 1,800-MHz DCS band: Here the split is 90 MHz,which is around 5% of the operating frequency. At 220 MHz, the split is only0.45% of the operating frequency. It is this small percentage, which dictates thespecification required of the diplexer filters in order to allow full duplex operation.Creating a filter with a suitably high rejection over such a narrow frequency band,at VHF, would result in a very large and expensive item (prohibitively so), if indeedit is realisable at all. Such filters would be nonsense in a handportable and prohibi-tively expensive and unacceptably large in a mobile.

A radically new approach to this problem is therefore required. If it is assumedthat a 2.5-W output power (+34 dBm) is required from the mobile and that thereceiver is well designed and hence has a dynamic range of 80 dB, then the maxi-mum level of transmit signal permitted in the receiver front end is −40 dBm (for anoverall receiver sensitivity of −120 dBm). The rejection required therefore is+34−(−40) dB = 74 dB.

This level of rejection must mainly be provided by some form of cancellationwithout sapping significant additional power from the supply or adding unreason-able levels of complexity.

The preceding discussion concentrates on conventional diplexer issues; thereare, however, a number of issues which arise when considering a flexible architec-ture radio. In particular, the requirement for flexibility, in a multi-mode radio capa-ble of operating with a number of radio systems (even in the same area of spectrum),introduces new duplexer issues which must be addressed. The problems occur sincethe different systems may use different multiple access schemes [e.g., fre-quency-division duplex (FDD), time-division duplex (TDD), time-division multipleaccess (TDMA), or code-division multiple access (CDMA)] and may have differenttransmit/receive frequency splits (or none at all in the case of TDD systems).

The required transmit/receive isolation for continuous-time, full duplex trans-mission (i.e., not TDD and not TDMA with non-simultaneous transmit/receivetimeslots) is based on the transmit power level and required receive sensitivity,along with the receive A/D dynamic range and the selectivity of the receiver (digital)filtering.

Consider the example of a handset full-duplex transceiver, with a 1-W(+30-dBm) maximum output power capability and a minimum receive sensitivity of−110 dBm (for a given modulation bandwidth). If it is assumed that a 10-dB C/I

4.3 The Problem of the Diplexer 143

ratio is the minimum for adequate demodulation of the chosen modulation scheme,then the minimum isolation which must be provided by the duplexer, for on-fre-quency duplex, is:

( )( )

Z P P DI OFD Tx C I, min= = −

= + − − −

=

30 110 10

150 dB

(4.1)

This is an extremely stringent requirement and would prove almost impossibleto meet by any known and economic technique.

If however, a duplex frequency split is now introduced, the situation becomesmore realistic. Consider the earlier example, but now with a duplex frequency-splitintroduced, such that the receive IF digital filtering can reduce the unwanted residualtransmitter signal appearing in the front-end received signal, to a negligible level.This makes no assumption about any analogue IF filtering, which may well ease theburden on, for example, ADC dynamic range, as the general case of a fully flexiblereceiver architecture is assumed here. There are now two isolation considerationswhich must both be met, however each is potentially much less stringent than thatconsidered earlier.

The first consideration is overload of the receiver and hence its front-end andreceiver strong signal handling capability. This breaks down into the analogue part(LNA, mixers, and so forth) and its IMD performance and the A/D converter and itsdynamic range. In this case (split-frequency duplex), the required isolation may bederived as follows. In the limiting case, the IMD power generated by the receivernon-linearity (or clipping) must not exceed the specified minimum sensitivity plusthe required C/I for the modulation format in question. In practice a margin of atleast 3 dB would be desirable; however, the simplified analysis below assumes nomargin, hence:

P P DIMD C I= −min (4.2)

The IMD power resulting from the front-end non-linearity, based upon the sim-ple assumption of a two-tone test and a purely third-order non-lineareity, is givenby:

( )P P PIMD Tone IP= −2 3 (4.3)

The tone power in this case is provided by the unwanted leakage of the transmitsignal into the receive signal path, hence:

P P ZTone Tx I SFD= − , 1 (4.4)

Combining (4.2) through (4.4) gives:

Z PP D

PI SFD TxC I

IP,min

1 32= =

−− (4.5)


where PTx is the transmitter output power, Pmin is the minimum specified receive sig-nal power, DC/I is the minimum required carrier-to-interference ratio for the modu-lation format in question, and PIP3 is the third-order intercept point of the receiverfront-end analogue components. If this example is used and a receiver input inter-cept point of +30 dBm is assumed (a reasonable upper limit for a linearised receiverfront-end in a handset), the required isolation reduces to 60 dB. This is still a veryhigh value, but may not be completely beyond the bounds of possibility for a futureisolation technology.

Note that (4.5) assumes that an adequate A/D converter dynamic range is avail-able, where this dynamic range is given by the difference between the unwanted(residual) transmitter output signal impinging upon the receiver and the maximumpermitted interferer level [given by (4.2)]. Strictly speaking, this is the required spu-rious-free dynamic range (SFDR) rather than the signal-to-noise ratio (although thismay also be important, depending upon the degree of averaging and/or filteringwhich can be employed in the digital domain, to extract the wanted signal). It isgiven by:

( ) ( )D P Z P DA D Tx I SFD C I= − − −

=, min1

90 dB(4.6)

This is again high, but not out of the question, particularly in a narrowband sys-tem. As ADC technology improves in the future, it will become increasingly realis-tic, even in broadband (and hence high sample-rate) systems.

The second requirement is that the transmitter noise floor must not mask thereceived signal. This results in the following isolation requirement:

( )Z N P DI SFD Tx C I, min2 = − − (4.7)

where NTx is the transmitter output noise power (in the receiver bandwidth). A typi-cal figure for this noise power is around −75 dBm, based upon the minimumreceived power levels used above (and hence channel bandwidths). With this figure,the required isolation is 45 dB, making the first consideration (on receiver linearity)dominant in this case.

There are a number of partial or complete solutions to the isolation problem:

1. Tx/Rx switch. It is possible to implement a purely switch-based duplexfacility, and this has many advantages. First, it can be made very broad-band (multi-octave, if necessary) since filtering is not necessary. Second, itplaces no restrictions on the system duplex frequency split, since nofrequency-selective components need be involved. Finally, it will allowon-frequency duplex (i.e., TDD) for the same reason.

It may be implemented using simple PIN-diode switch technology and istherefore low cost, although transmit-receive isolation is an issue and it maybe necessary to disable the transmitter while in receive mode to ensure thatthe transmitter noise floor does not de-sense the receiver.

2. Switched diplexer. Recent advances in integrated diplexer techniques haveled to the possibility of implementing a switched diplexer, in which


the transmit and receive paths can be switched between two (or more) paths.This type of system is discussed in more detail in Section 4.3.2. It hasa number of disadvantages, including band-limiting (i.e., it is notcommensurate with an ideal general-coverage SDR), relatively high loss(typically) due to losses in the switches, and limited power handling (again,due to switch-related issues, such as saturation and IMD).

3. Circulator. A second solution is to use a circulator, as shown in Figure 4.2.The main drawbacks of this approach lie in the frequency range limitationsof most high-isolation parts and the achievable isolation from low-cost,small-sized components, suitable for handset applications. Typical isolationvalues for these parts, even band-specific items, are in the range of 10 to25 dB. This is adequate for their current, primary application in protectionof the transmitter from the wide range of antenna VSWR conditions.However, even the higher value is not adequate for the duplex functionunder consideration here and it is difficult to envisage that an improveddesign could achieve the required figures without additional help fromfiltering or some other method of isolation enhancement.

4. Duplexer elimination schemes. This heading covers some new methods ofachieving transmit/receive isolation. It is possible, for example, to usecancellation-based techniques in order to remove the transmit signal fromthe receive signal path, although these techniques themselves have a numberof disadvantages. They are complex and have difficulties coping withexternal reflections. They also generally require complex antennaarrangements, which are not currently compatible with small handsetdesigns. Research is, however, being performed in this area and a solutionmay be developed in the future. Further details of the basic concept areprovided in Section 4.3.3.

4.3.1 RF Transmit/Receive Switch

Although it is possible to use coaxial relays for transmit/receive switching, virtuallyall low and medium power systems now utilise PIN diodes or FETs for this purpose.


Linear RF Poweramplifier

From Tx basebandcircuitry andupconversion

ReceiveLNA

To downconversionand receiverbaseband circuitry

Circulator

Figure 4.2 Use of a circulator to provide transmit/receive isolation.

The basic configuration of the switch simply connects the common terminal to theantenna, with the two changeover contacts being connected to the transmitter out-put and receiver input respectively. This is shown in Figure 4.3. Clearly the fourmain performance criteria for the switch are:

1. Isolation. A high degree of isolation is required to prevent the transmitsignals from overloading the receiver front end. The amount of isolationrequired is similar to that calculated above. This is by no means a trivialrequirement, even for a switch, and it is usually achieved in conjunction withdisabling the transmitter during the receive portions of the communicationinterchange. Typical switch isolation values range from 20 dB to 60 dB,depending upon the frequency of operation, the performance of the diode(s)used, and the complexity of the switch.

2. Linearity. This is particularly important for the transmit path, as a poorlinearity performance could significantly degrade the demanding linearityspecifications, which are often required from modern (linearised)transmitters. Linearity performance is usually related to the carrier lifetime ofthe diode itself, together with the resistance or attenuation being demandedfrom it. A long carrier lifetime generally results in low distortion, with a shortcarrier lifetime only resulting in low distortion at extremes of bias (either onor off). In the case of a PIN switch, where the diode bias is either at a highvalue or zero (or possibly a small reverse-bias), carrier lifetime becomes lessof an issue and shorter lifetime diodes can usually be applied.

3. Power-handling capability. The power-handling capability of the switch isusually set by either the PIN diode’s breakdown voltage or its powerdissipation capability, with the latter usually being the limiting factor. Forexample, consider a PIN diode used in series mode, with an on-resistance of1Ω, operating in a 50Ω system. If the maximum dissipation of the diode is2W, then the maximum power handling of the switch will be approximately100W.

4. Loss. While loss is an issue in power handling and device dissipation, asoutlined above, it can also be a contributor to receiver noise figure. A lowthrough-loss is therefore desirable for the receive path, as well as for thetransmit path.


Linear RF Poweramplifier


ReceiveLNA


PIN-diodeswitch

Figure 4.3 Use of a SPDT PIN-diode switch for transmit/receive changeover.

The simplest configuration commonly used for PIN-diode based trans-mit/receive switching is shown in Figure 4.4. In this circuit, L1 is an RF choke,C1–C3 are DC blocking capacitors and D1, D2 are the PIN diodes. The 50Ω, quar-ter-wave line can be constructed from any suitable transmission-line medium (e.g.,coaxial cable or microstrip line).

This configuration offers a number of advantages over the alternative of utilis-ing purely series diodes:

1. It requires only a single bias control line, thereby simplifying the controlcircuitry.

2. Bias is only required while in transmit mode, resulting in a low-power receivemode.

3. Both diodes are biased when the transceiver is in transmit mode. This is anadvantage, since PIN diodes usually generate most (harmonic) distortionwhen in their off state, due to modulation of the diode’s capacitance, orself-bias resulting from rectification of the transmitted signal. Since they arein their on state while the system is in transmit mode, this situation isavoided.

Operation of the switch is straightforward. In transmit mode, a bias current isapplied and both diodes appear in series (at DC) and hence turn on (low resistance).In this mode, the transmitter output is connected to the antenna and the receiverinput is shorted to ground. The short appearing at the receiver input is transformedby the quarter-wave transmission-line to an open circuit at the antenna port. Thisprovides a high impedance to the transmission of signals from the transmitter out-put (which have arrived at the antenna port), preventing them from entering thereceiver.

In receive mode, the bias current is removed and both diodes turn off (high-resis-tance). This disconnects the transmitter from the antenna port and removes theshort circuit at the input to the receiver. This, in turn, allows the normal


Linear RF poweramplifier


ReceiveLNA


50Ω

IBias

λ/4

D1

D2

C1

C3

C2

L1

Figure 4.4 Simple series-shunt transmit/receive switch using PIN diodes.

transmission of signals arriving at the antenna port, through the quarter-wave line,and into the receiver input. Note that the bias circuitry should possess a high imped-ance to RF signals (at the desired operating frequency) in both transmit and receivemodes. This will prevent the generation of intermodulation and harmonic distor-tion and also prevent unwanted loading of the transmitter output, when in transmitmode. Note also that for lower frequency operation, it is possible to replace thequarter-wave line by a lumped-element equivalent. This will usually be smaller andhave a lower, loss resulting in a better receiver noise figure. A simple, three-elementlumped-element quarter-wave line is shown in Figure 4.5. Its component values canbe found from:

C CfZin out= = 1

2 0π(4.8)

and

LZ

fS = 0

2π(4.9)

When carefully constructed, this type of switch is capable of more than 30 dB oftransmit/receive isolation at frequencies up to 2 GHz. Transmit and receive throughlosses (when in transmit and receive modes, respectively) are typically in the regionof 0.4 to 0.6 dB.

An alternative configuration is shown in Figure 4.6, effectively doubling-up thearrangement shown in Figure 4.4. In this case, two series diodes are used in thetransmit path, thereby increasing isolation in receive mode, due to the halving of theeffective reverse-bias capacitance of either diode (assuming that both are identical).Similarly, in the receive path, two diodes and two quarter-wave transmission-linesare employed, and these provide enhanced isolation in this part of the circuit (theo-retically, it should more than double). The drawback of this arrangement is, how-ever, an increase in both the transmitter and receiver path losses. This results in anincreased transmitter output power requirement (for equivalent power at theantenna) and results in an increased receiver noise figure.

Note that the configuration shown in Figure 4.6 requires a negative bias currentfor transmit mode and a zero (or positive) bias current for receive mode. This can bealtered to a positive bias requirement (as used in Figure 4.4) by reversing the direc-tion of all diodes.

A final option is shown in Figure 4.7. Again four diodes are used, in this case asseparate series-shunt switches for both the transmitter output and the receiver


Cin

LS

Cout

Input Output

Figure 4.5 Lumped-element equivalent of a quarter-wave line for use in transmit/receive switches.

input. This configuration has the disadvantage of requiring two bias control lines,but can provide good isolation without the need for a ¼-wave transmission line (orlumped-element equivalent).




ReceiveLNA


50Ω

IBias( )−ve

λ/4

D1

D4

C1

C3

C2

L1

D2

50Ω

λ/4

D3

Figure 4.6 Improved-isolation series-shunt transmit/receive switch.



ReceiveLNA


IBias1

D1

D4

C1

C3

C2

L1

D2

D3 L2

IBias2

L2

Figure 4.7 A high-isolation SPDT transmit/receive switch.

4.3.2 Switched Diplexers

These have been discussed briefly above and involve the fabrication of a number ofdiplex filter elements for the transmit and receive paths. A two-way or multi-waychange-over switch is then employed, to select the required filter pair for a giventransmit and receive band allocation. One example of this type of system is shownin Figure 4.8 and is described in the literature [2]. It utilises GaAs PHEMT switches,as these were reported to have a number of advantages over PIN diodes at therequired frequencies of operation. These advantages included: low current/low volt-age and single supply operation together with having no requirement to resonateout parasitics. The switches provided more than 20dB of isolation (excluding filterisolation), together with an insertion loss of less than 1dB for the overall diplexercircuit.


To/fromantenna

Lowpassfilter

Highpassfilter

Lowpassfilters

GaAs FETswitch

GaAs FETswitch

900 MHzRx

900 MHzTx

1800 MHzTx

1800 MHzRx

GSM

DCS

Diplexer

GSM input/output (50 )Ω

C2

(a)

(b)

L1

C3

C4

L2C5

C6

L3

C7

Antennaconnection(50 )Ω

DCS input/output (50 )Ω

C1

Figure 4.8 Switched antenna diplexer: (a) block diagram of the diplexer module; (b) diplexercircuit schematic. (From: [1] © 2005 IEEE. Reprinted with permission.)

There are a number of disadvantages of this arrangement. First, the GaAsswitches will have some non-linearity and this will impact upon the adjacent chan-nel performance of the transmitter(s) used in the system, for non-constant envelopemodulation formats (the design reported in [1] was primarily intended forGSM/DCS and linearity performance was not discussed). Second, the technique willonly work in a number of discrete bands, and these must typically be quite widelyspaced from each other. It is not, therefore, possible to use this approach for a gen-eral coverage system, offering full flexibility.

An alternative fabrication technology to that described earlier involves the useof SAW resonators to form the filter elements and PIN diodes to switch the requiredelements in and out of circuit. Such a system is also described in the literature [2]and, in this case, is employed to operate in two pairs of Tx/Rx bands, which are closeto each other (both are within the 800-/900-MHz area of the spectrum). Thediplexer was designed to operate in a handset application for the Japanese cdmaOnesystem, which has receive band allocations from 832 to 846 MHz and 860 to 870MHz and transmit band allocations from 887 to 901 MHz and 915 to 925 MHz.There is therefore a 14-MHz gap between the two different pairs of transmit andreceive frequency allocations and a 55-MHz duplex split.

The duplexer was reported to have a transmit path loss of less than 2 dB and areceive path loss of less than 3.3 dB. It had over 50 dB of image attenuation and atransmit-receive isolation of 35 dB, from the transmit filter characteristic, and 52dB, from the receive filter characteristic. It also had acceptable distortion character-istics from the PIN diodes. The main disadvantage of the technique is in its increasedlosses over those described earlier, although the comparison cannot be madedirectly.

4.3.3 Diplexer Elimination by Cancellation

A more radical idea for the elimination of the diplexer in a full-duplex softwaredefined radio system is in the controlled cancellation of the unwanted transmitteroutput signal as it appears in the receive signal path. The form of the solution to thisproblem involves the removal of the transmitter output signal from the receiverinput by anti-phase cancellation in a precisely controlled manner. A general blockdiagram illustration of this approach is shown in Figure 4.9.

The signal from the receive antenna (which may be coincident with, or part of,the transmit antenna) will contain a significant degree of unwanted coupling of thetransmitter output signal. This coupling (or its effects) must be removed in order toprevent overloading of the front-end components within the receiver section. Thiscan be achieved by taking a sample of the transmitter output signal utilising a cou-pler and, after suitable processing, subtracting this signal from the receiver input sig-nal, using a subtracter (which could also be a coupler). Since the receiver input signalwill contain both the wanted signal and the unwanted coupling, this subtractionprocess will remove the unwanted coupling to a high degree (assuming a negligibleamount of multipath coupling between the antennas).

The control circuitry uses samples of the receive signal after cancellation andtypically the transmit signal, in order to ensure intelligent and rapid operation of thecontrol elements (e.g., a variable attenuator and phase-shifter, as shown in Figure


4.9, or a vector modulator); the goal is both to obtain and maintain optimum can-cellation. The control process can take place in real time or utilise a periodicupdating mechanism.

4.3.3.1 Implementation Options

There are many potential methods of realising this system and only a restrictednumber may be included here. In the case of a linear radio2 incorporating a quadra-ture input transmitter (e.g., a Cartesian loop), one possible configuration is shownin Figure 4.10.

The received signal will contain a significant quantity of the energy from thetransmitted signal due to the coupling between the two antennas. These antennasmay be separate structures, a composite item, or, in the extreme, a single antennawith a circulator, isolator, attenuator, or coupler (or similar device) used to performthe transmit and receive path separation.

A sample of the transmit signal from the quadrature input transmitter is pro-cessed by a phase-shifter and a variable attenuator, before being fed to one input ofa subtracter. The received signal forms the other input to the subtracter and theresult of the subtraction process is fed to the receiver front end. If the variable phase




ReceiveLNA


Transmitantenna

Receiveantenna

ΦController

Voltage-variableattenuator

Voltage-variablephase-shift

Unwantedcoupling

Subtracter

Figure 4.9 Removal of the transmit signal from the receive path by anti-phase cancellation.

2. A linear radio refers to one in which the baseband signal information is transmitted by one or other or bothof amplitude and phase modulation of a carrier. Such radios may be used for the transmission of SSB, AM,FM, 16-QAM, GMSK, QPSK, CDMA, and almost any other recognized form of modulation.

and attenuator elements are correctly adjusted, the signal appearing at the input tothe receiver front end will contain predominantly the wanted receive signal; theunwanted transmitter output signal will have been substantially eliminated. Theremainder of the receiver processing (mixing, amplification, and detection) can thenoperate as in any other standard receiver configuration.

A key element of the system is the control of the variable phase and attenuation(or gain) elements in order to achieve and maintain optimum cancellation of theunwanted transmitter output signal from the receive signal path. For this purpose acontrol circuit utilising, for example, a digital signal processor (DSP) is configuredto provide the required parameter optimisation for both of the control elements,based on the measurement of an error signal, relative to a reference signal, derivedfrom the transmitter.

In the case of Figure 4.10, the reference signal is formed from the baseband (oraudio) inputs to the transmitter. In this case they are supplied in analogue form,although they could, advantageously, be supplied digitally, where the transmitterinput is supplied in that manner. These form one set of inputs to the controller. Theother set of inputs is formed from a coherent quadrature downconversion of a sam-ple of the received signal, after processing by the front-end components. The


Linear RFpoweramplifier

I/Qbasebandinputs

ReceiveLNA


Transmitantenna

Receiveantenna

ΦController

Voltage-variableattenuator

Voltage-variablephase-shift

Unwantedcoupling

SubtracterFront-endfilter

90º

0ºIn

90º

0ºIn

Localoscillator

Figure 4.10 One potential configuration of the diplexer elimination technique when applied to aquadrature-input transmitter.

oscillator used for this downconversion process may be the same as that used forupconversion in the transmitter; this is the case illustrated in Figure 4.10. Note thatthe downconverted signal could be supplied at a digital IF and the quadrature con-version could be undertaken digitally within the controller.

Thus two sets of inputs are supplied to the controller which is sufficient toenable it to provide optimum control of the system in order to maximise the cancel-lation of the transmitter output signals in the receive signal path.

The detailed realisation of the controller may be achieved in many ways and theoption chosen depends upon the precise form of its reference and/or error signalinputs. In the system shown in Figure 4.10, the function of the controller is primar-ily to adjust the variable attenuator and phase-shifter in order to minimise the levelof the error signals at its input and to maintain that state as conditions change [suchas the movement of persons or objects in the vicinity of the antenna(s)]. The purposeof the reference signals in this case is to provide a coherent reference with which toperform this minimisation. Clearly, the reference signals could be omitted and anenergy minimisation performed on one or more of the error signals.

An alternative configuration is shown in Figure 4.11, in which the separatetransmit and receive antennas are replaced by a single antenna, and a circulator isused to provide the basic transmit/receive separation. This configuration has manyadvantages over that of Figure 4.10 since a single antenna is generally much moreacceptable to users of both handportable and mobile equipment. The action of the


Linear RFPA

I/Qbasebandinputs

ReceiveLNA


Transmitantenna

Controller

Vectormodulator

Unwantedcouplingthroughimperfectcirculator


Localoscillator

90º

0ºIn

90º

0ºIn

RF amplifier

90º

0ºIn

Figure 4.11 Alternative configuration involving a single transmit/receive antenna and a circulator.

circulator is to permit a radio frequency signal, within its operating frequency range,to travel in only one direction (illustrated by the arrows in Figure 4.11). The trans-mitter output signal is therefore prevented from appearing at the receiver input.

This embodiment also illustrates the use of a vector modulator in place of thegain and phase controllers shown previously. The type of vector modulator used isnot critical and could be modified by, for example, replacing the multipliers shownin Figure 4.11, by variable attenuators.

A similar result can, theoretically, be achieved by the use of a directional couplerin the transmit signal path. The coupler is arranged such that the transmit signalpasses to the antenna relatively unimpeded and the unidirectional coupled port feedsthe receiver input. The directivity of the coupler ensures that a significantly reducedlevel of the transmitter output signal appears at the input to the receiver. This config-uration is shown in Figure 4.12.

A disadvantage of this latter technique is that the sensitivity of the receiver iscompromised by the coupling factor of the coupler. Thus, a lower overall receive sen-sitivity than that of which the receiver alone is capable is obtained. A further problem


Linear RFPA

I/QBasebandinputs

ReceiveLNA


Transmitantenna

Controller

Vectormodulator

Unwantedcouplingthroughimperfectcoupler


Localoscillator

90º

0ºIn

RF amplifier

90º

0ºIn

90º

0ºIn

Figure 4.12 Further alternative configuration involving a single transmit/receive antenna and a directionalcoupler.

is that the directivity of the coupler is dependent upon its terminating impedancesand is likely to be poor when connected to an antenna (particularly a mobile or por-table antenna). It is not possible to utilise an isolator to alleviate this problem, as itsunidirectional nature would inhibit the (wanted) receive signals from the antenna.

An enhancement of the above concepts is to utilise a multi-path cancellationscheme. In the event that a sufficient degree of cancellation is unable to be providedby a single subtraction process, a number of additional subtraction processes maybe included. There is clearly a limitation to this process where the gain/phase flat-ness of the signals involved is the restriction in cancellation performance. This isoften due to the influence of the antenna return loss characteristic, which can have asubstantial slope or ripple with respect to frequency, particularly in the case of ahandset antenna.

4.3.3.2 Use of an Auxiliary Transmitter

One method of overcoming the above issue is to generate a separate cancellation sig-nal, at an appropriate power level, and use this in place of the transmit signal sample[3]. This approach allows the power of digital signal processing to be applied inmonitoring the received signal and optimising the digitally generated transmit signal,by means of adaptive filtering. Thus, a perfect cancellation vector may be generated,at all desired frequencies within the transmit signal bandwidth, and adaptively con-trolled to ensure ideal cancellation in a changing antenna environment. The requiredsystem arrangement for this technique is shown in Figure 4.13.

A clear disadvantage of this technique is the added complexity and cost of a sec-ond transmit chain. This transmitter will, however, be of lower power than that ofthe primary transmitter (at least 10 dB and more if the antenna match is good, or thecoupling network has some useful isolation). If this transmit chain can be fabricated


Linear RF PA(main)

ReceiveLNA

Transmit/receiveantenna

Subtracter

Couplingnetwork

D/A

Upconverter

U/C

D/Aconverter

DSP

Linear RF PA(lower power)

D/A

Upconverter

U/C

D/Aconverter

Downconverter

D/CA/D

A/Dconverter

Figure 4.13 Use of an auxiliary transmitter in an active transmit-signal cancellation system. (From:[3]. © 2005 IEEE. Reprinted with permission.)

as a part of the main transmitter IC (in a handset application), and it does notrequire a separate PA device (i.e., a good antenna match or isolation are provided),then the added cost should be minimal.

This technique is ideally suited to applications where the transmit channel band-width is broad, such as in CDMA, WCDMA, or OFDM. The earlier techniquewould certainly suffer a poorer level of performance in this case and would proba-bly, therefore, not be practical.

4.4 Achieving Image Rejection

4.4.1 Introduction

The presence of an image is an issue in all receiver systems. In single-band receivers itcan be dealt with relatively easily by the use of suitable RF and IF filtering and a sen-sible design for the downconversion frequency plan. In multi-band or general-cover-age receiver systems, the image problem becomes much more acute and alternativesto traditional IF filtering must be found to ensure good receiver performance. Thissection discusses the two primary options for solving this problem and describessolutions to some of the inherent practical issues in each case.

Arguably, a third option is the use of a direct-conversion receiver architecture.In this case, the image appears in-band and hence is well controlled, in so much as itis an image of the wanted signal and not of a signal at an unknown level relative tothe wanted signal. The special case of a direct-conversion receiver is discussed inChapter 3.

4.4.2 Use of a High IF

One possible technique for overcoming the problems of image rejection in awideband coverage receiver is the use of a very high first intermediate frequency.This places the image at a frequency well outside of the potential band of interestand hence enables its removal either by explicit filtering or by the implicit filtering ofthe antenna (much less reliable).

As an example, consider a receiver required to receive any signal in the fre-quency range 400 MHz to 2.5 GHz (thus covering virtually all of the mobile com-munications bands). The first IF could be chosen as, for example, 3.5 GHz, as thiswould allow a reasonably high degree of filtering to be achieved before the lowerend of the image frequency band, which starts at 7.4 GHz. This frequency plan isillustrated in Figure 4.14.

This arrangement has a number of disadvantages:

1. The synthesised first-local oscillator has to operate at a very high frequency(3.96 GHz in the example shown in Figure 4.14) and hence its phase noisecan be poor for a low-cost and low-power device.

2. The second local oscillator, which still requires low phase noise, also needsto operate around 3.5 GHz (depending upon the digital IF frequencychosen). Again this is potentially an expensive device, with the likelihood ofit also having a relatively high power consumption.


3. The high-dynamic range present at the front end needs to be preserved up toand including the second mixer [i.e., it needs to be preserved in the front end,first mixer, first IF amplifier(s), and second mixer]. This is due to the(assumed) range of channel bandwidths required to be processed by thisfront-end (e.g., from 3.84-MHz WCDMA to 30-kHz AMPS); the first IFfilter and amplifiers must be able to process the wider required bandwidthand this means having to deal with a large number of narrower-bandcarriers when operating in that part of the spectrum. This is quite an onerousrequirement and may be difficult to meet in practice. The high-dynamicrange techniques mentioned elsewhere in this chapter, particularly involvingthe incorporation of the mixer, could potentially be employed to good effecthere. However, this would add cost and complexity.

4. Obtaining a good IF filter response at 3.5 GHz is not straightforward. This isbalanced somewhat by the relatively relaxed requirements on this device interms of roll-off. It has, for example, around 400 MHz, within which it mustachieve sufficient attenuation to reject the local oscillator signal.

An alternative frequency plan is shown in Figure 4.15. In this case, the IF is nowplaced at a higher frequency, allowing the first local oscillator (LO) to run at a lowerfrequency. This will ease the requirements on this LO which, being synthesised, hasthe more difficult design issues regarding phase-noise, spurious, and so forth. Thisoption does, however, make the IF filter design more difficult and (potentially)expensive.

It is evident that the use of a high IF is not without its problems, although it doessolve the image-rejection issue. It is predominantly the cost and difficulty of over-coming these issues which have led to alternative options being considered. Themain alternative is image-reject mixing and this is described next.

4.4.3 Image-Reject Mixing

The basic concept of image-reject mixing is not new and has been described innumerous papers (e.g., [4]). The essential idea is to make use of the fact that theimage frequency will reflect about the frequency origin, when downconverted by

4.4 Achieving Image Rejection 159

Frequency(GHz)

IFfrequencyband

0.4

Complete receivercoverage: 400 MHzto 2.5 GHz

2.5 7.4

Complete imageband: 7.4 GHzto 9.5 GHz

9.53.5

...

LO range3.9 GHzto 6 GHz

Figure 4.14 Use of a high IF to achieve good image-rejection in a multi-band receiver.

the local oscillator, and hence will suffer a 180° phase reversal. This phase reversalcan be used to distinguish the image frequency from the wanted RF signal and henceto enable cancellation of the unwanted image.

The basic configuration of an image-reject mixer is shown in Figure 4.16. Notethat the local oscillator and RF input signals can be interchanged without loss offunctionality, but that the arrangement shown below has the advantage that it issimpler to produce the required broadband 90° splitter for a constant-level highstrength signal (i.e., the local oscillator signal). Some of the broadband quadraturetechniques described elsewhere in this book could be used for this purpose.

The in-phase splitter may easily be realised for broadband operation by eithertransformer or resistive splitting techniques; the latter having the disadvantage of a3-dB additional degradation in the mixer noise figure.

The quadrature combiner on the right-hand side of the diagram operates at theIF frequency and therefore need only be a (relatively) narrowband component.Transformer, microstrip, coupled-transmission-line, or lumped-element techniquesmay therefore be used in this component, depending upon the IF frequency chosen.

If this circuit is used as part of a high-dynamic range general coverage receiversystem, then the two mixers will require a good dynamic range to avoid blocking.This can be achieved with, for example, high-level diode or FET ring mixers (e.g.,


Frequency(GHz)

0.4

Complete receivercoverage: 400 MHzto 2.5 GHz

2.5 7.7

Completeimage band:7.7 GHz to9.8 GHz

9.8

...

LO range2.6 GHz to4.7 GHz

IFfrequencyband

5.1

Figure 4.15 Alternative frequency plan utilising a lower local oscillator frequency range.

Mixer

90º

0ºIn

90º

0º

50Ω

IF out

Image out

Mixer

RF input signal(wanted + image)

Localoscillator

Figure 4.16 Basic configuration of an image-reject mixer.

level 17 devices), or by utilising some of the lineariastion techniques described inSection 4.5.

4.4.3.1 Alternative Forms of Image-Reject Mixer

The image-reject mixer shown in Figure 4.16 is essentially a form of the Hartley IRmixer [5]. The original form of this mixer is shown in Figure 4.17. In this case, therequired IF quadrature is provided by the RC and CR networks, which are designedto operate at their 3-dB points, at the desired IF. This quadrature method isdescribed in more detail in Chapter 5.

An alternative configuration, more commonly used in upconversion (and,indeed, Cartesian loop transmitters [6]), is shown in Figure 4.18. This technique,known as the Weaver method, utilises a second pair of mixers to provide therequired output quadrature. The clear disadvantage of this architecture is therequirement for a second local oscillator; hence, it is not often used in practice. Therealisation of this latter quadrature mixing stage in the digital domain, within a


Mixer

90º

0ºIn

90º

0ºIn IF out

Mixer


Localoscillator 1

Lowpassfilter

Lowpassfilter

Mixer

Mixer

Localoscillator 2

Figure 4.18 A Weaver image-reject mixer.

Mixer

90°

0°In IF out

Mixer


Localoscillator

Lowpassfilter

Lowpassfilter

R

C

R

C

Figure 4.17 A Hartley image-reject mixer.

receiver, may alleviate this cost. This does, of course, assume that the cost of the rel-atively high-speed ADCs required to provide the analogue conversion, does notexceed the cost of the mixers and LO.

4.4.3.2 Enhancement of the Standard Image-Reject Mixer

The basic image-reject mixer described above relies on accurate gain and phasematching of the upper and lower paths to achieve a high degree of cancellation of theunwanted image signal. In a production component, with a reasonable temperaturespecification, it is possible to achieve an image rejection of around 20–30 dB typi-cally. This figure is far from the more than 60-dB requirement in order for it to besuitable for use in a general-purpose receiver, as the sole method of achieving imagerejection.

A possible enhancement is therefore to control the gain and phase balancewithin the image reject mixer, using an automatic control mechanism, in order toachieve and maintain a high degree of image cancellation. There are a number ofmechanisms by which this may be accomplished and each will be described next.

Note that the illustrated method in each case employs I and Q detectionand polar control; however, the control functions could be as easily implementedin vector form (e.g., using a vector modulator) with similar performance andoperation.

Control Based on Local Oscillator Nulling

Figure 4.19 shows a basic block diagram of this approach. The technique involvesthe injection of a small amount of DC into the RF ports of the mixers, thereby allow-ing some local oscillator feedthrough. If the system is perfectly balanced, then thefeedthrough should be cancelled at the output of the system (i.e., no local oscillatorsignal should be present). The control mechanism can therefore detect the residuallocal oscillator signal (in I and Q components) using either the input local oscillator(thus creating a DC error signal) or an offset (but tracking) oscillator, which will cre-ate an audio frequency error signal suitable for processing in a DSP. This latteroption will overcome the problems of DC offsets in the I/Q detection mixers andsubsequent analogue processing.

The gain and phase control components can appear in a number of locationswithin the basic circuit, including prior to the mixer in the lower path or the equiva-lent positions in the upper path. The same control circuitry and control signals couldbe used in all of the appropriate positions.

The advantage of putting the gain and phase control components after the mix-ers (either one) is that they are then only required to operate at the intermediate fre-quency and hence need only operate over a narrow bandwidth. This will make themboth lower cost and easier to realise in a practical system.

An alternative to utilising the LO directly is to utilise an offset frequency close tothe LO, in order to generate an audio-frequency IF, suitable for processing within alow-cost DSP. One option for this arrangement is shown in Figure 4.20. The keybenefit of this approach is that it eliminates DC offset issues for the downconversionmixers, analogue integrators, and ADCs (where used).


4.4A

chieving Image Rejection

163

Mixer

0ºIn

90º

0º

50Ω

IF out+ small LO component

Image out

Mixer

RF input signal(wanted + image)+ small DC voltage

Localoscillator

Φ

dt dt

90º

0ºIn

Variablephase-shift

Variableattenuator

IntegratorIntegrator

Correlator

Correlator

SplitterSplitter

Splitter

Quadraturesplitter

Quadraturecombiner

Quadraturesplitter

90º

Figure 4.19 Control of an image-reject mixer by utilising the local oscillator as a sounding signal.

164M

ulti-Band and General C

overage Systems

Mixer

90º

0ºIn

90º

0º

50Ω

IF out

Image out

Mixer


Localoscillator

Φ

dt dt

90º

0ºIn

Variablephase-shift

Variableattenuator

IntegratorIntegrator

Correlator

Correlator

Splitter

Splitter

Quadraturesplitter

Quadraturecombiner

Quadraturesplitter

Offset oscillator

A/D

D/AD/A

A/D

DSP

Mixer Mixer

Sounding signal oscillator(close to image signal)

Figure 4.20 Control of an image-reject mixer by utilising the local oscillator as a sounding signal and an offset oscillator for detection.

This system utilises a separate, locked local oscillator to downconvert the inputand output versions of the LO signal to, say, a few kilohertz or tens of kilohertz.This oscillator would track the main local oscillator (approximately it could operatewith a larger step size, for example, to lower cost) such that it maintains anaudio-frequency separation from the LO. For example, if the main LO wassynthesised in 5-kHz steps, the tracking LO could be synthesised in 25-kHz steps,thus yielding a maximum difference frequency of 25 kHz (since a 0-Hz differencefrequency is undesirable, due to the problem of DC offsets mentioned earlier).

Control Based on Sounding Tone Injection

The basis of this technique is to inject a sounding tone into the RF input to the imagereject mixer (in addition to the off-air signals) and utilise this to set up the gain andphase controllers. This signal can be located either close to the wanted RF signal(s)or close to the unwanted image signal(s). If the sounding signal is injected close tothe image frequency, the control circuitry will act to null out the sounding signal atthe IF output port of the complete image reject (IR) mixer. If it is injected close to thewanted transmission, the control circuitry will act to null the sounding signal at theimage output of the IR mixer.

In this description, the sounding signal could take the form of a CW carrier, aspread-spectrum signal, a swept tone, or a switched (TDM) signal. The positioningof the signal (in terms of its frequency) may vary over a wide range, with the wantedtransmission and image frequencies being able to appear on either side of the localoscillator frequency, depending upon the implementation of the IR mixer. Forexample, interchanging the role of the IF out and image out terminals in the abovediagrams, would have this effect.

In the system as described, with, for example, the image frequency set to behigher than the wanted transmission, then an image-like sounding signal couldappear anywhere (in frequency terms) above the LO frequency. Similarly, the trans-mission-like sounding signal could appear anywhere below the LO signal.

There are a number of advantages in placing the sounding signal close to, butnot at, the image frequency:

1. Correlation between the image signal and sounding signal is avoided; thiswould otherwise have the potential to provide erroneous controlinformation.

2. Any uncancelled sounding signal components appearing at the IF outputwill be offset from the wanted IF signal and hence will not get through the IFfilter (if the system is designed appropriately).

3. Close placement of the sounding tone to the image frequency will still ensuregood correlation between the image null point and the null point of thesounding signal. This will, in turn, ensure that a good overall level of imagerejection can be achieved and maintained, despite the frequency differencebetween the two.

Optimum placement of the sounding signal is probably one or two channelsaway from the image frequency (either side).


The main disadvantage of this option is the additional hardware required togenerate and subsequently downconvert the sounding signal.

Variations in this technique are discussed in the literature, utilising periodic cali-bration [7] or one-time only calibration [8]. In the latter case, digital storage of thecalibration coefficients is used to remove the need for periodic recalibration. Drift inperformance will still occur, however, and this must be characterised. It is clearlyless of an issue in the well-matched environment of an integrated circuit receiver, butwould probably yield unacceptable performance in a discrete solution (with periodicrecalibration being required).

Control Based on Direct Multiplication

A further alternative control scheme is proposed in [9] and shown in Figure 4.21. Inthis scheme, error signals are generated directly from the signals within the IR mixerand these are used to control a variable gain and delay element (the latter beingformed using a filter). It is similar, in some respects, to the first scheme described inthis section, since it utilises the local oscillator signals as a basis for assessing theamplitude and phase errors present in the system.

The phase and amplitude error signals, respectively, resulting from the error sig-nal generation processing shown in Figure 4.21(a), are given by:

V AARF

∆θ θ= − +

12

116

22

(4.10)

and

V A AA

ARF

∆ ∆= − +

12

18

2

(4.11)

where A = A1A2 is the product of the two LO signal amplitudes, θ = θ1 + θ2 is the sumof the phase angles of the two local oscillator signals, ∆A = ∆A1A2 + ∆A2A1 (where∆A1 and ∆A2 are the amplitude errors of the two local oscillators) and ARF is theamplitude of the RF input signal to the IR mixer system.

If the RF input signal is small (or disconnected for calibration), the above equa-tions reduce to:

V A∆θ θ= − 12

2 (4.12)

and

V A AA∆ ∆= − 12

(4.13)

These two signals therefore provide independent steering information for cor-rection of the amplitude and phase errors present in the system.

Figure 4.21(b) shows how these signals are utilised to correct the gain and phaseimbalance initially present in the system. The quadrature local oscillator signals,


4.4A

chieving Image Rejection

167

Mixer

In IF out

Mixer


LO1

Lowpassfilter

Lowpassfilter

Mixer

90° 90°

0° 0°In

Mixer

LO2

a

b

b-ab+a

Amplitudeerror, V∆A

Phaseerror, V∆θ

Figure 4.21 Multiplication-based control for a Weaver image-reject downconverter: (a) error signal generation; and (b) control system based on the generated errorsignals. (After: [9].)

together with the gain and phase error signal voltages, form the inputs to a variablegain/phase element block. The integral of the phase error voltage is used to vary thepole and zero locations of an integrated filter (by varying gmO), while the integral ofthe gain error voltage is used to vary the gain of the filter (by varying gm). In this way,the relative amplitude and relative phase of the two IF signals feeding the IF outputsummer/subtracter is varied, in order to maximise the degree of image rejectionachieved. The prototype device, described in [9], was reported to have an imagerejection of 26 dB, prior to calibration/correction, and 59 dB afterwards (based on a1.8-GHz RF input frequency and a 1.4-GHz image frequency). One point to note,however, is that once the approximation used to derive (4.12) and (4.13) is no lon-ger valid, the resulting calibration error leads to a significant drop in image-rejectionperformance. Consequently, if large RF input signals are expected on a regularbasis, periodic, rather than continuous, calibration should be employed.

4.4.3.3 Application of Polyphase Filtering in an Image-Rejection Mixer

The general concept and use of polyphase filtering is described in Chapter 5, forapplication in broadband quadrature networks in transmitters and upconverters. Itis, however, equally possible to utilise them in receivers (notably integrated circuit,single-chip receivers) and, in particular, as the IF quadrature network inan image-reject mixer [10, 11]. Their broadband properties are useful in this appli-cation, where a low-IF is required relative to the signal bandwidth underconsideration.

In a typical integrated circuit configuration for this low-IF application, twomatched bandpass filters would be incorporated within the IR mixer (occupying thepositions of the lowpass filters shown in Figure 4.17). These IF filters are notintended to provide image-rejection, merely to eliminate all other unwanted signalswhich pass through the (wide) front-end cover filter. A polyphase filter can be usedto replace these two bandpass filters and to provide both the required bandpassresponse and the required IF quadrature. The format of such a filter is shown in


Mixer

90º

0ºIn IF out

Mixer

RF inputsignal(wanted +image) LO1

Lowpass filter

Lowpass filter

Multiplier

In

LO2

Variablegain/delayelement

Amplitudeerror, V∆A

Phaseerror, V∆θ

Multiplier

90º

0º


Figure 4.22, while its inclusion within the context of an IR mixer is illustrated inFigure 4.23. Note that all components with a suffix 1 will ideally match those with asuffix 2 in these figures.

A key advantage of an IR mixer, when utilising a polyphase filter in this context,is that its bandpass characteristic is symmetrical about the IF centre frequency—ittherefore causes no degradation to the received eye. A conventional low-frequencybandpass filter will typically have an asymmetric response about its design centrefrequency, thereby distorting the received data eye (partially closing the eye in thecorresponding eye diagram).

A second key advantage of polyphase filtering in this application is that thedegree of component matching required in the two sections of the filter (upper pathand lower path) is much less stringent than that of the two conventional IF filters asdescribed above. In other words, a higher degree of image-rejection may beachieved for a given degree of component matching.

The degree of image-rejection which can be achieved is given by:

SR

R

Q

Q

IR

fb

=

+

=+

≅

1

1 4

1

1 16

14

2

2(4.14)

where Q is the quality factor of the filter, Rfb (= Rfb1 = Rfb2) is the value of the feed-back resistors (perfect matching assumed), and R (= R1 = R2) is the value of the crosscoupling resistors (again, perfect matching is assumed). This is, of course, the image


Vout1

From I/Qmixer

Vout2

C1

Rfb1

A1−1

R2

R1

C2

Rfb2

A2

−Vout1

Figure 4.22 An active polyphase filter [12].

leakage in an ideal implementation, with no component mismatch. The impact ofcomponent mismatch will be to degrade the amount of image-rejection calculatedusing (4.14), however the degree of matching required, for, say, 60 dB of imagerejection, is still a factor of 4 lower than that which would be required if conven-tional IF filters were to be used instead [11]. In this case, a mismatch of 0.4% wouldbe adequate, compared with a mismatch of 0.1% for conventional IF filters.

4.5 Dynamic Range Enhancement

The receiver in a software defined radio, particularly one operating over multiplebands, is likely to encounter a wider input dynamic range than is a single-modereceiver. This is due to the fact that an ideal multi-band software defined radio willhave little or no front-end filtering, to save both the size and cost which would beadded by the use of multiple front-end filters, for the multiple bands to be received.The front end is therefore likely to encounter a wide range of both potentiallywanted and certainly unwanted carriers and must process these linearly until at leastthe point where the wanted channel can be selected. Failure to do this will result insignificant blocking problems for the receiver and/or a significant EVM degradationfor the wanted channel.

This section presents a range of linearity enhancement techniques which areappropriate for receiver front-end designs. Some of these are only applicable to theLNA, whereas others can improve the linearity of the complete RF/IF signal process-ing subsystem. There are also differences in bandwidth applicability, with sometechniques providing very good performance over a narrow (single-channel) band-width and others providing perhaps less dramatic performance, but over a broad(multi-carrier or even multi-band) frequency range.

Many of the techniques presented are analogous to their high-powerlinearisation counterparts; however, the criteria for use in a receiver front end are


C1

Rfb1

A1

−1

R2

R1

C2

Rfb2

A2

Mixer

90º

0ºIn IF out

Mixer


Localoscillator

Figure 4.23 Application of a polyphase filter in an IR mixer.

significantly different. Specifically, noise performance is not typically a major prior-ity in a high-power design; however, it is clearly critical in a receiver front end.Indeed, some techniques (such as standard feedforward applied around anLNA/mixer) do not actually improve overall dynamic range; they merely shiftwhere the useable dynamic range appears in terms of signal power. In other words,they degrade the front-end noise figure by the same amount as they improve itsintercept point. A much cheaper equivalent, if a shift in dynamic range is the desiredgoal, is to insert an attenuator prior to the LNA.

Note that most of the techniques presented here will not compensate for genu-ine clipping of the signal. If front-end overload is occurring to such a degree thateither the LNA or first mixer is driven to this level, then non-linearity and conse-quent distortion/blocking are inevitable. Feedforward can provide some benefit inthis area, however this is at the expense of a higher-power error amplifier, witha consequent likely degradation in noise figure and thereby overall system noisefigure. Feedback techniques can actually increase the output distortion at thepoint where clipping occurs, since it will attempt to generate an infinite compensa-tion signal that can have a broad spectral characteristic (see, for example, [6],Chapter 4)

4.5.1 Feedback Techniques

Feedback is a commonly used technique in RF power amplifier lineariastion appli-cations, in its various guises: RF feedback, modulation feedback, Cartesian loop,and so forth. Some of these techniques are also applicable in receiver applications,particularly for linearisation of the front-end LNA. Some new feedback variants arealso emerging which are configured specifically with a receiver in mind and act tolinearise the first mixer and/or the LNA. The relative merits of all of these tech-niques will be discussed in this section.

The techniques to be discussed in this section concentrate on those which can beimplemented at a macro level, that is, taking mixers, amplifiers, and filters as sepa-rate blocks (in separate packages if necessary), rather than techniques which canonly be implemented at an integrated circuit design level. It is assumed, therefore,that the building blocks from which these systems are constructed are alreadyselected as being state-of-the-art devices. There is typically little point (from a costor size perspective) in using these techniques to improve a poorly performing mixer,for example, to the point of matching an existing state-of-the-art, stand-alonedevice. The existing device will almost certainly be smaller and lower cost.

The use of feedback as a mechanism for receiver linearisation has a number ofpotential advantages.

1. It is often capable of large linearity improvements, as long as it is operatedwithin its gain-bandwidth-delay product limit.

2. It is often (but not always) a simple technique to implement and hence issmall and low cost, both of these criteria being essential in commercial SDRapplications.

3. It can be used to linearise both the LNA and the front-end mixer, if properlyconfigured.

4.5 Dynamic Range Enhancement 171

4. It can generally be constructed in such a manner as to have minimal impactupon system noise figure; this is clearly an advantage in a receiverapplication.

4.5.1.1 Conventional RF Feedback

Conventional RF feedback may be applied externally to an existing LNA and canachieve relatively good wideband performance due to the inherently low delay oflow-power LNAs (particularly integrated, e.g., MMIC, designs). The main issue inthe application of such feedback is that it lowers the gain of the LNA stage by anamount equal to the degree of feedback applied. In most cases, this lowering of gain,and its consequent impact upon overall receiver noise figure, is not worth theimprovement in intercept point which it enables. A better technique, if a sacrificein noise figure is permissible, is to utilise a higher power LNA, based around amedium or even a high-power device (in, for example, military systems), and bias itfor good linearity. The overall performance achieved, measured as an improvementin dynamic range, is likely to be rather better than that obtained by linearising alower power device or MMIC.

4.5.1.2 IF/RF Feedback with Vector Subtraction

This technique (outlined in Figure 4.24) contains elements of both feedback andfeedforward, although it is essentially a feedback technique in terms of its distortioncancellation methodology. Its detailed operation is illustrated by the various spectra(amplitude versus frequency plots) shown at a number of points within the figure.


RF imagefilter

Downconvertingmixer

IF filter

Φ

Φ

Localoscillator

RFamplifier

Upconvertingmixer

RFamplifier

IFamplifier

Variablephase-shift

Variableattenuator

Variablephase-shift

Variableattenuator

RFinput

IFoutput

RF signalpathIF signalpathLO signalpath

Figure 4.24 Feedback-based mixer linearisation technique using IF/RF feedback. (From: [13]. © 2001 IEE.Reprinted with permission.)

The nonlinear downconverting mixer is fed with a combination of the wanted(input) signal and an error signal derived from the system output. The purpose ofthe error signal is to act as a predistorting signal for the mixer, with the feedbackmechanism operating continuously in real-time (unlike that of, say, conventionalpredistortion).

The error signal results from an upconversion of the IF output of the system,using the same local oscillator as that of the original downconversion process. Thisreupconverted signal must be filtered to remove image products and this filter willcontribute to the overall loop delay (perhaps significantly). The resulting RF errorsignal should now be comparable with the RF input signal (although containingunwanted distortion). Finally, a copy of the input signal is subtracted from the RFerror signal, with an appropriate gain and phase weighting to ensure near-ideal vec-tor subtraction. The resulting error signal resembles those typically seen in afeedforward system. It is then gain and phase weighted and amplified and added tothe original input signal, to form the RF input to the downconversion mixer, asdescribed earlier.

The degree of gain and phase matching required in the main-signal cancellationprocess, to achieve good performance, is reported to be quite high. A match of 0.1dB and 0.1° was used to generate the results outlined below. To achieve and main-tain these levels of matching in a practical solution would require an automatic con-trol system, in very much the same way as that of the error-generating loop in afeedforward system. Note that because this is a feedback-based process in the sys-tem described here, the cancellation performance will inevitably degrade withincreasing bandwidth (even with perfect gain and phase matching) and that this willintroduce a fundamental bandwidth limitation into the system.

The main advantage of the technique lies in its potentially high linearityimprovement capability. The technique was reported to be capable of some 20–25dB of IMD improvement for both a two-tone test and a π/4-DQPSK carrier. Thisrepresents a useful improvement in receiver intercept point. This linearity improve-ment was achieved with a minimal degradation in overall noise figure of 0.2 dB.This is a clear advantage over both feedforward and predistortion techniques.

The main disadvantages of the technique lie in its relative complexity, particu-larly when a control scheme is included to maintain the performance of the vectorcancellation part of the system, and its inherent gain-bandwidth limitation. Theimplementation described in the literature [13] is very narrowband, operating overtens or low hundreds of kilohertz and is therefore essentially a single-carrier tech-nique, suitable primarily for improving the signal quality of a single received(strong) signal. While it is undoubtedly possible to extend this bandwidth, particu-larly if the technique was to be implemented in an ASIC, it is unlikely ever to be suit-able for multi-band front-end operation, as it stands.

4.5.2 Feedforward Techniques

4.5.2.1 Feedforward Linearisation of an LNA

Feedforward [6] can be employed as an LNA linearisation technique as well asbeing used in high-power linearisation systems. In the case of a low-noise system,the feedforward process will cancel the noise generated in the main amplifier, which


can therefore be a relatively high-power (good intercept point), relatively highnoise-figure circuit. The critical elements, from a noise perspective, then become thereference-path components, which must be low loss, and the error amplifier, whichmust have a good noise figure. The error amplifier is, however, relieved of the bur-den of achieving a high intercept point, and hence can be a more conventional LNA.

The noise added by the main amplifier can be thought of as an additional signal,which is not also present on the reference path, and hence will appear as part of theerror signal. It will therefore be corrected as a part of the natural operation of thefeedforward process and, assuming a perfect gain/phase balance for the overall sys-tem, will be eliminated in the output of the complete feedforward amplifier. Thefeedforward process therefore not only eliminates distortion added by the mainpower amplifier, but also noise and indeed any other spurious signals present at theoutput of the main amplifier which are not also present in the reference path.

This is a very powerful and useful benefit of a feedforward system, as it allowsrelatively low-noise amplifiers to be constructed with extremely high third-orderintercept points, hence resulting in a very high dynamic range system.

The configuration of a feedforward system for use as a low-noise, high-interceptpoint amplifier is shown in Figure 4.25. Note that the two blocks labelled compen-sation circuit refer to the gain/phase controllers or vector modulators used toachieve optimum cancellation of the main signal energy in the error signal and of theerror signal energy (main amplifier noise and distortion) in the output signal.

The noise figure of a feedforward amplifier is determined by the elements of thesystem which are not included within the correction process (i.e., those elements ofthe loop for which correction is sought). In other words, noise added in the referencepath, or by the error amplifier and associated components, is not corrected for bythe feedforward process and will be added to the output signal at the level it appearsat the output of the error amplifier, less the coupling factor of the output coupler.

This may be summarised with reference to Figure 4.26 as follows: The total lossup to the error amplifier input is:

( )L L L L LT C TD S CC= + + +1 dB (4.15)

Since the components introducing this total loss may be assumed to be matchedto the characteristic impedance of the system (50Ω), it can be shown that the result-ing noise power is kTB (watts), where k is Boltzmanns constant (1.38 × 10−23 J/K), T


τ

Mainamplifier

Timedelay

LNAInput

Inputcoupler

Compensationcircuit

Erroramplifier

Subtracter

Outputcoupler

τCompensationcircuit

LNAoutput

Timedelay

Figure 4.25 Configuration of a feedforward system for optimum noise performance.

is the system temperature in Kelvin, and B is the bandwidth of interest (hertz) [14].The system input noise is therefore:

( )N kTBin = W (4.16)

The noise power at the output of the complete feedforward system may there-fore be derived:

( ) ( )N G F N

kTB

kTB

out err err in

F G C

F

A A C

A

=

=

=

−. .

.

10 10

10

2 2 210 10 W( )2 2 2 10+ −G CA C

(4.17)

where Ferr is the error amplifier noise factor3 and Gerr is the gain of the error ampli-fier, as seen at the output of the feedforward amplifier (i.e., incorporating the out-put coupler loss).

The system noise factor is therefore:

FN

G Nout

T in

= (4.18)

where GT is the total gain of the reference and error paths in the feedforward systemand is given by:

( )GTL G CT A C= − + −10 2 2 10 (4.19)

Hence, the system noise factor is:

( )( )( )F

kTB

kTB

F G C

L G C

A A C

T A C=

+ −

− + −

10

10

2 2 2

2 2

10

10 .(4.20)

Simplifying gives:


τ

Mainamplifier

Timedelay

Input

Inputcoupler

Compensationcircuit

Erroramplifier

Subtracter

Loss = L C1(dB)

Loss = L TD(dB)

Loss = L S(dB) Loss = LCC (dB)

Outputcoupler

Coupling factor = C C2 (dB)

Gain = G (dB)A2Noise figure = F (dB)

Matched 50Ω systemup to this point, hencenoise power = kTB

A2

Figure 4.26 Noise figure of a feedforward system.

3. Noise figure = 10log10(noise factor).

( )F L FT A= +10 2 10 (4.21)

Hence the system noise figure is given by:

( ) ( )F F L FdB T A= = +10 10 2log dB (4.22)

The noise figure of the feedforward amplifier, in the case where perfect nullingof the main amplifier distortion and spurious signals is assumed, is therefore deter-mined purely by the losses in the reference path and the noise figure of the erroramplifier.

Note that the input splitter and the subtracter in Figure 4.26 are both shown asdirectional couplers, configured to provide minimum loss to the reference signal.This is the optimum configuration for minimum noise figure, although it doesrequire a higher main amplifier gain than would a system based on 3-dB hybridsplitters.

The use of feedforward is unlikely ever to achieve the noise figure performanceof the very best LNAs, simply because there will always be a finite loss in the inputcoupler, subtracter, and reference-path delay line. These will add to the (potentiallystate-of-the-art) noise figure of the error amplifier, resulting in a compromised noisefigure. A properly designed feedforward system can, however, provide a usefuldynamic range enhancement over that of a conventional LNA, as it can extend theupper-end intercept point by more that it reduces the lower end noise performance(by increasing the noise figure). Designs have therefore been undertaken in, forexample, military applications, where a very high intercept point is advantageous toreduce or eliminate the impact of jammers.

4.5.2.2 Feedforward Linearisation of a Cascaded Front End

The various architectures shown in Figure 4.27 are options for utilising feedforwardto linearise a front end and first mixer—the critical elements as far as strong-signalshandling are concerned, in a typical receiver (an IF filter may be used to protect sub-sequent stages). Note that the IF delay-line could advantageously be implemented asan IF filter (e.g., using a SAW or ceramic device). This would then, in conjunctionwith the use of a filter preceding or succeeding the error amplifier, ensure that thecancellation process in the output coupler was a relatively narrowband subtraction.Such a subtraction could achieve good performance with relative ease.

There is, however, a fundamental flaw with all of these architectures. They donot achieve an overall benefit in terms of the achievable dynamic range from thefront-end. While each is capable of producing an increase in the input interceptpoint of the front-end, it will also yield an identical (or greater) increase in noise fig-ure, such that the overall dynamic range achieved remains unchanged. A much sim-pler (and cheaper) way of achieving the same end is to insert an attenuator in front ofthe cascade of an LNA and mixer, where the LNA is based upon the error amplifier,originally intended for use in the feedforward system.

The reason for this is that there is always one mixer which must handle the fulldynamic range of the signal and is not subject to IMD/noise correction by thefeedforward process [for example, the mixer in the reference path of Figure 4.27(a)].



τ

RF Mainamplifier

RF Timedelay

RFInput

Inputcoupler

Compensationcircuit

IF Erroramplifier

Subtracter

Outputcoupler


IFoutput

IF Timedelay

Local oscillator

Downconversionmixer

Downconversionmixer

(c)

(a)

τ

RF mainamplifier

RF timedelay

RFInput

Inputcoupler

Compensationcircuit

IF erroramplifier

Subtracter

Outputcoupler


IFoutput

(b)

IF timedelay

Localoscillator

Downconversionmixer

Downconversionmixer

Upconversionmixer

τ

RF mainamplifier

RF timedelay

RFinput

Inputcoupler

Compensationcircuit

RF erroramplifier

Subtracter

Outputcoupler


IFoutput

IF Timedelay

Localoscillator

Downconversionmixer

Downconversionmixer

Upconversionmixer

Figure 4.27 Various options for incorporating both the LNA and mixer within a feedforward-basedfront end: (a) Option1; (b) Option2; and (c) Option 3.

If it were possible to make a suitable mixer to meet the required specification for thisdevice (for a given application), it would be possible to use this same device (in con-junction with an attenuator and/or LNA) to achieve the same result, withoutfeedforward correction.

4.5.3 Cascaded Non-Linearity Techniques

A much better linearisation technique for receiver front ends is that of employing acascaded non-linearity. There are three locations in which this could be employed,and these are summarised in Figure 4.28. These configurations are essentially formsof predistortion or postdistortion and operate in exactly the same manner (seeChapter 6).

The form of non-linearity required in these systems can be very simple (e.g.,third order only), since front-end non-linearities tend to be relatively simple and wellbehaved (unlike those of most high-power RF amplifiers). The benefits of utilisingmore involved forms of non-linearity are normally outweighed by the complexityand cost disadvantages of their implementation.

Figure 4.28(a) shows a conventional predistortion configuration, applied to areceiver front-end. Again, non-linearity present in subsequent IF stages is ignored (atleast from the perspective of strong-signal handling/blocking), as the IF filter (fol-lowing the first mixer) will afford protection. The main disadvantage of this tech-nique lies in the loss inherent in the predistorter and its consequent noise figure.This will add to the overall noise figure of the receiver front-end. Even if a low-noise,active predistorter is used, the front-end noise figure will still be higher than that ofthe LNA alone. Although it is potentially a useable architecture, there are betteroptions.

Figure 4.28(b) shows a cascaded non-linearity in the form of a predistorter/postdistorter configuration, applied to a receiver front end. In this case, the non-linearity acts as a postdistorter to the LNA and as a predistorter to the mixer. In thisposition it should have a minimal effect on front-end noise figure, while providing asimilar linearity improvement to the overall system, as did the previousconfiguration.

Results from a system built using this configuration (by the author) yielded anintercept point improvement of around 10 dB at 1.8 GHz, although maintenance ofthis performance would either require good temperature tracking of the variousnon-linearities, or a control scheme. The noise figure degradation, when employingthe technique, was negligible.

Finally, Figure 4.28(c) shows a cascaded non-linearity, in the form of apostdistorter configuration for an LNA and mixer combination. Whilst this optioncan provide correction for the non-linearity experienced by the wanted signal(s), it isunable to aid in improving blocking and other issues caused by the non-linear pro-cessing of unwanted or out-of-band signals (e.g., cross-modulation). It is thereforeof limited use and provides no real benefits over the previous configuration. It couldalso act as a predistorter for an IF amplifier possessing poor linearity; however, it isusually better to design appropriately linear IF stages in the first place and not to relyupon a lineariser.


4.5.4 Use of Diplexer Elimination, Image-Reject Mixing, and High DynamicRange Techniques in a Receiver

The concepts which have been described in this section may be incorporatedtogether to form the universal receiver concept mentioned in the introduction toChapter 3. One embodiment of this arrangement is shown in Figure 4.29.

There are various valid configurations, based on the above concept, with someof the systems components being intertwined. For example, the high-dynamic rangefront-end amplifier is likely to form part of the diplexer elimination circuit


LNA

(a)

(b)

(c)

Predistorter

RF input IFoutput

LO Input

LNA Prepostdistorter

RF input IFoutput

LO input

LNAPostdistorter

RF input IFoutput

LO input

Figure 4.28 Options for the placement of a cascaded non-linearity in order to improve front-enddynamic range: (a) predistortion; (b) pre/postdistortion; and (c) postdistortion.

configuration. Similarly, the image-reject mixer could be linearised as part of thefront-end amplifier (as described earlier for a conventional mixer).

References

[1] Lucero, R., et al., Design of an LTCC Switch Diplexer Front End Module forGSM/DCS/PCS Applications, Proc. of IEEE International Microwave Symposium, Phoe-nix, AZ, May 2001.

[2] Hikita, M., et al., New Low-Distortion Band-Switching Techniques for SAW AntennaDuplexers Used in Ultra-Wide-Band Cellular Phone, IEEE Trans. on Microwave Theoryand Techniques, Vol. 52, No. 1, pp. 38–45, January 2001.

[3] Schacherbauer, W., et al., A Flexible Multiband Front-End for Software Radios Using HighIF and Active Interference Cancellation, IEEE International Microwave Symposium, Phoe-nix, AZ, May 2001, pp. 1,085–1,088.

[4] Joswick, W., Uses and Applications of I & Q Networks, Microwaves and RF, 1994.[5] Hartley, R., Modulation System, U.S. Patent No. 1,666,206, April 1928.[6] Kenington, P. B., High-Linearity RF Amplifier Design, Artech House, 2000.[7] Montemayor, R., and B. Razavi, A Self-Calibrating 900-MHz CMOS Image-Reject

Receiver, Proc. of 26th European Solid-State Circuits Conference, Stockholm, Sweden, Sep-tember 1921, 2000, pp. 292–295.

[8] Der, L., and B. Razavi, A 2GHz CMOS Image-Reject Receiver with Sign-Sign LMS Calibra-tion, IEEE International Solid-State Circuits Conference Digest Technical Papers, February2001, pp. 294–295.

[9] Elmala, M. A. I., and S. H. K. Embabi, Calibration of Phase and Gain Mismatches inWeaver Image-Reject Receiver, IEEE Journal of Solid-State Circuits, Vol. 39, No. 2, Febru-ary 2004, pp. 283–289.

[10] Crols, J., and M. Steyaert, A Single-Chip 900MHz CMOS Receiver Front-End with aHigh-Performance, Low-IF Topology, IEEE Journal of Solid-State Circuits, Vol. 30, No.12, December 1995, pp. 1,483–1,492.

[11] Hornak, T., Using Polyphase Filters as Image Attenuators, RF Design, June 2001,pp. 26–34.

[12] Voorman, J. O., Asymmetric Polyphase Filter, U.S. Patent No. 4,914,408, June 12, 1989.


Linearized RFpower amplifierFrom Tx baseband

circuitry andupconversion

High-dynamicrange (linearized)receive LNA


Universaldiplexer

Wide-coveragesynthesizer

Controlled Image-reject mixer

Figure 4.29 Complete universal receiver concept.

[13] Nesimoglu, T., et al., Linearised Mixer Using Frequency Retranslation, IEE ElectronicsLetters, Vol. 37, No. 25, December 6, 2001, pp. 1,493–1,494.

[14] Fish, P. J., Electronic Noise and Low Noise Design, New York: Macmillan Press, 1993,Chapter 4.


C H A P T E R 5

Flexible Transmitters and PAs

5.1 Introduction

Arguably the most important element of any software defined radio system,whether in a base station or handset, is the linear or linearised transmitter. Receiversystems have always required a high degree of linearity, as they must possess a goodstrong signal handling capability, in addition to good low-noise performance. In thecase of transmitters, however, a high degree of linearity is a relatively recent require-ment, arising predominantly from the widespread adoption of cellular networks.Transmitters used in this type of application require a much greater degree of linear-ity (i.e., a much lower level of distortion) than even single-sideband (SSB) lineartransmitters used in the past (e.g., for military applications). This is due to thenear-far effect present in cellular systems ([1], Chapter 1), which results in transmit-ter non-linearities causing significant interference to users of adjacent channels,thereby limiting system capacity. This limitation affects both uplink and downlink,depending upon which transmitter has the non-linearity problem: If it is the handsettransmitter, the uplink capacity of a nearby cell will be impacted; if it is a BTS trans-mitter problem, the downlink capacity of a nearby cell will be impacted. Evenwith the high-linearity transmitters available today, many city-centre systems arecurrently interference limited (in terms of capacity) rather than noise limited. High-linearity transmitters are therefore an enabling technology for many cellularsystems, irrespective of the use (or otherwise) of a software defined radio-basedarchitecture in their realisation.

In the case of a generic software defined radio system, a high-linearity transmit-ter is essential for any design that must be capable of operation on an enve-lope-varying modulation format. In practice, this means virtually all softwaredefined radio systems must adopt one or other of the high-linearity amplifier ortransmitter technologies highlighted in Chapter 6 and covered in detail in [1]. Thisfollows from the fact that most modern modulation formats incorporate somedegree of envelope variation, the only significant exception at present being GSMand its derivatives (DCS and PCS).

The basic architecture of a software defined radio transmitter revolves aroundthe creation of a baseband version of the desired RF spectrum, followed by a linearpath translating that spectrum to a high-power RF signal. The frequency translation(upconversion) and power amplification processes, involved in creating the highpower RF signal, must therefore fall into one of the following categories:

1. Inherently linear processing. The main mechanism by which this is ensuredis typically by the use of backoff of all stages from their 1-dB compression

183

points. This has the obvious advantage of simplicity, in terms of design, butis typically highly inefficient (particularly in the case of the power amplifier)and costly, since it is required to significantly overrate all of the componentsinvolved.

2. Linearisation of the RF PA. With this option, a linearisation technique, suchas those described in Chapter 6, is applied to the RF power amplifier,with inherently linear processing used for the upconversion system. Thissignificantly reduces the size and cost of the transmitter, relative to that ofoption 1, but still requires the upconverter to be overrated.

3. Linearisation of the complete transmitter. Linearisation techniques existwhich are capable of linearising the complete transmitter from itsbase-band input to its high-power RF output. This form of solution allowsthe upconversion processing to be more non-linear, hence requiring lessbackoff, and thus to be potentially cheaper. Again a number of thesetechniques will be described in Chapter 6.

4. RF synthesis techniques. The final option relies on the processing of constantenvelope waveforms throughout the upconversion and power amplificationhardware, with the desired envelope-varying RF waveform beingsynthesized by combining these waveforms at the output. Examples of thistype of system are described in Chapter 6.

5.2 Differences in PA Requirements for Base Stations and Handsets

A number of differences exist in the requirements placed upon an RF power ampli-fier, depending upon whether it is to be deployed in an SDR base station or handset(other than the obvious difference in output power requirement). These will dependto a degree upon the range of modulation formats to be supported (i.e., how genericthe system is designed to be) as well as potentially dictating the range of transmitterarchitectures and/or linearisation techniques that are applicable.

5.2.1 Comparison of Requirements

The primary constraints upon a base-station or handset linear PA or transmittermay be summarized as follows:

1. Output power. The output power of a base-station PA is typically muchgreater than that of a handset, both in terms of overall mean power and on apower-per-carrier basis. In some micro and pico-cell applications, the powerlevels of the two may be similar on a power-per-carrier basis, but typicallythe number of carriers involved dictates that the base-station PA is of a muchhigher power overall.

2. Size. This is the most obvious difference—a handset will clearly have muchless space within which the PA must be accommodated. In cellular basestations, a rack format is still common, although even here size is becoming amajor issue, particularly for micro and pico BTS applications.

184 Flexible Transmitters and PAs

3. Efficiency. The battery life of a handset is a key selling feature (or converselythe battery size/weight for a given talk-time)—efficiency is clearly of majorconcern here. Efficiency is, however, of arguably similar importance in thecase of the base station, due to issues of size, cooling, and running costs. Anincrease in base-station PA efficiency from, say, 10% to say 15%, whenmultiplied across a complete 3G network, can result in savings of manymillions of dollars per annum in electricity costs alone. These savings will becompounded in practice by additional savings in cooling costs, and powersupply costs. In addition, removing the need for air conditioning systemsand the reduction and/or removal of the need for cooling fans willsignificantly improve BTS reliability. In a typical BTS, it is the airconditioning unit which is the single least-reliable element and failure of thissubsystem frequently results in failure (due to overheating) of othersubsystems (notably the RF power amplifier or transmitter).

5.2.2 Linearisation and Operational Bandwidths

It is useful, at this point, to draw the distinction between the linearising and opera-tional bandwidths of a linear transmitter. An amplifier or transmitter is capable ofperforming linearisation over a certain channel or multichannel bandwidth, whichis determined by the bandwidth of the feedback loop (in, for example, a Cartesianloop transmitter) or gain/phase matching of the system components (in, for exam-ple, feedforward or predistortion amplifiers). This is termed the linearising band-width and will obviously depend on parameters such as the gain employed in thefeedback loop, as well as its bandwidth. A practical limit on this bandwidth is in theregion of a few hundreds of kilohertz (for a Cartesian feedback transmitter with ahigh level of loop gain and a standard RF power module) or a few tens of megahertz(for a feedforward or predistortion system). In the case of a feedback system, higherlinearisation bandwidths are possible when using very low delay power amplifiers.Examples include integrated circuit PAs found in handsets and broadband MMICamplifiers, both of which can have delays of less than 1 ns.

The operational bandwidth is defined by the circuit components, that is, thebandwidth of the power amplifier chain, the quadrature bandwidth of the localoscillators, and the phase-shift network, as applicable. It is the bandwidth withinwhich the linearising bandwidth can appear while still maintaining acceptable per-formance; this may be several tens of megahertz for a typical feedback design andmay be over 100 MHz for a feedforward or predistortion system. For example, atypical feedback transmitter operating in a mobile radio system utilising DAMPSmodulation would have a linearising bandwidth of 30 kHz and an operationalbandwidth of 30 MHz. In other words, the 30-kHz linear channel could appearanywhere in the 30-MHz spectrum allocation and, more importantly, could be real-located simply by reprogramming the channel synthesiser. Note that the linearisingbandwidth is defined here in terms of the wanted channel bandwidth. The lineariserwill clearly suppress all significant IMD products caused as a result of the signalsappearing within its linearising bandwidth. In the example above, significant IMDproducts could be generated over a bandwidth of a few hundred kilohertz as a result

5.2 Differences in PA Requirements for Base Stations and Handsets 185

of the signals falling within the 30-kHz linearising bandwidth. This wider band-width is sometimes referred to as the linearisation bandwidth.

5.3 Linear Upconversion Architectures

5.3.1 Analogue Quadrature Upconversion

One of the first upconversion architectures to be employed in a software defined radiotransmitter, quadrature analogue upconversion, is still widely deployed today.Although both the phasing and Weaver methods of upconversion can be supported, itis the Weaver method which is most commonly employed (see Section 5.3.6), as itrequires the minimum possible bandwidth (and hence sampling rate) for the D/Aconverters.

The basic configuration of this technique is shown in Figure 5.1. A quadrature sig-nal is generated by the DSP; this fits well with many digital modulation formats, asthese are typically generated in a quadrature format. The I and Q channel signals feedD/A converters which only need to operate ideally at a sampling rate equal to thechannel bandwidth (i.e., half of the Nyquist rate for the channel bandwidth). This isdue to the fact that the I and Q signals themselves only occupy half of the channelbandwidth, the full bandwidth being created only at the summed RF output.

The outputs of each of the D/A converters feed anti-alias lowpass filters. If thesampling rate is chosen to be the minimum necessary to fulfill the requirements ofNyquist, then these filters must be ideal brick wall types. In practice, a sampling ratesomewhat higher than that required by Nyquist is usually used and this is increas-ingly in the form of an interpolating DAC. Such a DAC operates internally at a muchhigher sampling rate than that of a conventional DAC and includes interpolation fil-tering, thereby ensuring that the alias products appear far from the wanted chan-nel(s). These products can therefore be filtered easily by conventional analoguelowpass filters.

The quadrature mixers and local oscillator quadrature splitter can be fabricatedusing discrete mixers and a 90º hybrid splitter. It is, however, more common forthese functions to be provided in a single integrated component in most softwaredefined radio applications. Integration into a single component has the advantage ofgood gain and phase matching (ripple) between the two paths and good temperature


90°

0°In

D/A

I-channelDAC

D/A

Lowpassfilter

Lowpassfilter

Q-channelDAC

DSP RF outputLocaloscillator

Figure 5.1 Quadrature upconversion in a linear transmitter employing an analogue upconverter.

stability for these parameters. It also generally allows a lower power local oscillatorsignal to be employed and this is advantageous in a handset application in reducingboth spurii and power consumption.

The local oscillator is generated by one of two main methods. The first is a fre-quency multiplication and division architecture which internally generates twice thelocal oscillator frequency and then divides this by two, generating quadrature localoscillator signals in the process. The second is by using a broadband 90º phase-shiftfilter (a polyphase filter). This latter option has the advantage of being a linear pro-cess, thereby generating far less energy at the second harmonic of the local oscillatorand hence producing a cleaner output spectrum. It also allows the variations in per-formance at a range of local oscillator levels to be assessed, and an optimum level tobe selected to fulfill a particular requirement (e.g., gain and phase balance, LOfeedthrough, and IMD level).

5.3.1.1 Issues and Mitigations for an Analogue Quadrature Upconvert Architecture

I/Q gain and Phase Imbalance

In any analogue system with two notionally equal-level outputs there will inevitablybe a small gain and phase error between them. This error will have two elements: astatic (i.e., frequency invariant) component and a frequency-varying (ripple) com-ponent. Both will generate (if uncompensated) an unwanted in-band image signal,falling on top of the wanted signal, but lower in level. In the case of the static com-ponent, it is possible to compensate for this error by predistorting the I and Q sig-nals, either internally within the DSP or externally in analogue hardware. In eithercase, the form of compensation required is shown in Figure 5.2.

The required compensation may be achieved by modifying the I and Q base-band signals supplied from the DSP in the manner shown in Figure 5.2. A small frac-tion of the I channel signal is added to the Q channel output, and by alteration of the

5.3 Linear Upconversion Architectures 187

Quadratureinput signals

KQ1

KI2

I

Q

Compensatedquadratureoutput signals

I'

Q'

I

Q

Input signals Output signals

I

QQ'

KI1

KQ2

I'

Figure 5.2 Compensation for quadrature upconverter errors.

variables KX1 and KX2 (where X = I or Q), any amount of gain and phase mismatchmay be accommodated. This is directly analogous to the method discussed in Chap-ter 3 for receiver I/Q mismatch compensation.

It is possible to automate the compensation process by providing a feedback ref-erence path and thereby generate an error signal to correct the mismatch. Clearlythis feedback path must have a more accurate quadrature gain/phase balance thanthe upconverter, in order to improve its performance. It is unlikely that this will bepossible using analogue hardware (if it were, the required design changes should beincorporated into the upconverter), and hence a digital solution is required. Thebasic form of this solution is shown in Figure 5.3.

A number of alternative solutions have been proposed, based upon the provisionof an analogue (and hence imperfect) quadrature demodulator in place of the digitalIF and quadrature demodulator shown in Figure 5.3. These are detailed in the litera-ture [26]. Most of these methods rely on the provision of a training sequence withinthe data, or a training signal (e.g., tones). Training sequences are usually undesirablein any transmission system, as they effectively waste data and hence reduce thecapacity of the link. They are sometimes provided for other purposes, however, suchas to allow the receiver to synchronise and in this case a dual use of the trainingsequence can be envisaged. A further drawback of these schemes is that they are typ-ically slow and may also rely upon a near-perfect knowledge of the characteristics ofthe detector used (often an envelope detector). It is clearly better, if at all possible, touse a digital IF and an ideal digital quadrature demodulator.

The use of a digital IF in the feedback path, allows the feedback path quadratureprocessing to be performed digitally and hence be perfect from the viewpoint of I/Q


90º

90º

0º

0º

In

D/A

I-channelDAC

D/A

Lowpassfilter

Lowpassfilter

Q-channelDAC

DSP RF outputOn-channellocal oscillator

In A/D

A/Dconverter

Mixer

Lowpassfilter

NCO

Off-channellocal oscillator

Digital IF (e.g. ~tens of megahertz)

Idealquadraturereferencesignals

Figure 5.3 Automation of the quadrature error compensation process.

errors. It is therefore possible to envisage a number of algorithms which can takeadvantage of this perfect reference in order to compensate for I/Q gain and phaseimbalance in the analogue quadrature upconverter. Compensation would take theform of a weighted summation of some of the I-channel output signal into theQ-channel and/or vice versa, as shown in Figure 5.2. This would ideally take placedigitally prior to the DACs, although this does imply a small loss of dynamic range,due to the compensation headroom required.

The A/D converter required in the feedback path of Figure 5.3 must be capableof sampling fast enough to deal with an IF input. It will therefore need to sample at aminimum of twice the sample rate of the I/Q DACs (ignoring interpolation), andusually somewhat higher than this. The distortion performance of this converter(and, indeed, its dynamic range) should not be critical if a suitable algorithm is used,assuming that only I/Q gain and phase errors are to be compensated. More typicallythis feedback path is also used for distortion measurement in some form oflinearisation technique, and in this instance distortion performance becomes muchmore critical (see Section 6.3.1.4).

Image suppression is arguably most critical in a multi-carrier system in whichthe carrier distribution may be non-symmetrical about the centre frequency of theband, or allocation, of interest. A four-carrier WCDMA system is a good exampleof this, as shown in Figure 5.4. It is possible, although not necessarily desirable, tohave a bandwidth occupancy of the type shown in this figure and this leads to animage signal appearing on an unoccupied channel. This image will therefore appearas an adjacent channel signal and hence will be required to meet adjacent channelpower levels (e.g., those specified by 3GPP [7, 8]). If, on the other hand, the spec-trum allocation was fully occupied (all four channels used), then the image specifi-cation would be determined by signal quality requirements, such as signal vectorerror, (SVE) [sometimes known as error vector magnitude (EVM)].


Amplitude

FrequencyCenter ofallocated band

Allocated bandwidth

Channel Channel Channel

ImageImageImage

Unwanted localoscillator leakage

1 2

4 2 1

4

Figure 5.4 Non-symmetrical carrier distribution for a four-carrier WCDMA allocation showingunwanted in-band image products.

The frequency varying (ripple) component of the gain and phase imbalance willhave a similar impact to that described above (i.e., it will also contribute to theunwanted image). In this case, however, the impact will typically be an order ofmagnitude or more lower than that of the uncompensated static errors (and oftenmuch more for a integrated circuit implementation). This is due to the amount ofripple typically being much smaller than the static errors, in most quadratureupconverter designs. The other key difference is that it is much more difficult tocompensate (either manually or automatically) for the effects of ripple and it is usu-ally not necessary (or economic) in most systems.

An alternative or additional solution to providing controlled image suppression(as described earlier) is to detect the overall bandwidth of the input signals (e.g.,using an FFT algorithm) and to retune the LO signal(s) to ensure that the spectrum isalways symmetrically distributed around the upconverter LO. This then ensures thatthe in-band image spectrum always falls directly on top of the carriers, therebyrelaxing the image suppression requirement. The limitation is now set by eitherEVM requirements (e.g., 34 to 40 dBc for 2% to 1% EVM) or by the use of asym-metric carriers (e.g., one at full power and one backed-off). The only circumstance inwhich this frequency symmetry is not valid is in, for example, a four-carrierWCDMA system in which carriers 1, 2, and 4 are turned on and carrier 3 is turnedoff (as shown in Figure 5.4). This is an uncommon scenario (globally) as most allo-cations are 1, 2, or 3 carriers, and hence this may be an acceptable limitation.

LO Leakage Suppression

Local oscillator leakage in the output spectrum occurs at the centre frequency of theupconversion process and hence is typically in-band (as shown in Figure 5.4). It can-not therefore be removed by filtering, which is the traditional method of eliminationin conventional upconverters.

Carrier leakage has three main mechanisms:

1. Imperfect isolation between LO and RF ports in the mixers. This can occurboth in discrete FET or diode-ring based mixer implementations and in ICmixers. It can only be improved by better design of the mixers themselvesand is a typical selection parameter for mixers to be used in directupconversion applications.

2. Unwanted DC generated within the mixer appearing on the IF port andcausing leakage of the LO signal through to the RF port. Unwanted DCwithin the mixer is typically generated by non-linear self-mixing of the IF orlocal oscillator signals. Self-mixing of either of these signals (i.e., multiplyingthe signal with itself) will result in one or more harmonics of the signal(depending upon the order of non-linearity involved), plus a basebandcomponent incorporating DC. It is this DC component, when it appears inthe IF portion of the mixer, which causes unwanted LO leakage.

3. DC offsets appearing at the mixer input. These can be generated by the IFinput circuitry of a quadrature upconverter chip (e.g., DC offsets from aninput amplifier) or by DC offsets at the output of the I and Q DACs or filters,which are connected to the IF inputs. These can be eliminated by ACcoupling, assuming that a gap exists in the centre of the desired output


spectrum (as is the case in Figure 5.4). This is illustrated in Figure 5.5. If a gapdoes not exist, as is likely to be the case in systems employing an odd numberof adjacent carriers, then a calibration technique (described next) is required.Note that the roll-off of the AC-coupling process will be 6 dB/octave or 20dB/decade (for a single-pole filter, i.e., a coupling capacitor), but that this isbased on octaves at baseband. In other words if the 3-dB frequency is chosento be 1 kHz, 60 dB of attenuation will, theoretically, be provided at 10 Hz.This will then create a notch at the centre of the RF band with a 3-dBbandwidth of 2 kHz and a 60-dB bandwidth of 20 Hz.

The effect of all three of the sources of carrier leakage is the same and hence asingle method may be used for their elimination. Since DC leakage from the DACsinto the mixer IF inputs can generate LO leakage, injection of an appropriateamount (and sign) of DC can be used to eliminate it. It will eliminate the effect of allsources of leakage since they can be viewed as a vector summation and the deliber-ately injected DC is designed to cancel the resultant (and not the individual sources).

The hardware architecture required to achieve this is conveniently the same asthat required to remove static gain and phase errors (shown in Figure 5.3). As LOleakage is an error in the forward path of a feedback system, which is not replicatedin the feedback path (as the feedback demodulator is implemented digitally), it istherefore possible to eliminate it—ideally by DC injection into the mixers from theforward-path DACs. If the loss of dynamic range from these DACs is unacceptable,separate, low-performance DACs may be used, as shown in Figure 5.6.

Out-of Channel/Band DAC or Upconverter Noise Floor

Many specifications (e.g., 3GPP [7]) place stringent requirements on out-of-channeland out-of-band emissions. In most systems, the close-to-carrier emissions are


Amplitude

FrequencyCenter ofallocated band

Allocated bandwidth

Channel Channel Channel

ImageImageImage

Response of AC coupling filter at output of both baseband DACs

21

4 2 1

4

Figure 5.5 Incorporation of AC-coupling between the I/Q DAC outputs and the mixer IF inputs in aquadrature upconverter.

dominated by distortion in the transmit power amplifier; however, this situationchanges far from the wanted carrier (many tens of megahertz, typically). This isillustrated in Figure 5.7.

Far from the wanted carrier, noise from the DAC and the upconverter becomedominant and these result in a relatively flat noise spectrum (unlike IMD). Clearly, ifthe spectrum being transmitted consists of a number of relatively narrowband,widely spaced carriers (e.g., from a GSM multi-carrier transmitter), then DAC andupconverter noise may well be visible between the carriers and may dominate thenoise in this area. The situation shown in Figure 5.7 is primarily illustrative of thecase of a single wideband non-constant envelope carrier (e.g., CDMA) or a numberof closely spaced carriers (either narrowband or wideband).

Mitigation in this case must, in general, revolve around the specification andoptimum use of both the DAC and the upconverter. In general, a discrete passiveupconverter (e.g., diode-ring mixer based) will have a better noise performance thanwill an integrated circuit implementation. It will also, of course, have a generallypoorer gain and phase balance and an insertion loss—all of these parameters must


90º

0ºIn

D/A

I-channelDAC

D/A

Lowpassfilter

Lowpassfilter

Q-channelDAC

DSP RF outputOn-channellocal oscillator

In A/D

A/Dconverter

Mixer

Lowpassfilter

NCO


Digital IF (e.g. ~tens of megahertz)


D/A

I-channellow-freq.DAC

D/A

Lowpassfilter

Lowpassfilter

Q-channellow-freq.DAC

I-channel DCcompensation

Q-Channel DCcompensation

90º

0º

Figure 5.6 Use of separate DACs for LO leakage suppression.

be traded off in a given design. The only filtering help which is available (and thenonly for the DAC noise) is obtained from the anti-alias filters. In systems where theDACs are not used to provide linearity improvement (e.g., by predistortion), thenthese filters may produce a modest amount of assistance. In the case where theDACs are being used to provide linearity improvement, it is likely that the anti-aliasfilters will need to have a bandwidth such that significant roll-off is not available tohelp meet the nearer of the out-of-band specifications.

LO Phase Noise

The amount of phase noise present on the upconversion LO is important in achiev-ing both good adjacent channel performance and good EVM performance, from anysoftware defined radio transmitter. Poor phase-noise performance may be intrinsicto the design of the oscillator, in which case the only solution is an improved design,or it may be due to modulation of the VCO by the high-power output from the trans-mitter. This latter problem is most common in systems using an on-frequency VCO,such as the direct upconversion system being considered here.

There are two main solutions to this problem:

1. Improved screening of the transmitter output (and any noise/RF it induceson supply lines) from the VCO and its supply lines;

2. Realisation of the on-frequency LO from a mix of two off-frequency LOs.This approach ensures that neither of the VCOs appears on-channel and thisgreatly reduces the potential for interference from the transmitter outputsignal.

Note that the clocks feeding the data converters are also critical in this regardand these must have a very low jitter. Since these are commonly derived from thesame reference as the LO synthesiser(s), it is important to maintain the purity of thisreference.


Amplitude

Frequency

Channel

DAC andupconverternoise dominate

DAC andupconverternoise dominates

IMD noisedominates

IMD noisedominates

Figure 5.7 IMD and noise contributions to out-of-channel emissions.

EVM Performance

Transmitter EVM performance is determined by a number of factors:

1. LO leakage;

2. I/Q error or image suppression;

3. LO phase noise.

Assuming that these factors are reduced, to the degree required to meet the othersystem requirements (e.g., adjacent channel performance), they should be easilygood enough not to compromise EVM performance in most systems [likewise forpeak code domain error (PCDE)].

5.3.2 Quadrature Upconversion with Interpolation

This scheme, shown in Figure 5.8, is similar to the basic quadrature upconversionscheme described earlier (and is identical if interpolating DACs are used in thatscheme). Interpolation is important (and arguably essential) in ensuring that thealias products produced by the DACs are sufficiently separated from the wantedchannel(s) such that they can be attenuated to an acceptable level by the analogue,lowpass, anti-alias filters. These filters will typically have a demanding flatness spec-ification, particularly if they form part of a linearisation scheme, such aspredistortion, or an RF synthesis technique, such as LINC [9, 10]. Requiring abroad, flat passband restricts the type of filter which can be employed to, for exam-ple, Bessel, Butterworth, or very low ripple Chebyshev designs. All of these designsrequire a very high order of filter to be employed in order to achieve a reasonableroll-off in the stopband and there are practical restrictions on the maximum orderthat can be achieved. All of these considerations lead to a desire to place the aliasbands as far as is practicable from the wanted channels; oversampling coupled withinterpolation is a relatively simple method of achieving this.

The technique of interpolation operates by increasing the effective sample rateof the input waveform, by synthesizing additional samples in between the existing


90º

0ºIn

D/A

I-channelDAC

D/A

Lowpassfilter

Lowpassfilter

Q-channelDAC

Digitalinterpolationfilters

RF outputDSP Localoscillator

n

n

Figure 5.8 Quadrature upconversion in a linear transmitter employing an analogue upconverterand digital interpolation filtering.

samples. These new samples are based upon a weighted average of the original sam-ples. The DAC now needs to operate at this new sample rate, which may be typically4 or 8 times the original (e.g., Nyquist) sample rate. This clearly places far greaterdemands upon the DAC, but it does allow the bulk of the signal processing (i.e.,everything prior to the interpolation process) to operate at the minimum possiblesample rate.

Figure 5.9 illustrates this process in the time domain for a single sinusoidalinput signal at an original sampling rate of 5 samples per cycle [Figure 5.9(a), i.e.,well within the Nyquist limit] and an oversampling rate of 4 [Figure 5.9(b)]. It canbe seen that each of the original samples has been replaced by 4 new samples, withthe sample time consequently reduced to one quarter of that of the original sam-pling process. The effect of this on the DAC output can be seen in Figure 5.9(c, d)for the original and oversampling rates, respectively. It is clear that in Figure 5.9(d)a much more recognizable facsimile of a sinewave is generated and it follows thatthis will therefore result in a cleaner output spectrum.

Figure 5.10 illustrates the effect of the various processes shown in Figure 5.9, inthe frequency domain. In Figure 5.10(a), the complete spectrum of the non-interpo-lated DAC output can be seen (up to the fourth Nyquist zone). The anti-alias filterrequired in this case would need to have an adequate roll-off by the first imageproduct—a tight specification. If interpolation is now employed, the situation


Four samples replaceeach original sample

TimeTime

TimeTime

(a) (b)

(c) (d)

1/4fClock

1/4fClock1/fClock

1/fClock

Figure 5.9 Time-domain view of the effect of interpolation on a sinewave input signal: (a) 5 samplesper cycle; (b) 20 samples per cycle; (c) unfiltered DAC output from (a); and (d) unfiltered DAC outputfrom (b).

improves to that shown in Figure 5.10(b); the interpolation filter is now able togreatly attenuate the images found in the first, second and third Nyquist zones, leav-ing only that present in the fourth zone. Given the large frequency separationbetween this product and the wanted fundamental, it is a fairly straightforward mat-ter to design an antialias filter to eliminate it.

The job of this anti-alias filter is made even simpler by virtue of the effect of thesin(x)/x response of the DAC itself (illustrated in Figure 5.10(c) for the non-interpo-lated DAC and Figure 5.10(d) for the interpolated DAC). In both cases, the DACresponse helps to attenuate the alias products; however, in the non-interpolatedcase, the attenuation of the first image is small. This means that a tight anti-alias fil-ter response is still required and little advantage is gained from the DAC roll-off. Theuse of interpolation, however, allows the DAC response to have a beneficial effect,with a useful level of attenuation being provided in the fourth Nyquist zone.

The internal structure of an interpolating DAC is shown in Figure 5.11. Theinput data is fed to a latch that holds the data for access by the interpolation routineand filter. The interpolation processing is clocked at the relevant multiple of theinput data rate (i.e., four times, in the example given earlier) and this is also the clockrate for the DAC itself. The internal data rate between the interpolation process andthe DAC core is then very high; however, as this takes place on-chip, it is not an


Frequency

Fundamental

Attenuatedfirst image

(b)

Digital interpolationfilter response

(a)

2fFrequency

3f 4ffClock Clock Clock Clock

Fundamental First image

(d)

Frequency

Fundamental

DAC frequencyresponse

(c)

Frequency

Fundamental

DAC frequencyresponse

Am

plit

ude

Am

plit

ude

Am

plit

ude

Am

plit

ude

2f 3f 4ffClock Clock Clock Clock

2f 3f 4ffClock Clock Clock Clock 2f 3f 4ffClock Clock Clock Clock

Figure 5.10 Frequency-domain view of the effect of interpolation on a sinewave input signal:sampled output spectrum (a) before and (b) after interpolation; and DAC output (c) from (a) and (d)from (b), showing effect of the sin(x)/x response.

issue. The interface data rate between the DSP and the (interpolating) DAC chipnow returns to the minimum possible rate (usually Nyquist plus an implementationmargin). Typical DAC devices are capable of good performance at up to 80% of theNyquist limit.

Clock multiplication may be provided on-chip in the form of a frequency multi-plier or phase-locked loop (PLL), or it may need to be provided externally by theuser. It is, of course, possible to implement the interpolation processing externally,within the signal processing which generates the input data. It is then necessary,however, to utilise a DAC with a very fast input interface [e.g., low voltage differen-tial signalling (LVDS)]. Obtaining a suitable DAC, with an appropriate sample ratecapability, may be both costly and difficult and this may make a discrete implemen-tation of the technique unattractive. The main problem, at present, with providinghigh-speed DACs is generally not in the DAC core itself; it is more typically thedigital interface that proves to be the bottleneck.

Interpolating DACs are usually more expensive than their non-interpolatingcounterparts (due to the large silicon area occupied by the interpolation filter). Itmay therefore be cheaper to use a non-interpolating DAC and implement the inter-polation filter on the DSP device (space permitting) or as part of an ASIC, if one isbeing used for the signal processing operations.

5.3.3 Interpolated Bandpass Upconversion

Interpolated bandpass upconversion (Figure 5.12) is similar to that describedabove, except that the interpolation filter now selects one of the higher images.It can therefore be viewed as analogous to alias downconversion, when using anADC.

This architecture has the advantage that local oscillator leakage is now no lon-ger a part of the wanted output spectrum and hence can be eliminated more easily(e.g., using an analogue highpass filter). It does, however, place greater demandsupon the analogue performance of the DAC and the DACs sin(x)/x response mayintroduce an unacceptable amplitude slope across the bandwidth of interest. This is


D/AnInput datalatch

Digitalinterpolationfilter

fClock

4f Clock

N N N

xN

Frequencymultiplier

Data input Analogueoutput

InterpolatingDAC

fClock

Figure 5.11 Structure of an interpolating DAC.

unlikely to be a problem for a single narrowband carrier but may be more significantfor a multi-carrier CDMA transmitter.

5.3.4 Digital IF Upconversion

It is now possible, with modern DACs, to obtain an output at a useable IF frequency(i.e., many tens of megahertz). This brings with it the option of performing therequired quadrature upconversion processing in the digital domain, thereby achiev-ing near perfect image rejection and local oscillator suppression. The architecturerequired to do this is shown in Figure 5.13.

The implementation shown in Figure 5.13 still employs interpolation filteringand this provides the same benefits as previously obtained with the analogueupconversion architecture of Figure 5.8. The outputs of the interpolation processesnow feed a digital quadrature upconverter, which utilises a numerically controlledoscillator (NCO) as the local oscillator signal.

The use of an NCO permits frequency-hopping to take place digitally, if desired,and this can typically provide a much shorter hop time than with an analogue PLL.If this approach is chosen, however, it is important to note that the analogue IF filtermust now be widened to cover the whole bandwidth over which hopping may occur(typically the whole frequency allocation). It is therefore no longer able to removeclose-in DAC spurs and these must be sufficiently low to meet the required systemspecification unaided.


90º

0ºIn

D/A

I-channelDAC

D/A

Lowpassfilter

Lowpassfilter

Q-channelDAC

Bandpassdigitalinterpolationfilters

RF OutputDSP Localoscillator

n

n

Figure 5.12 Analogue quadrature upconversion employing bandpass interpolation.

90º

0ºIn

IF outputDAC

Digitalinterpolationfilters RF output

n

n

D/ADSP

Digital quadratureupconverter

Bandpassfilter

MixerBandpassfilter

RF amplifierNCO

Local oscillator

Figure 5.13 Transmitter architecture employing a digital IF output.

The output of the digital upconverter feeds an IF output DAC, which, ifoversampled, may be operating at a rate of many hundreds of megahertz. The out-put of this DAC contains the wanted band, plus a range of harmonic and alias prod-ucts. These are typically removed using a bandpass filter (e.g., a SAW filter);however, some simple analogue lowpass filtering to eliminate some of the higherharmonics may also be beneficial (the higher-frequency stopband attenuation ofsome filters can be poor). Once the wanted IF band has been selected by this first IFfilter, one or more stages of conventional frequency upconversion may then beemployed to translate the signal to its final RF allocation.

This architecture has the advantage that only a single DAC is needed, althoughthe requirement for one or more IF filters (with typically a tight specification) willfrequently more than offset the cost saving of a second DAC. In addition, the perfor-mance of most DACs with an IF output will be poorer than with a baseband output,thus making a given specification more difficult to achieve. Comparing the perfor-mance of a typical DAC, when utilising a 5-MHz baseband signal and a 20-MHz IFsignal, indicates that a 5- to 10-dB reduction in spurious-free dynamic range canresult. This assumes that the DAC is designed to operate at a suitable sample rate,such that the 20-MHz IF can be accommodated with a reasonable, but not anexcessive, margin.

5.3.5 Multi-Carrier Upconversion

Figure 5.14 shows a logical extension of the digital IF transmitter architecturedetailed above. In this case, multiple carriers (three are shown) are sepa-rately upconverted, each by its own NCO. These are then summed digitally, prior todigital-to-analogue conversion. Since this is now a multi-carrier signal, thepeak-to-mean ratio of the signal is likely to have increased, unless steps are taken tocounteract this effect (e.g., prefilter and/or postfilter clipping, carrier phasing, andcrest factor reduction). The DAC must possess a sufficient dynamic range to copewith this and hence this architecture is generally the most demanding in terms ofDAC performance.

The circuitry following the DAC is similar to that described earlier for a digitalIF based transmitter. The main differences in this case are:

1. The filtering must now be sufficiently wide to cope with a number of notnecessarily adjacent carriers, but while still having a similar roll-off(typically) to that of the single carrier system. This therefore places greaterdemands upon the filter design.

2. The dynamic range of the active circuitry (mixers, amplifier, and so forth)must be greater in order to cope with the greater peak-to-mean ratio of themulti-carrier signal.

The NCOs may be used for frequency hopping, as outlined earlier for the digitalIF architecture. In this case, however, there is no disadvantage in terms of the ana-logue IF filter, as this must already cover the whole band of interest and hence theDAC spurs must be low enough to meet the system requirement (or this architecturecannot be used).


200Flexible Transm

itters andPA

s

IF outputDAC

RF output

Pulseshaping

n

n

D/ADSP

Bandpassfilter

Mixer

Bandpassfilter

RF amplifierNCO



Pulseshaping

n

n

DSP

NCO

90º

0ºInPulse

shaping

n

n

DSP

NCO

Local oscillator


90º

0ºIn

90º

0ºIn

Figure 5.14 Multi-carrier transmitter architecture employing a digital IF output (three-carrier version shown).

Standard integrated circuits are available which implement the digitalupconversion and NCO functionality of the above system, typically for four carri-ers. Alternatively, the whole of the digital system, including modulation generation,coding, and framing, can be implemented in a single application-specific signalprocessor (ASSP).

5.3.6 Weaver Upconversion

Weaver upconversion is implicitly incorporated in the above quadrature-basedtransmitter architectures. It was originally envisaged as a method of SSB generationand was first proposed in 1956 [11] as a method of generating SSB, without therequirement for a narrowband crystal filter. It is an extension of the phasing methodof SSB generation, which suffers from the fact that the remaining unsuppressedimage band appears adjacent to the wanted frequency band. Although, in theory,this image should not exist, imperfect system components mean that it cannotentirely be eliminated. This is a particular problem in a mobile radio environment,as the adjacent channel performance must be very good—hence the need for highlylinear amplification and an alternative method of SSB generation.

The principal advantage of the Weaver method is that the image channel fallswithin the band of the wanted channel and hence the suppression specification isgreatly relaxed. A Weaver method SSB generator is shown in Figure 5.15. It is adirect-conversion architecture, although it can be (and frequently is) used to directlyconvert to an appropriate IF, prior to conventional analogue upconversion to therequired frequency band. A significant advantage of the technique, when used in asoftware defined radio application, is that it allows many aspects of the system to beimplemented in a DSP device, and in particular, those areas which would otherwisebe difficult to realize in analogue hardware (e.g., the generation of the quadraturesignal components, SI1 and SQ1, in Figure 5.15).

The operation of a Weaver generator may be described, with reference to Figure5.15, as follows: The baseband input signal is restricted to a bandwidth, B, with a


Sin

90º 90º

Sout

SI1 SI2 SI3

SQ1 SQ2 SQ3

0t)cos(ω Ct)cos(ω

Ct)sin(ω0t)sin(ω

Figure 5.15 Weaver method SSB generator.

band centre frequency, f0, and a lower limit, fL, as shown in Figure 5.16. The inputband may be considered as a summation of sinusoids:

( ) ( )s t E tin nn

N

n n= +=

∑1

cos ω φ (5.1)

The baseband input signal is mixed with a quadrature oscillator operating athalf of the required modulation bandwidth. Two baseband-frequency quadraturepaths are thus formed where the baseband spectrum in each has been folded on topof itself, occupying half of the original bandwidth. In an SDR implementation, par-ticularly of a digital modulation scheme, these two signals may well result directlyfrom the modulation process, thereby removing the need for the left-hand half ofFigure 5.15.

In either case, the resulting signals are:

( ) ( )[ ] ( )[ ]s t E t E tI nn

N

n n nn

N

n n11

01

0= − + + + += =

∑ ∑cos cosω ω φ ω ω φ (5.2)

and

( ) ( )[ ] ( )[ ]s t E t E tQ nn

N

n n nn

N

n n11

01

0= − − + + + += =

∑ ∑sin sinω ω φ ω ω φ (5.3)

The resulting spectrum appears as shown in Figure 5.17; note the gap betweenthe top of the required baseband spectrum and the bottom of the mixer productsband. This provides a convenient region for the lowpass filter roll-off and will be600 Hz wide for a 300-Hz–3.4-kHz audio input spectrum. The resulting filtered sig-nals will be:

( ) ( )[ ]s t E tn n nn

N

12 01

= − +=

∑ cos ω ω φ (5.4)

and

( ) ( )[ ]s t E tQ n n nn

N

2 01

= − − +=

∑ sin ω ω φ (5.5)

Each path is then upconverted to the final channel frequency by a quadraturelocal oscillator operating at the centre of the channel. This is not what would be


fL L Frequency

Amplitude

f +Bf

B

0

Figure 5.16 Baseband input signal spectrum.

described as the carrier frequency in a conventional filter-based SSB system, how-ever in most modern mobile communications systems, the carrier frequency definesthe centre of the wanted channel and not necessarily the frequency of theupconverting local oscillator(s) (although given the widespread use of quadratureupconversion techniques, the term carrier frequency is now almost synonymouswith the centre of the wanted channel.)

The resulting RF output signals are therefore:

( ) ( )[ ]

( )

s tE

t

Et

In

n

N

c n n

n

n

N

c n

31

0

10

2

2

= + − +

+ − + −

=

=

∑

∑

cos

cos

ω ω ω φ

ω ω ω[ ]φn

(5.6)

and

( ) ( )[ ]

( )

s tE

t

Et

Qn

n

N

c n n

n

n

N

c n

31

0

10

2

2

= + − +

− − + −

=

=

∑

∑

cos

cos

ω ω ω φ

ω ω ω[ ]φn

(5.7)

The two paths are then summed to produce an SSB channel in which the imagefrom the final upconversion process appears in-band and the suppression of whichis mainly governed by the quadrature accuracy of the oscillator and the leakagesinvolved in the RF summing junction:

s s sout I Q= +3 3 (5.8)

Hence

( )[ ]s E tout n c n nn

N

= + − +=

∑ cos ω ω ω φ01

(5.9)


Frequency

Amplitude

f0 B/2 2f B/− 2 2f

2f

2f B/+ 20 00 0

L

Figure 5.17 Signal spectrum at the output of the first balanced modulators.

The two quadrature baseband frequency paths, created by use of the Weavermethod, lend themselves rather neatly to application in a Cartesian loop transmitter[12] or a digital predistortion transmitter, or indeed any quadrature-based transmit-ter architecture (e.g., some forms of the LINC technique, certain sigma-delta tech-niques, and so forth). All of these options are discussed in Chapter 6.

5.3.7 Non-Ideal Performance of High-Speed DACs

Many of the imperfections encountered in a high-speed DAC are analogous to thosealready discussed in Chapter 3, relating to high-speed ADCs. These include INL andDNL errors, finite spurious-free dynamic range, SINAD and signal-to-noise ratios,and bad or missing codes. This section will briefly discuss the additional issues relat-ing to high-speed DACs and their impact upon transmitter performance; it will notduplicate the discussion of Chapter 3 and the reader is referred to that chapter fordetails on some of the other high-speed data converter issues.

5.3.7.1 Distortion Mechanisms Which Depend upon Output Signal Frequency

Many DAC non-linearities are not dependent upon the frequency of the DAC out-put signal. These include INL, DNL, and bad or missing codes. These errors are typ-ically small in a modern converter and should not impact significantly upon theconverter’s spectral properties.

There are three main distortion mechanisms, however, which do depend uponthe output frequency required from the DAC:

1. Amplifier slew rate: Caused by the finite bandwidth/slew rate of the outputamplifier(s);

2. Non-linear capacitance: Occurring within the DAC IC itself;3. Open-loop non-linearities: These begin to manifest themselves as loop gain

rolls off at higher frequencies and hence the effect of feedback reduces.

All three of these mechanisms (along with the other effects discussed next) con-tribute to the reduction in performance experienced with high-speed converters, astheir frequency limit of operation is reached.

5.3.7.2 Step Response of a High-Frequency DAC

Figure 5.18 shows the impact of a step change in the required DAC output voltage,upon the actual voltage appearing at the DAC output. The dashed line shows thedesired ideal output change which the DAC should produce, as a result of a stepchange in the input code (e.g., from half to full scale), while the solid line shows theform of the actual output which will be seen in practice.

Examining the practical DAC response in detail highlights a number of imper-fections. These break down into static errors and dynamic errors. The main staticerror shown in Figure 5.18 is dynamic non-linearity (DNL)—this is the differencebetween the desired steady-state output voltage, for a given input code, and theactual voltage generated by the DAC. There are a number of dynamic errors and


dynamic aspects of the system exhibiting non-ideal behaviour, usually resultingfrom large step changes and/or short update periods:

1. Glitch impulses. These occur at the start of the transition from the previouscode’s output voltage to that of the new code. This typically results in a smallreduction in the DAC’s output voltage at the start of the transition from alower to a higher output voltage (and conversely for a higher-to-lowervoltage transition).

2. Non-linear slewing. The transition from the previous output voltage level tothe new output voltage level will not occur instantaneously, nor will it(necessarily) occur linearly. Clearly the impact of this effect will increasewith increasing sample rate and it is one of the reasons behind the lowerperformance seen with most high-speed converters, as their sample rate limitis approached and reached.

3. Overshoot and ringing. As in any system operating at high frequencies with(unavoidable) reactive elements, an amount of overshoot and/or ringing isinevitable. Again this will become more pronounced, in terms of its overalleffect on the output spectrum, as the converter’s sample rate limit isapproached and reached.

4. Clock or data feedthrough. This effect is typically most evident after theoutput voltage has begun to settle and can be seen as a small glitch in thesteady-state response of the DAC. It can result from many causes, bothinternal to the DAC and also in the external circuitry. Clearly, care shouldbe exercised in the design of the latter, to ensure that such glitches areminimised or eliminated.

5.3.8 Linear Transmitter Utilising an RF DAC

The concept of using a DAC which that operates at the required final carrier fre-quency, is clearly attractive for both handset and base-station applications. In theformer case, power consumption is likely to be a major issue for some time to come;


Settling time

Time

DA

Cou

tput

volta

ge

Overshootand ringing

Clock or datafeedthrough

Glitchimpulse

Nonlinearslewing

Ideal DACoutputresponse

DNLerror

Figure 5.18 Response of a practical high-speed DAC to a step change in the required outputvoltage.

however, the latter area is likely to be an early adopter of this type of system, as andwhen it becomes commercially viable.

RF DACs are now beginning to be discussed, with low-resolution, high-speedconventional converters appearing in some direct-to-carrier (RF) applications andhigher speed converters appearing in the literature (e.g., [13]). This section discussesa promising alternative to the conventional type of high-speed DAC for RF applica-tions. It is not yet a commercial product (as of the time of this writing), but doesoffer a promising route to achieving carrier-frequency synthesis of an RF waveform.

5.3.8.1 Drawbacks of Existing DACs

The performance of existing high-speed DACs is limited by distortions present at thedata switching transitions (Figure 5.19) and these distortions impact upon the fre-quency-domain performance of the device. The three main causes of this are [14]:

1. Intersymbol interference (ISI);2. Imperfect timing synchronization;3. Clock jitter.

It is possible to solve the first problem (ISI) by using a return-to-zero (RZ) DACarchitecture. This type of DAC effectively removes the sample-to-sample memoryof the converter, thereby ensuring that the switching data transients are moreclosely related to the input data stream. It does, however, require the DAC to pro-duce larger steps for the same output energy and this increases its sensitivity to clockjitter [15, 16].

5.3.8.2 Structure and Operation of an RF DAC

The concept of utilising a sinusoidally shaped pulse as the output for each DAC codehas been proposed, in order to solve the ISI problem mentioned earlier, as well as toalleviate the jitter problem [17]. This mechanism solves the former problem, sincethe waveform chosen is an RZ pulse, with the sinusoidal output and the DAC sam-pling clock being aligned, such that the DAC is switched in the regions of the sinu-soidal pulse where it falls to zero.

If the sinewave used to create the pulse is perfectly locked to the data clock,the sensitivity of the resulting system to clock jitter is substantially removed. Thisoccurs since the sinewave pulse has zero value and zero gradient at the switchingpoints.

The RF DAC concept, shown in Figure 5.20, builds on this idea by utilising mul-tiple oscillatory periods (or pulses) within each DAC output code. This idea retains


D/ADigitalinput

Ampl.

Time

Ampl.

Timet t t /f+1 s

AAnalogueoutput

Figure 5.19 Response of a conventional DAC to an impulse, showing switching-edge distortion.

the above properties with respect to ISI and jitter immunity, but adds the advantagethat upconversion is effectively performed at the same time, thereby creating an out-put at a desired RF carrier frequency. The RF DAC can therefore be thought of asequivalent to a conventional DAC followed by a mixer and LO-based upconverter.

An alternative approach, utilising a conventional DAC, is to employ one of thehigher Nyquist zones at the output of the DAC, in place of the first Nyquist zone.This can be achieved simply by placing a bandpass filter, designed for the requiredcentre frequency, after the DAC, thereby isolating the desired Nyquist zone, con-tained in the DAC output. This approach does, however, have the significant disad-vantage that the sin(x)/x response of the DAC means that the output level of thishigher Nyquist zone signal, will be significantly below that of the main lobe andalso significantly lower than an equivalent output from the RF DAC discussed here.

The RF DAC employs a harmonic of the DAC clock as the oscillatory wave-form, used to generate the DAC output pulses (fOSC nfS). Examples of the resultingform of the DAC output pulse are shown in Figure 5.21, for n = 2 and n = 3. It can beseen from this figure that DAC switching can still occur in regions of the waveformwhere it drops to zero and has a gradient of zero. It therefore has the same ISI andjitter advantages described above for a single sinusoidal pulse.

Comparison of Figures 5.21(a) and 5.21(b) shows that it is possible to centre theDAC’s response around any desired frequency, simply by changing the oscillatorfrequency, fOSC. It must, of course, be ensured that the resulting sample rate is anappropriate compromise between sampling the desired signal bandwidth (as a mini-mum) and not over-designing the system with regard to sample rate, as this is expen-sive in both cost and power consumed.

The key advantages of the RF DAC, over the more conventional DAC-plus-mixer approach are:

1. The non–return-to-zero DACs used in a conventional DAC-plus-mixerarchitecture, result in them being prone to the ISI and clock-jitter problemsdiscussed earlier.

2. The conventional architecture is also prone to phase noise on theupconversion local oscillator. Although a similar oscillatory waveform isrequired for the RF DAC, the resultant system is still capable of betteroverall performance [14, 18].

3. An RF DAC offers power consumption, hardware complexity, and noisebudget savings, as it does not require local oscillator, mixer, or additionalfilter components and the current-to-voltage transformations required todrive such devices.


D/ADigitalinput

RF DAC

Ampl.

Time

Ampl.

Timet t t /f+1 s

AAnalogueoutput

Figure 5.20 Basic structure of an RF DAC [14].

The main drawback is that the DAC needs to switch synchronously with theminima in the oscillatory pulse waveform; some form of phase-locked loop is there-fore required. If this is not provided or performs poorly, the RF DAC will still oper-ate and create the desired RF output signal. It will, however, suffer from both clockjitter and ISI sensitivity, as would a conventional DAC.

5.3.8.3 Transmitter Architecture Using an RF DAC

The form of transmitter architecture required to exploit the benefits of an RF DAC isvery simple, as shown in Figure 5.22. Digital quadrature upconversion is performedto generate a real output signal (to eliminate the requirement to use two RF DACs),with this signal being provided at a low digital IF. The RF DAC then performs boththe digital-to-analogue conversion and upconversion functions of a conventionaltransmitter and all that remains in the analogue domain is a bandpass filter and aPA, both operating at the required output frequency.

If it is desired to keep DAC sample rates to an absolute minimum, which may beadvantageous in narrowband and/or single-carrier applications, the dual-DACarchitecture of Figure 5.23 may be used. In this case, the RF DACs form an integralpart of the quadrature upconversion process and therefore operate with digital base-band input signals. Their required sample rate is then, at worst, half that of the DAC


Timet t+1/fs

A

Timet

(a)

(b)

(c)

t+1/fs

A

Timet t /f+1 s

A

Figure 5.21 Example of using multiple oscillatory pulses for each DAC output code in order tocreate an RF DAC: (a) fOSC = 2fS, (b) fOSC = 3fS, and (c) fOSC = 2fS.

required in Figure 5.22, and typically much lower. This saves both cost and powerin the DAC, although as two are now required, whether an overall saving wouldresult is not necessarily clear.

5.3.9 Use of Frequency Multiplication in a Linear Upconverter

Frequency multiplication is a very low-cost upconversion technique and is in wide-spread use in very low-cost consumer handheld transmitters. It is traditionally usedonly with constant-envelope modulation formats (typically analogue FM) and isindeed, by its very nature, a highly non-linear technique. It has been suggested in[19], however, that the technique is capable of linearisation, to a limited degree, bymeans of digital predistortion—it is therefore potentially appropriate for use in lin-ear SDR applications, although at present the cost of the digital processing requiredfor the predistorter will far outweigh the lower cost of the upconverter. In thefuture, as the cost of the required digital processing reduces, it may become a worth-while technique in low-cost applications. It may also be an appropriate way ofrealising a quasi-linear transmitter in very high frequency (millimeter-wave) appli-cations, where frequency multiplication is the most sensible, or only, option forachieving upconversion.


90º

0ºIn RF

outputDSP

Digitalquadratureupconverter

Bandpassfilter

RF amplifierNCO

Digitalprocessing

RF outputDAC

D/A

Figure 5.22 Linear transmitter architecture employing an RF DAC.

90º

0ºIn RF

outputDSP

Digitalquadratureupconverter

Bandpassfilter

RF amplifierNCO

Digitalprocessing

RF outputDAC

RF outputDAC

D/A

D/A

Figure 5.23 Linear transmitter architecture employing dual RF DACs.

The basic format of an odd-order frequency multiplier is shown in Figure 5.24.The modulated frequency source, Vs, (at a frequency f0) is fed to a pair of anti-paral-lel diodes (in this case, as a series element) via a matching network. The appropriatenth harmonic is selected by the output matching network, which is resonant at nf0.The resulting harmonic is then fed to the load (e.g., an antenna). Detailed designinformation on frequency multipliers may be found in [20].

As an example, the schematic for a Schottky diode based 820-MHz input,2.46-GHz output frequency tripler, is shown in Figure 5.25. It utilises the AgilentHSMS-2852 diodes and these appear as shunt elements, matched by two discretematching networks.

The reported results for this network [19], when using predistortion, indicatethat an improvement from 4 dBc to 34 dBc is possible for a single-channel IS-95CDMA signal, with an EVM improvement from close to 100% to around 7.3%.While these are clearly not spectacular results from an absolute performance per-spective, they may well be adequate in many fixed or quasi-fixed radio applications(e.g., satellite systems). This is therefore potentially an interesting technique in someapplication areas.

5.4 Constant-Envelope Upconversion Architectures

The previous section focused on generic upconverter/transmitter architectures, suit-able for any modulation format (within a given bandwidth capability). This sectionwill concentrate on transmitter architectures which are suitable only for con-stant-envelope, phase (or frequency) modulated transmitters, or, perhaps moreimportantly, for use as part of an envelope elimination and restoration (EE&R)transmitter (discussed in Chapter 6). In the latter case, the transmitter architecturesdescribed here would form the phase-modulation part of the EE&R transmitter,with a separate amplitude modulation system modulating the PA drain supply (e.g.,using a pulse-width modulator).

5.4.1 PLL-Based Reference or Divider Modulated Transmitter

The first architecture, shown in Figure 5.26, is that of a standard, modulated-PLLtransmitter. This form of transmitter utilises a conventional PLL-based synthesiser


Z0

f0 nf 0 ZL

Z0

Vs

Figure 5.24 Format of a basic odd-order frequency multiplier.

and modulates this, either by directly modulating the frequency reference (if this isformed from a VC-TCXO, for example) or by dithering the divider ratio within thefrequency divider.

5.4.2 PLL-Based Directly-Modulated VCO Transmitter

A modified form of the technique illustrated in Figure 5.26 is shown in Figure 5.27,where the modulation process in this case utilises a direct imposition of the inputdata upon the VCO within the PLL [21]. Its method of operation is as follows: Ini-tially, the PLL is operated with the data modulation switch closed, in order to allowthe loop to lock and the VCO to be pulled on to the correct carrier frequency. Thedata switch is then opened and the transmit data applied directly to the VCO. Thisdata then directly modulates the control voltage to the VCO, thereby modulating itsfrequency.

The primary advantage of this technique is that it is simple, since the VCO per-forms both modulation and upconversion functions. It can therefore be fabricatedto have a very low power consumption, in an integrated circuit implementation.

It does, however, have the significant disadvantage that the VCO is operatingopen loop, when being modulated by the data signal, and hence is liable to drift offthe desired carrier frequency. It will also suffer from injection locking, whereby thehigh-power output of the PA pulls (and hence modulates) the VCO. Excellent

5.4 Constant-Envelope Upconversion Architectures 211

ZLVs

C1 10.5 pF=

L1= 82 nH L1 5.6nH=

C1 9.0 pF=

HSMS−2852

Figure 5.25 Circuit diagram of a Schottky diode based frequency tripler.

÷N

Chargepump

Phase/freq.detector

VCO RF PA

Lowpassfilter

Divider

Frequencyreference

Modulationinput

Tx data/modulationinput options

Ditherinput

Figure 5.26 A PLL-based reference or divider-modulated transmitter.

screening is required between the PA stage(s) and the VCO in order to overcome thisproblem.

5.4.3 PLL-Based Input Reference Modulated Transmitter

The PLL frequency reference can be generated from a local oscillator, upon whichthe desired transmit data has been imposed by a DSP and quadrature upconverter[22]. This type of architecture is shown in Figure 5.28. There are a number of possi-ble methods of implementing the baseband/DSP part of the system, and hence only ageneric DSP block is shown in Figure 5.28. This block is therefore assumed to incor-porate a Hilbert transform filter, DACs, and reconstruction filtering (if required, ineach case, depending upon the implementation chosen). A DSP device is ideallysuited to the implementation of a Hilbert transform filter and hence is veryappropriate for use in this application.

The operation of this transmitter is similar to that of Figure 5.26, with theexception that in this case, the reference for the PLL is generated by upconvertingI/Q data signals (generated by the DSP), using a local oscillator. The other key differ-ence is that the frequency divider in Figure 5.26 has been replaced by a mixer and a


÷N

Chargepump

Phase/freq.detector

VCO RF PA

Lowpassfilter

Divider

Frequencyreference

Tx datainput

Figure 5.27 A PLL-based directly modulated VCO transmitter.

Chargepump

Phase/freq.detector

VCO RF PA

LowpassFilter

Mixer

LowpassFilter

Second localoscillator

90º

0ºIn

First localoscillator

DSP

D/A

D/Aconverter

D/A

D/Aconverter

Figure 5.28 A PLL-based input reference modulated transmitter.

second local oscillator. This relaxes the small synthesis step size requirement, whichwould otherwise be necessary in the first local oscillator, as this oscillator can pro-vide some or all of the required tuning.

This architecture is, again, simple and amenable to integration in a low-powerdevice. It does, however, require two local oscillators, in addition to the VCO, andpulling of the second LO and/or the VCO is still an issue (again, requiring good PAto LO/VCO isolation).

5.4.4 Use of a Direct-Digital Synthesizer to Modulate a PLL-Based Transmitter

An alternative modification to the architecture that is shown in Figure 5.26 isshown in Figure 5.29; in this case, a direct-digital synthesiser (DDS) is used to formthe reference signal and this is fed by a combination of the channel frequency infor-mation, for the given set of channels on which the transmitter can operate, and thedesired transmit data. In this way, the reference frequency to the PLL is supplied asan already-modulated signal and the PLL effectively upconverts this signal to thedesired carrier frequency.

The fundamental reference for this system is now the clock oscillator (notshown in Figure 5.29), which clocks the DDS (and typically also the DAC). Thisovercomes the frequency drift problems associated with the architecture of Figure5.27, although whether it has any advantage, in terms of output noise, over thearchitectures of Figures 5.26 and 5.28, will depend upon the particular implementa-tion in each case. It also has significant disadvantages, at present, due to the fine fre-quency resolution which would be required in most applications and the trade-offbetween switching time and spurious response for the DDS device. The former issueis similar to that discussed in Section 5.4.3 and could be overcome by the samemechanism (i.e., use of a mixer and second LO in place of the frequency divider).

5.4.5 A PLL-Based Transmitter Utilising Modulated Fractional-N Synthesis

If a fractional-N synthesizer is used in place of a conventional synthesizer, a trans-mitter of the form shown in Figure 5.30 can be created [23]. In this transmitter, thedivide ratio is modulated by the desired transmit data and frequency modulation isthereby achieved. This stems from the fact that the output frequency for a PLLsynthesiser is given by:

5.4 Constant-Envelope Upconversion Architectures 213

÷N

Chargepump

Phase/freq.detector

VCO RF PA

Lowpassfilter

Divider

Sinusoid LUT(e.g., stored in ROM)

Tx datainput

Requiredchannelfrequency data

PLLreference

D/A

Figure 5.29 A PLL-based transmitter in which the input reference is generated by a DDS.

F NFout ref= (5.10)

If the divide ratio, N, is now modulated, (5.10) becomes:

( ) ( ) F t N D t Fout ref= (5.11)

where D(t) is the data modulation (following filtering and so forth). The frequencyof the output signal has therefore been modulated by the data waveform.

The operation of the transmitter is as follows. The transmit data is first filtered,typically by a Gaussian FIR digital filter, before summation with the division ratiovalue required to select the desired channel (i.e., the carrier frequency offset value).The resulting signal forms the input to the delta-sigma modulator, the output ofwhich is used to control the divide ratio of the PLL. It is this variation of the divisionratio which modulates the carrier and thereby provides the desired, modulatedoutput signal.

The use of a delta-sigma modulator allows the quantisation noise, generated inthe modulation process, to be moved to a frequency range much higher than that ofthe baseband data spectrum. This noise can therefore be filtered by the naturallylowpass characteristic of the PLL.

A key advantage of this architecture, over those already achieved using theinput-reference modulation techniques discussed earlier, is that higher data rates canbe transmitted without requiring the reference frequency to be lowered. The use of adelta-sigma modulator, and the lack of any requirement for mixers, allows thisarchitecture to be both simple and capable of implementation in a low-powerintegrated device.


÷ N/(N 1)+

Chargepump

Phase/freq.detector

VCO RF PA

Lowpassfilter

Divider

Tx datainput

Required channelfrequency data

Frequencyreference

∆−Σmodulator

Tx datafilter

Figure 5.30 A constant-envelope transmitter employing a fractional-N-based upconversion system.

One disadvantage of this architecture lies in its requirement for the PLL loopbandwidth to be greater than the modulation bandwidth. This drawback may,however, be overcome by utilising the method proposed in [21].

5.5 Broadband Quadrature Techniques

A broadband quadrature network is an important enabling technology in a numberof areas within a software defined radio system. There are a range of applicationsfor quadrature networks within a software defined radio, each with different char-acteristic requirements. These include:

1. Quadrature upconverter. In this application, it is the local oscillator whichmust be generated in quadrature and the broadband requirement comesfrom the coverage range desired from the system; the instantaneousbandwidth required of the quadrature generation system is negligible. In thiscase, any of the techniques described below may be applied, including themore traditional doubler/divider (digital) techniques for LO quadraturegeneration.

Quadrature errors manifest themselves as an imperfect image suppression,with this occurring in-band in the case of Weaver [11] upconversion (seeSection 5.3.6). Note that in the case of a multi-carrier transmitter (e.g., in abase station), in-band refers to the instantaneous transmit bandwidth of thesystem. This can cause unwanted products to appear in adjacent channels, aswas shown in Figure 5.4. In addition, these errors are likely to result in anincreased error vector magnitude from the system, unless this parameter isalready dominated by local oscillator phase noise or PA non-linearity. In thecase of Figure 5.4, channels 1 and 4 would suffer most severely from thisproblem, since these have in-band image signals falling directly on top ofthem. Channel 2 should exhibit a much better EVM performance, taken inisolation.

2. Quadrature downconverter. Similarly, in this application, it is the localoscillator which must be generated in quadrature and the broadbandrequirement again comes from the coverage range desired from the system;the instantaneous bandwidth required being negligible. Any of the followingtechniques may be applied, including the more traditional doubler/divider(digital) techniques for LO quadrature generation.Quadrature errors can manifest themselves, here, as an imperfect imagesuppression (as above) when the downconverter is used in the feedback loopof a linearised transmitter (e.g., Cartesian loop). They can also result in animperfect receiver image suppression, when applied to a receive quadraturedownconverter. In either case, this is likely to result in a degradation of theerror vector magnitude performance of the system, as was the case with theupconverter discussed earlier.

3. Image-reject mixer. The use of image-reject mixing is described in Chapter 4and hence the treatment here will be brief. Broadband quadrature is requiredin two parts of an image-reject mixer: in the LO path and at RF. In the

5.5 Broadband Quadrature Techniques 215

former case, the same issues and solutions apply as described above forquadrature upconverters and downconverters. In the latter case, a truebroadband quadrature is required (i.e., one with a relatively largeinstantaneous bandwidth). This reduces the number of techniques availablefor its realization, largely to those based on all-pass (or polyphase) filteringand coupler-based techniques (e.g., a Lange coupler). Quadrature errors willmanifest themselves as a reduction in the available image rejection.

5.5.1 Introduction to Quadrature Techniques

There exists a wide range of narrowband methods for generating quadrature sig-nals. Such techniques include various forms of quadrature hybrid (lumped-element,branch-line, ring, and transformer), together with narrowband filter-based tech-niques. These techniques are typically capable of acceptable quadrature behaviour(for example, <0.5 dB of amplitude imbalance and <3° of phase imbalance) over abandwidth of perhaps 20% of their centre frequency, at UHF and above. Althoughthis performance is adequate for single-band applications, it is not acceptable in amulti-mode, multi-band software defined radio, where an octave or more of cover-age may well be required.

The techniques described in this section present a range of options for quadra-ture generation, both for CW signals, such as a local oscillator and also for linearbroadband signals, such as one or more modulated carriers. These latter techniquesare appropriate for use on any signal and will preserve the signal’s fidelity. Theoptions presented also cover a range of implementation methodologies, both dis-crete and integrated, as well as a range of applicable frequency bands. The appropri-ate areas of application and implementation methodology will be highlighted ineach case.

In addition to these options, there are a wide range of alternatives for the broad-band generation of quadrature local oscillator signals, directly, largely based onintegrated circuit implementations. These methods encompass purely analogue,quasi-digital and purely digital techniques (e.g., direct-digital synthesis). This is acontinuously emerging area and further examination of the literature should beundertaken, particularly in the case of an integrated design, prior to selecting asolution.

5.5.2 Active All-Pass Filter

A lowpass or highpass filter will produce a 90° phase lag (or lead) in its stop-band,with a reasonable phase error (say, ~3°) being achieved at a frequency of perhaps 25times (or 1/25th in the case of highpass) its 3-dB bandwidth. At this point, the atten-uation will be in excess of 27 dB, making it a very lossy circuit. A better alternative isto use a simple all-pass network.

Figure 5.31 shows an active all-pass filter whose phase lag is given by:

( ) ( )θ ω ω= − −2 1tan RC (5.12)

It thus produces a 90° phase-shift at:


ω = RC (5.13)

with a broadband unity-gain amplitude response. It may therefore form the heart ofa very simple quadrature network, albeit with a narrow instantaneous bandwidth.

The key advantages of this technique are:

• Simplicity of implementation;• Broadband flat gain response;• Can be made tuneable by varying R or C.

However, it does suffer from some obvious drawbacks:

• The bandwidth of its 90º phase-lag may well not be wide enough in many soft-ware defined radio applications.

• High-frequency RF use may prove difficult, due to gain-bandwidth limita-tions of its op-amp structure (although the bandwidth capabilities of op-ampsare continuously improving).

These limitations have led to a range of alternative options being developed.

5.5.3 Use of Highpass and Lowpass Filters

It is possible to exploit the properties of low and highpass filters in order to obtain abroadband quadrature generator, while still preserving the fidelity of the originalwaveform. The system will work over a wide operational bandwidth, but with onlya modest instantaneous bandwidth (dependent upon the degree of amplitude andphase flatness required over the signal bandwidth).

The system concept may be explained with reference to the highpass andlowpass filter phase response characteristics shown in Figure 5.32. It can be seenfrom these responses that both filters produce a 45° phase shift at an angular fre-quency given by:

ω = RC (5.14)

In the case of the lowpass filter, this is a phase lag and in the case of thehighpass, it is a lead. The phase difference, therefore, between the outputs from two


Op-Amp

R1

R1

R

C

In Out

Figure 5.31 Active all-pass phase lag circuit.

identical filters, one highpass and the other lowpass, when fed with the same input(CW) signal, will be 90º.

Figure 5.33 shows how a combination of a lowpass and a highpass section maybe employed with a broadband 0º splitter (e.g., resistive) to produce a narrowband90° splitter. It will generate quadrature at an angular frequency given by:

ω = RC (5.15)

It is evident that the instantaneous and operational bandwidths of this system areidentical and modest. Essentially, precise quadrature is only produced at the angularfrequency given by (5.15), although an acceptable quadrature will be obtained over amodest percentage bandwidth. The operational bandwidth is also modest, since thesystem is not tunable, in the configuration shown in Figure 5.33.

This system can be made tunable to cover a wide frequency range (perhaps onedecade), although the instantaneous bandwidth will remain modest. The requiredarrangement is shown in Figure 5.34, with the diodes shown being of the PIN type(RF, and not baseband, operation is assumed for this circuit). It unrealistically


Normalised Frequency (Hz)

Phas

eshi

ft (

degr

ees)

10

10

20

30

40

50

60

70

80

90

(b)

0.01 1−90

−80

−70

−60

−50

−40

−30

−20

−10

0

Normalised Frequency (Hz)

Phas

eshi

ft (

degr

ees)

0.1 10

(a)

100

0.01 0.1 10 100

Figure 5.32 Normalised (a) lowpass and (b) highpass filter responses for a first-order R-C filter.

assumes perfect components and a linear resistance versus applied voltage charac-teristic for the PIN diodes.

The arrangement shown in Figure 5.34 does solve the operational bandwidthproblem, but not that of instantaneous bandwidth. The main instantaneous band-width problem arises due to the difference in the amplitude vectors at a given fre-quency offset from the design centre frequency; one vector will suffer attenuationgreater than 3 dB and the other less. There will thus be an undesired vector error thatcannot easily be compensated (without adding additional, unwanted phase shift).

It is possible to automate the tuning process shown in Figure 5.34, and thisovercomes the unrealistic expectation that the PIN diodes have a linear resistanceversus applied voltage characteristic. The accuracy of quadrature is now dependentupon the phase detector performance, and in particular its DC-offset level and vari-ation with frequency and/or amplitude, as appropriate (static error could easily besubtracted).

This technique, shown in Figure 5.35, results in a broadband 90° splitter witha narrow instantaneous bandwidth. This is ideal for a software defined radio


R

C

In

Out1( 45º)−

R

C

Out2( 45º)+

Figure 5.33 Narrowband 90º splitter.

C

In

Out1( 45º)−

C

Out2( 45º)+

Rbias

0-12V

Rbias/2

Rbias/2

Figure 5.34 Tuneable narrowband 90º splitter (indicative circuit diagram).

application, particularly on the transmit side (within the upconverter), since only asingle channel is typically transmitted at any given point in time. This channel couldappear anywhere over a very broad bandwidth and hence a broad coverage range isrequired, however a narrow instantaneous bandwidth should be adequate for mostsingle-carrier signals.

Its principle of operation is very straightforward. The basic phase splitter is thesame as that described earlier; what has been added here is a control mechanism toensure that the splitter automatically adjusts itself to maintain quadrature around thewanted channel, wherever that channel may be within its operational bandwidth.

The quadrature outputs from the system are split to allow them to feed a broad-band phase detector. It is the quadrature accuracy of this detector which now deter-mines the overall phase accuracy of the quadrature resulting from the splitter. Thephase detector, assumed to be a mixer or multiplier-based detector here, will onlyprovide a zero voltage output when phase quadrature is maintained between itsinputs. The output from this detector can therefore be used to supply an integrator,configured such that its output, when suitably amplified, electrically adjusts the PINdiodes in the splitter to return the system to quadrature.

Note that Figure 5.35 is somewhat conceptual in nature and a more complexsystem would probably be required in most practical situations. It does, however,serve to illustrate the concept and one form of its practical implementation.

The main drawback with the technique is that control is not provided for theamplitude balance (although this could be added in the form of an AGC on one ofthe outputs). Without this, use of the splitter would provide a poor level of imagerejection when deployed in an upconverter, unless some form of limiting amplifierwas provided on each of the quadrature outputs.

A practical version of this circuit has been constructed (by the author) and gaveacceptable performance across a decade frequency range from 100 MHz to 1 GHz(operational bandwidth, not instantaneous bandwidth).


C

In

Out1( 45º)−

C

Out2( 45º)+

Rbias

12V

Rbias/2

Rbias/2

Phasedetector dt

Figure 5.35 Automatically adjusted 90° splitter (indicative circuit diagram).

5.5.4 Polyphase Filtering

Polyphase filtering was mentioned in Chapter 4, in connection with image-reject(IR) mixing. For that application, an active polyphase filter was shown to providethe relatively broadband quadrature, which may be required in situations where alow IF IR mixer is desired. In this section, the polyphase filter to be described [24] isa passive filter, consisting of a series of single-pole R-C sections. These R-C sectionssynthesize what is in essence a Hilbert filter. A single-section (first-order) polyphasefilter is shown in Figure 5.36, based around a differential input and output configu-ration. Since almost all known polyphase filters are used within integrated circuits,they tend to be designed to operate differentially.

A second-order polyphase filter is shown in Figure 5.37, highlighting how sec-tions may be cascaded to obtain wider band operation (for a given quadrature accu-racy) and also indicating which outputs form the differential quadrature signals.Many sections may be cascaded in order to generate very wideband quadraturenetworks, if required.

The main advantage of a second-order polyphase filter over the classicalRC-CR (highpass, lowpass) quadrature generator lies in its good broadband quad-rature accuracy and consequent insensitivity to absolute variations of the R and Cvalues. It is therefore ideally suited to integrated applications, since absolute com-ponent value accuracy is poor in that type of system, although relative accuracy isgenerally very good.

The practical use of a polyphase filter within an image-reject mixer arrange-ment is described in [25]. In this case, the polyphase filter is used as the broadband


R

C

In ( ve)−

Out190V' ∠ −

Out20V' ∠

Out390V' ∠

Out4V' 180∠

In ( ve)+

R

C

R

C

R

C

Differentialinput

Figure 5.36 Single-stage polyphase filter architecture.

90° combiner and not as the local-oscillator 90° split. The results reported from thisarchitecture indicate that an image-rejection of over 60 dB is achievable, over anoutput IF range from 4 to 25 MHz, based upon a fifth-order polyphase filter.

5.5.5 Broadband Passive All-Pass Networks

An alternative broadband, filter-based, quadrature-splitting option involves the useof passive, LC all-pass sections, as shown in Figure 5.38. This has the advantage of abroad instantaneous bandwidth, with a defined phase ripple (error), which dependsupon the order of the filter, n. It can also be implemented successfully as a discretedesign, generally with realistic component values, although the range of valuesrequired for a broadband, low-ripple design, can sometimes be an issue.

As an example, consider a 90° design between 200 MHz and 2.294 GHz (ωu/ωl =11.47). For n = 6, the ripple would be ±0.1°, yielding two three-element networks.The design centre frequency is given by:

f f fu l0 677 35= = . MHz (5.16)

The pole locations for the N and P networks are then given in Table 5.1 (seeAppendix A and [26]).

Finally, the inductor and capacitor values may be found from:


R1

C1

In ( ve)−

Out1-90V' ∠

I ( ve)+out

Out20V' ∠

Q ( ve)+out

Out390V' ∠

I ( ve)−out

Out4180V' ∠

Q ( ve)−out

In ( ve)+

R1

C1

R1

C1

R1

C1

Differentialinput

R2

C2

R2

C2

R2

C2

R2

C2

Figure 5.37 Second-order polyphase filter, showing quadrature differential output connections.

LR

CR

=

=

2

2

0

0

α

α

and (5.17)

where α0 are the pole values in Table 5.1 and R is the terminating impedance for thenetworks (assumed identical in all cases).

Utilising (5.15), the values given in Table 5.2 may be derived, for a 50Ω system(R = 50Ω).

The resulting circuit is shown in Figure 5.39 (note that exact values are shown).These values could potentially be improved (in terms of their practicality) by

reducing the system impedance. This is due to the fact that R is a multiplier to theinductor values and a divisor for the capacitor values. In other words, the higher thevalue of R, the greater the relative spread between inductor and capacitor valuesand hence the greater the chances of parasitic capacitances within the inductorsinfluencing or swamping the intended capacitance values. As an example, the valuesfor a 25-Ω system are shown in Table 5.3. The maximum inductor to capacitorvalue ratio (nanohenries to picofarads, respectively) is now less than 20–in the 50-Ωexample it was around 80.


C C C R

C C C R

Vs

L L L

L L LN-network

P-network

R

Figure 5.38 Passive all-pass filter sections used in a broadband 90° splitter.

Table 5.1 N and P Pole Values for theBroadband Phase-Shift Design

P-Network N-Network

4.438 × 1010 1.295 × 1010

16.035 × 109 3.001 × 109

1.399 × 109 0.408 × 109

The impedance of the system could be restored to 50Ω at the input and outputby means of transformers.

The advantages of the technique may be summarised as follows:

• Broad operational bandwidths are possible (one decade or greater).• Low phase-ripple (0.1º over the full band; possibly much less over the required

instantaneous bandwidth).

The disadvantages of the technique may be summarised as follows:

• Wide range of component values for a 50-Ω system, hence the potential forparasitic effects in some components to swamp the value of others;


Table 5.2 N and P Component Values for the BroadbandPhase-Shift Design (50-Ω System)

P-Network N-Network2.25 nH 0.9 pF 7.72 nH 3.1 pF

16.6 nH 6.6 pF 33.3 nH 13.3 pF

71.5 nH 28.6 pF 245.1 nH 98 pF

3.1 pF 13.3 pF 98 pF 50Ω

0.9 pF 6.6 pF 28.6 pF 50Ω

Vs

7.72 nH 33.3 nH 245.1 nH

2.25 nH 16.6 nH 71.5 nH

N-network

P-network

50Ω

Figure 5.39 Circuit for the 200-MHz to 2.3-GHz broadband phase-shift network with 0.1° ofpassband ripple.

Table 5.3 N and P Component Values for the BroadbandPhase-Shift Design (25-Ω System)

P-Network N-Network1.13 nH 1.80 pF 3.86 nH 6.18 pF

8.29 nH 13.26 pF 16.66 nH 26.66 pF

35.74 nH 57.18 pF 122.6 nH 196.1 pF

• Effect of component value errors on amplitude and phase ripple can be anissue.

Note that accepting a greater phase ripple and/or a reduced operational band-width will reduce the complexity of the system and the component tolerancesrequired. A reasonable circuit analysis package will allow the effect of using realcomponent values (as opposed to the exact values shown earlier) to be assessed.

5.5.6 Multi-Zero Networks

This type of passive splitter network has been proposed in the literature [27] and hasbeen demonstrated to have a bandwidth in excess of 70% of its centre frequency,while maintaining a good amplitude and phase balance (0.3 dB and 1°, respec-tively). The basic concept is shown in Figure 5.40.

The multi-zero network itself operates in a number of bands, with sharp nulls inbetween (see Figure 5.41). Within these bands, there exists a portion (at the centre ineach case) where both the amplitude and phase ripples are acceptably small. In thecase of the output phase ripple, this is based on an average value of +90° or 90°,depending upon the band. Within a band, this region of acceptable performance canbe around 70% of the centre frequency of that band.

Note that it may be possible to achieve a pseudo-broadband performance bycareful placement of the bands. For example, one band could be centred around 900MHz, covering, say, 800 MHz to 1 GHz (and above), with a second band centredaround 2.7 GHz, covering, say, 2.4 GHz to 3 GHz. This approach may result in theswapping of the I and Q channels between the two areas of spectrum (see bands 1and 2 in Figure 5.41), and this must be accommodated elsewhere in the design (e.g.,in the baseband firmware or software).

5.5.7 Tunable Broadband Phase Splitter

This technique [28] is an extension of the multi-zero network discussed earlier, toincorporate tuning of the band within which quadrature is achieved over a range offrequencies between 1 and 2 GHz. To achieve this, the multi-zero network in Figure5.40 is replaced by an open-circuit half-wavelength stub. The electrical length ofthis stub can then be varied by tuning the varactor diode located at its open-circuitend, as shown in Figure 5.42.


Multi-zeronetwork

τ

In-phasesplitter

Delay line

RF input

RF Output 1

RF Output 2

Figure 5.40 Quadrature splitter employing multi-zero techniques.

The original multi-zero network contained a number of short-circuited quar-ter-wavelength stubs, which formed a comb filter. The Q of the comb filter, formedby the single half-wave stub shown in Figure 5.42, is now determined largely by theseries resistance of the varactor diode, and the finite (non-zero) value of this resis-tance, for a practical varactor, serves to increase the bandwidth of the system.

The operation of the system is similar to that of the multi-zero technique dis-cussed earlier. The input signal is split by a Wilkinson power divider, with one out-put feeding a phase-shift path (formed from the stub-based comb filter as discussedearlier) and the other feeding a delay path. The delay path is necessary to compen-sate for the finite delay of the phase-shift path, thereby ensuring a broadbandresponse. The delay path also contains a variable attenuator, formed using a PINdiode, to tune the gain balance of the splitter and thereby ensure that a close gain tol-erance is achieved, between the two outputs of the quadrature splitter.


Out

put

gain

diffe

renc

e(d

B) 0

−10

−20

−30

−40

−50

150

90

30

−30

−90

−1500 1 2 3 4 5 6

Out

put

pha

sedi

ffere

nce

(deg

)

Frequency units

Band 2Band 2Band 1 Band 3

Figure 5.41 Theoretical performance of a quadrature splitter based around a multi-zero network.(From: [27]. © 2001 IEE. Reprinted with permission.)

τ

Varactor diode

Half-wave stub

Attenuator

PIN diodeattenuator

Delay path

WilkinsondividerInput

Phase-shiftpath output

Delay pathoutput

Figure 5.42 Outline of a tuneable broadband quadrature phase splitter. (From: [28]. © 2002 IEE.Reprinted with permission.)

The results reported in [28] indicate that if a static gain and phase balance of upto +/−5° and +/−2 dB can be tolerated, then instantaneous bandwidths of between16% and 32% of centre frequency (1.5 GHz in this example) could be achieved.Bandwidth in this case, was defined as the frequency range over which a phase errorof +/−3° and a gain error of +/−0.3 dB could be achieved, and this was based arounda number of fixed states for the delay and phase paths.

5.5.8 Lange Coupler

A Lange coupler [29], shown in Figure 5.43, is a passive coupled-line structurecapable of functioning as a very broadband 3-dB 90° splitter. It is similar in struc-ture to an interdigital filter and can be constructed as a microstrip circuit. The band-width capability is very large, with 2 octaves or more being common (see [30], forexample) and up to a decade of bandwidth being achievable. The typical applica-tion frequency range is, however, in the mid-gigahertz to tens of gigahertz region. Ittherefore sees less application at current cellular and PCS frequency bands.

The design of a Lange coupler is most usually achieved with the aid of a suitablemicrowave design software package. Many of these have Lange coupler designs asexamples or interdigital circuit analysis as a specific function. The basic designequations are, however, provided in the literature [31], if required.

Since this quadrature circuit is a passive structure, it is suitable for both CW(local oscillator) and modulated signal applications. Furthermore, the modulatedsignal can occupy the whole of its designed bandwidth, if desired. In other words, itsinstantaneous bandwidth is identical to its operational bandwidth. The same is nottrue of, for example, the highpass/lowpass configuration shown in Figure 5.35.

There are two main drawbacks of the Lange coupler when considered as astand-alone circuit element:

1. It is typically a large structure when used at UHF frequencies. For example, alength of 12 cm is reported in [30] for a coupler operating at a centrefrequency of 625 MHz.

2. The line widths and line spacings can be very small and may be difficult torealize in practice due to etching tolerances for a typical PCB.

The tolerances required in a Lange coupler fabrication usually restrict them tohybrid or MMIC fabrication technology, with hybrid designs being known at 750


λ/4 at design centre frequency

Input

Output 1(coupled port)

Output 2(direct port)

Isolatedport

Figure 5.43 Lange coupler for use as a broadband 90° phase splitter.

MHz and many MMIC designs known at 10 GHz, 4–16 GHz, and 1–19 GHz. As anindication, the size of a 10-GHz design can be around 2.4 mm × 1 mm.

5.5.9 Multiplier-Divider Techniques

It is possible to use digital electronic techniques to create a simple quadrature net-work, as shown in Figure 5.44. Clearly, this technique is only appropriate for CW(e.g., local oscillator) signals, as it does not attempt to preserve the fidelity of theinput signal (indeed, quite the reverse). It can, however, produce high accuracyquadrature signals from a relatively simple circuit and is capable of very broadoperating bandwidths.

Operation of the system may be explained as follows. The input signal is con-verted to a squarewave, utilising a limiter or limiting amplifier. It is then squaredusing a suitable squaring process. This is shown in Figure 5.44 as a mixer or multi-plier with both inputs connected together, however a range of other alternativesexist (e.g., a saturating amplifier stage, followed by a bandpass filter tuned to thesecond harmonic). The output of this squarer is a squarewave (clock) signal at twicethe original local oscillator input frequency.

This frequency-doubled clock signal is then split and fed to two toggle flip-flops,one of which is positive edge-triggered and the other negative edge-triggered. Thesetwo flip-flops then, effectively, divide the signal frequency by two (thereby restoringthe original local oscillator frequency), but do so based on differing edges of theclock signal. The result of this, as can be seen in the timing diagram shown in Figure5.45, is that the two output signals appear in quadrature.

An integrated example of the use of digital flip-flops for quadrature generationis described in [32]. In this example the flip-flops are clocked with a signal operatingat four times the desired local oscillator frequency (after an initial 2:1 frequencydivision). Two flip-flops are used in cascade in each I or Q section, thereby provid-ing a total frequency division of 4, with the arrangement being designed to provide


RF In

Out1( 45º)−

Out2(+45º)

Squarer

Q

QT

CLK

+V(logic 1)

+V(logic 1)

Q

QT

CLK

Toggleflip-flop

Toggleflip-flop

Limiter

Figure 5.44 Use of digital techniques to create a broadband 90° splitter.

all of the necessary signals to drive its integrated mixer sections directly (a total of 6signals). The principle of operation is essentially similar to that of Figure 5.44,however.

A second example is described in [33], in this case employing a VCO running attwice the desired output frequency, which is used to lock the second-harmonic oftwo LC dividers. This concept, termed superharmonic injection locking is describedin detail in [34]. It is reported to have the advantage, over polyphase filtering, oflower power consumption, when used in a direct-conversion receiver design. This isdue to the fact that the mixers employed in a direct-conversion receiver usually havea large input capacitance, to minimize 1/f noise, and therefore buffer amplifiers arerequired between the polyphase filter and the downconversion mixers. This addi-tional buffering requirement adds to the device power consumption.

The quadrature accuracy achieved using this technique (reported in [33]), is anamplitude error of better than 0.9 dB and a phase error of less than 2.5°.

References

[1] Kenington, P. B., High Linearity RF Amplifier Design, Norwood, MA: Artech House,2000.

[2] Cavers, J. K., and M. Liao, Adaptive Compensation for Imbalance and Offset Losses inDirect Conversion Transceivers, IEEE Trans. on Vehicular Technology, Vol. 42, No. 4,1993, pp. 581–588.

[3] Faulkener, M., T. Mattson, and W. Yates, Automatic Adjustment of Quadrature Modula-tors, IEE Electronics Letters, Vol. 27, No. 3, pp. 214–216, 1991.

[4] Lohtia, A., P. Goud, and C. Englefield, An Adaptive Digital Technique for Compensatingfor analogue Quadrature Modulator/Demodulator Impairments, Proc. of IEEE PacificRim Conference, 1993, pp. 447–450.

[5] Hilborn, D., S. Stapleton, and J. Cavers, An Adaptive Direct Conversion Transmitter, IEEETrans. on Vehicular Technology, Vol. 43, No. 2, 1994, pp. 223–233.

[6] Cavers, J. K., New Methods for Adaption of Quadrature Modulators and Demodulators inAmplifier linearisation Circuits, IEEE Trans. on Vehicular Technology, Vol. 46, No. 3,1997, pp. 707–716.


Limiter output

Squarer output

Out 1

Out 2

Figure 5.45 Timing diagram for the digital 90° splitter.

[7] 3GPP Specification TS 25.141, Base Station Conformance Testing (FDD), 2000.[8] 3GPP Specification TS 25.104, UTRA (BS) FDD: Radio Transmission and Reception, 2000.[9] Cox, D. C., Linear Amplification with Nonlinear Components, IEEE Trans. on Communi-

cations, Vol. COM-22, December 1974, pp. 1,942−1,945.[10] Kenington, P. B., High Linearity RF Amplifier Design, Norwood, MA: Artech House. 2000,

Chapter 7.[11] Weaver, D. K., A Third Method of Generation and Detection of SSB Signals, Proc. of the

Institute of Radio Engineers, No. 44, 1956, pp. 1,703−1,705.[12] Bateman, A., R. J. Wilkinson, and J. D. Marvill, The Application of Digital Signal Process-

ing to Transmitter linearisation, IEEE 8th European Conference on Electrotechnics, Stock-holm, Sweden, June 1317, 1988, pp. 64–67.

[13] Scafferer, B., and R. Adams, A 3V CMOS 400mW 14b 1.4GG/s DAC for MulticarrierApplications, IEEE ISSCC Dig. Tech. Papers, February 2004, pp. 360–361.

[14] Luschas, S., R. Schreier, and H. S. Lee, Radio Frequency Digital-to-analogue Converter,IEEE Journal of Solid-State Circuits, Vol. 39, No. 9, September 2004, pp. 1,462–1,467.

[15] Tao, H., L. Toth, and J. Khoury, Analysis of Timing Jitter in Bandpass Sigma-Delta Modu-lators, IEEE Trans. on Circuits and Systems II, Vol. 46, August 1999, pp. 991–1,001.

[16] Adams, R., et al., A 113dB SNR Oversampling DAC with Segmented Noise-Shaped Scram-bling, IEEE ISSCC Dig. Tech. Papers, February 1998, pp. 62–63.

[17] Zhang, B., Delta-Sigma Modulators Employing Continuous-Time Circuits and Mis-match-Shaped DACs, Ph.D. thesis, Oregon State University, Corvallis, OR, 1996.

[18] Luschas, S., and H. S. Lee, High Speed Sigma-Delta Modulators with Reduced Timing JitterSensitivity, IEEE Trans. on Circuits and Systems II, Vol. 49, November 2002, pp. 712–720.

[19] Park, Y., and J. S. Kenney, Adaptive Digital Predistortion on linearisation of FrequencyMultipliers, IEEE Trans. on Microwave Theory and Techniques, Vol. 51, No. 12, Decem-ber 2003, pp. 2,516–2,522.

[20] Camargo, E., Design of FET Frequency Multipliers and Harmonic Oscillators, Norwood,MA: Artech House, 1998.

[21] Perrott, M. H., T. L. Tewksbury, and C. G. Sodini, A 27-mW CMOS Fractional-N Synthe-sizer Using Digital Compensation for 2.5-Mb/s GFSK Modulation, IEEE Journal ofSolid-State Circuits, Vol. 32, No. 12, December 1997, pp. 2,048–2,060.

[22] Mehta, J. L., Transceiver Architectures for Wireless ICs, RF Design, February 2001,pp. 76–96.

[23] Riley, T., and M. Copeland, A Simplified Continuous Phase Modulator Technique, IEEETrans. on Circuits and Systems II, Vol. 41, No. 5, May 1994, pp. 321–328.

[24] Gingell, M. J., Single-Sideband Modulation Using Sequence Asymmetric Polyphase Net-works, Electronic Communication, Vol. 48, No. 1-2, 1973, pp. 21–25.

[25] Behbahani, F., et al., CMOS Mixers and Polyphase Filters for Large Image Rejection, IEEEJournal of Solid-State Circuits, Vol. 36, No. 6, June 2001, pp. 873–887.

[26] Bedrosian, S. D., Normalized Design of 90° Phase-Difference Networks, IRE Trans. on Cir-cuit Theory, June 1960.

[27] Warr, P. A., et al., Quadrature Signal Splitting Technique Offering Octave-Band Perfor-mance, IEE Electronics Letters, Vol. 37, No. 4, February 15, 2001, pp. 262–263.

[28] Watkins, G. T., P. A. Warr, and J. P. McGeehan, Tunable Broadband Quadrature PhaseSplitting Technique, IEE Electronics Letters, Vol. 38, No. 13, June 20, 2002, pp. 641–642.

[29] Lange, J., Interdigital Stripline Quadrature Hybrid, IEEE Trans. on Microwave Theory andTechniques, Vol. 17, December 1969, pp. 1,150–1,151.

[30] Chi, C. -Y., and G. M. Rebeiz, Design of Lange-Couplers and Single-Sideband Mixers UsingMicromachining Techniques, IEEE Trans. on Microwave Theory and Techniques, Vol. 45,No. 2, February 1997, pp. 291–294.


[31] Ou, W. P., Design Equations for an Interdigital Directional Coupler, IEEE Trans. onMicrowave Theory and Techniques, Vol. 23, February 1975, pp. 253–255.

[32] Hornak, T., et al., An Image-Rejecting Mixer and Vector Filter with 55 dB Image Rejectionover Process, Temperature, and Transistor Match, IEEE Journal of Solid-State Circuits,Vol. 36, No. 1, January 2001, pp. 23–33.

[33] Gatta, F., et al., A Fully Integrated 0.18-µm CMOS Direct Conversion Receiver Front-Endwith On-Chip LO for UMTS, IEEE Journal of Solid-State Circuits, Vol. 39, No. 1, January2004, pp. 15–23.

[34] Rategh, H. R., and T. H. Lee, A CMOS Frequency Synthesizer with an Injection-LockedFrequency Divider for a 5 GHz Wireless LAN Receiver, IEEE Journal of Solid-State Cir-cuits, Vol. 34, No. 6, June 1999, pp. 813–821.


C H A P T E R 6

Linearisation and RF SynthesisTechniques Applied to SDR Transmitters

6.1 Introduction

The discussion of transmitter techniques up to this point has assumed that the trans-mitter components, most notably the RF power amplifier, are intrinsically linear toa degree commensurate with the application under consideration. This is typicallynot so and some form of linearisation or RF synthesis technique is required to createthe desired high-power RF signal. A complete and detailed discussion of RF poweramplifier linearisation techniques is beyond the scope of this book and has been pre-viously undertaken by the author [1]. This section will therefore concentrate onsummarizing the primary techniques for linearisation that are currently employedin software defined radio systems and how these may be incorporated or accommo-dated in the transmitter architectures outlined in Chapter 5.

The various options break down in to three categories:

1. Power amplifier linearisation techniques. These can be employed in directsubstitution for the linear power amplifier blocks shown in the transmitterarchitectures outlined in Chapter 5.

2. Transmitter linearisation techniques. These techniques are typicallybaseband input systems (with either digital or analogue inputs) and must beemployed within or around the architectures described in Chapter 5.

3. RF synthesis techniques. Again, these are typically baseband input systems;however, the high-power RF waveform is now formed at the output of thetransmitter from high-power non-linear waveforms generated within thetransmitter. Again, these must be employed within or around thearchitectures described in Chapter 5. Most of these techniques have yet tofind widespread acceptance in software defined radio systems, although theywill undoubtedly do so in the future. Early applications have tended toconcentrate on handset designs, where the advantages, in terms of improvedbattery life (or smaller and lighter battery requirements), are mostimmediately beneficial.

6.2 Power Amplifier Linearisation Techniques

As discussed earlier, these techniques may be used to create the linear power ampli-fier modules, which are assumed in the transmitter architectures outlined in

233

Chapter 5. They are RF input/output systems and should require no interactionwith, or knowledge of, the operation of the remainder of the transmitter. In practicesome form of interaction is usually present, such as providing information on theinput signals presence/absence (e.g., burst framing), approximate power level, enve-lope, and so forth. This information can help with both the linearisation processitself (e.g., allowing it to hold coefficients when no signal is present) or with improv-ing the efficiency of the overall transmitter, such as during low power or suspendedoperation (e.g., by controlling transistor bias levels). In the following discussion,however, no form of interaction will be assumed and the techniques will be treatedas stand-alone.

6.2.1 Predistortion

Predistortion is conceptually the simplest form of linearisation for an RF poweramplifier. It simply involves the creation of a distortion characteristic which is pre-cisely complementary to the distortion characteristic of the RF PA and cascading thetwo in order to ensure that the resulting system has little or no input-output distor-tion. It is, of course, possible to cascade the complementary distortion element afterthe RF PA and this is referred to as postdistortion; however, there are a number ofobvious drawbacks with that technique and few advantages (for high-power ampli-fiers). The result is that most complementary distortion systems are based aroundpredistorting the input signal.

6.2.2 Analogue Predistortion

Analogue predistortion is typically performed at RF (or IF) due to the relative sim-plicity of fabricating suitable networks at these frequencies. Although it is also possi-ble to fabricate baseband predistortion networks, these are much less popular andhave been largely replaced by digital baseband predistortion systems (describedlater).

A fundamental advantage of RF predistortion lies in its ability to linearise theentire bandwidth of an amplifier or system simultaneously. It is therefore ideal foruse in wideband multi-carrier systems, such as in cellular or PCS base-stationapplications.

The degree of linearity improvement which can be achieved in practice dependsupon a wide variety of considerations and in particular on the form of the transfercharacteristic of the amplifier. With traditional predistortion systems, the achiev-able linearity improvement is modest, by comparison with, say, a controlledfeedforward system or a Cartesian feedback system, but is adequate in many appli-cations. In general, the better behaved the transfer characteristic is, the greater thedegree of improvement which can be achieved and, more importantly, maintainedover a variety of input conditions (most notably power level). This is not true, how-ever, if the amplifier is already very linear, for example, if it is operating backed-offor is a low-power class-A amplifier. In this case, the dominant non-linearity may notbe due to compression, making it difficult for simple forms of predistortion to workwell.

234 Linearisation and RF Synthesis Techniques Applied to SDR Transmitters

6.2.1.1 Theory of Operation

The basic form of a predistortion linearisation scheme is shown in Figure 6.1. Thepredistorting function, β(•), operates on the input signal in such a manner that itsoutput signal is distorted in a precisely complementary manner to the distortionproduced by the RF PA, F(•). The output signal is therefore an amplified, but undis-torted replica of the input signal.

The problem then is to ascertain the required form of the predistortion charac-teristic and to fabricate a circuit with a transfer characteristic which closely resem-bles the required function (see Figure 6.2). Note that Figure 6.2 is only anillustration of the form of operation and that a practical (e.g., cubic) predistorterwill not result in a characteristic which is a direct mirror image of the amplifier char-acteristic, as suggested by this diagram. This is, at least in part, because it is notusual to predistort even-order elements of the amplifier transfer function, henceresulting in a marked difference between the predistorter and inverse amplifiercharacteristics.

This is not a trivial problem and a large number of different networks have beenutilised over the years in an attempt to mimic various types of characteristic. Thesimplest and most widely used networks merely attempt to predistort thethird-order characteristic and may, in the process, increase the level of higher-orderdistortion products.

Other networks attempt to curve-fit the distortion characteristic and therebyimprove the performance of a number of orders of distortion. For such networks toachieve a high level of performance, however, they often need to be designed, or atleast adjusted, for each individual amplifier (even of the same design). Predistortionamplifiers can therefore benefit from the use of an automatic control technique invery much the same manner as a feedforward system (covered later in this chapter).

An example of an ideal curve-fit of this type is shown in Figure 6.3. In this case,terms up to third order [for Figure 6.3(a, b)] and fifth order [for Figure 6.3(c, d)] areused to fit the (measured) characteristic of a quasi-linear PA—the inclusion ofeven-order terms is necessary to provide a good illustration of the quality of the fit;

6.2 Power Amplifier Linearisation Techniques 235

Input

Vi

Output

Vo

F( )α

Predistorter RF amplifier

F V A ( )β =i

iβ( )V

Figure 6.1 Schematic of an RF amplifier and predistorter.

β( )V

Vi

F( )α

α

V

Vi

i o

Figure 6.2 Operation of a predistortion system.


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−5.00

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0.00

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20.00

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−7.5 −7 −6.5 −6 −5.5 −5 −4.5 −4 −3.5 −3 −2.5 −2 −1.5 −1 −0.5 0Backoff [dB]

I channelClosest fit

Closest fit given by: y 8E-05x 0.0148x 0.4906x 5.6395= − + − +3 2

Volta

ge[V

]

Closest fit given by: y 5E-05x 0.0144x 0.817x 5.7255= − + +3 2

−7.5 −7 −6.5 −6 −5.5 −5 −4.5 −4 −3.5 −3 −2.5 −2 −1.5 −1 −0.5 0Backoff [dB]

Volta

ge[V

]

Q channel

Closest fit(b)

Figure 6.3 Characteristics of a quasi-linear amplifier, with corresponding optimal polynomial fit: (a)I-channel, third-order polynomial; (b) Q-channel, third-order polynomial; (c) I-channel, fifth-orderpolynomial; and (d) Q-channel, fifth-order polynomial.

however, such terms would be omitted in a practical implementation. Note that thenon-linearity present in this quasi-linear PA is quite large, as this illustrated the


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(c)

(d)

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0.00

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20.00

30.00

−7.5

−7.5

−7

−7

−6.5

−6.5

−6

−6

−5.5

−5.5

−5

−5

−4.5

−4.5

−4

−4

−3.5

−3.5

−3

−3

−2.5

−2.5

−2

−2

−1.5

−1.5

−1

−1

−0.5

−0.5

0

0

Closest fitQ channel

Backoff [dB]

Backoff [dB]

Volta

ge[V

]

I channelClosest fit

Volta

ge[V

]

Closest fit given by: y 1E-08x 5E-06x 0.0005x 0.0156x 0.0801x 3.3243= − + − + +5 4 3 2

Closest fit given by: y 3E-08x 1E-07x 0.0002x 0.0109x 0.1316x 13.561= − + − + +5 4 3 2

−25.00

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−10.00

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0.00

5.00

10.00

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−30.00


properties of the fit well, visually; a well-designed class-A or AB amplifier wouldtypically exhibit a much more linear characteristic. Note also that the curve-fit illus-trated is that of the amplifier model and not that required to predistort the amplifier.

6.2.2.2 Cubic Predistorters

The aim of a cubic predistorter is to eliminate third-order distortion by means of thecorrectly phased addition of a cubic component to the RF input signal. In the case ofa bandpass system, it is only necessary (or beneficial) to reduce the third-order prod-ucts to the same level as, or slightly below, the level of the next highest products(usually the fifth-order products). Improvements beyond this point are generally oflittle benefit, other than when predistortion is used in conjunction with feedforward,in which case, the power contained in the error signal (and hence the power ratingrequired of the error amplifier) can perhaps be reduced.

One form of cubic predistorter is shown in Figure 6.4. The RF (or IF) input signalis split, in this case by a directional coupler, to form a main path and a secondarypath. The main path contains a time-delay element, to compensate for the delaythrough the various elements in the secondary path, and ensure that the signalsrecombine with the correct time relationship. Since this delay element will typically beoperating at a low power level, its insertion loss is usually not critical, although it willcontribute to the overall noise figure of the system. Furthermore, it may be eliminatedin narrowband (e.g., single-carrier) systems, particularly when the system is fabri-cated on an IC. This is due to the fact that the delay difference between the two pathswill be sufficiently small to remain within the coherence bandwidth of the system.

The secondary path contains a low-level buffer amplifier, followed by gain andphase control elements to ensure that the correct relationship is achieved at the sum-ming junction (combiner). The predistortion element is formed by the cubic non-lin-earity and the resulting signal is buffered and amplified by the postdistortionamplifier. Both of the amplifiers in the secondary path are small-signal devices andhence should contribute negligible distortion.

The configuration shown in Figure 6.4 is that of a scalar predistorter and thephase relationship between the upper and lower paths is such that the lower pathsubtracts from the upper path, as outlined next.

The order and placement of many of the components in a cubic predistorteris not critical. An alternative version is shown in Figure 6.5 [2], in which the


Directionalcoupler

Timedelay

τ

RFamp

Variablephase-shift

ΦRFamp

( )3

Inputx t( )

Variableattenuator

Cubicnon-linearity

Outputz t( )

Figure 6.4 Cubic RF/IF predistorter.

phase-shifter is incorporated in the delay-line path and the attenuator follows thecubic non-linearity. The principal advantages of this configuration are that the gainand phase controllers are largely isolated from each other (some interaction canoccur otherwise) and that the delay line can be shorter (or even eliminated) since thedelay through the gain and phase controllers is likely to be similar.

There are many methods by which a cubic non-linearity may be constructed,most of which involve a diode or transistor with a characteristic which closelymatches the third-order characteristic of the non-linear amplifier. Where access to asilicon foundry is possible, the characteristics of the predistorter device may bedesigned to accurately match the required characteristic and this method providesthe best performance. Some typical predistorter devices include dual-gate GaAsFETs operating close to pinch-off [3] and Schottky diodes [4]. Further details on arange of circuit configurations for this element are provided later.

6.2.2.3 Practical Predistorter Circuits

There exists a range of relatively simple predistortion circuits which can be config-ured for use at either RF or IF (depending upon the precise components used), anda number of examples are provided in the following. These systems typically sacri-fice performance for simplicity and are appropriate where modest linearityimprovements are required.

Series-Diode Predistorter

The simplest form of predistort non-linear element is a series diode, with manyexamples appearing in the literature (e.g., [5−7]). The format of this type ofpredistorter is illustrated in Figure 6.6.

The predistorter uses a Schottky diode with a separate parallel capacitor (CP) inorder to achieve a positive amplitude and a negative phase deviation at a low-biascondition (set by the bias resistor, Rbias). Adjustment of the bias resistor and thevalue of the parallel capacitor allow the predistorter characteristic to be matched asclosely as possible to that of the power amplifier under consideration.

This type of predistorter will not result in spectacular linearity improvementsnor large efficiency gains, but is nevertheless very simple and cost-effective.


Cubicnon-linearity

( )3

τΦ

Variableattenuator

Delayline

Phaseshifter

Input Output

Figure 6.5 Alternative form of RF/IF predistorter.

Adjacent channel power ratio (ACPR) improvements in the region of 4 dB for IS-95CDMA have been reported at 1.9 GHz (in [5]).

Varactor Diode Predistorter

This format of predistorter is strictly a combination of two techniques: a varactordiode for AM-PM linearisation and second harmonic control for AM-AMlinearisation. This combination has the advantage, over the series diode techniqueoutlined above, of a lower insertion loss (around 2 dB relative to perhaps 6 dB forthe series-diode alternative).

The application of this technique to a GaAs FET single-stage amplifier is shownin Figure 6.7 [8]. The varactor diode functions as a compensation for the nonlinearcapacitance at the input to the GaAs FET and hence serves to greatly reduce theAM-PM conversion in the resulting amplifier. The AM-AM characteristic islinearised using source second harmonic control [9] and hence the combination ofthe two techniques compensates for both the AM-AM and AM-PM conversion ofthe amplifier. The reported improvement in first adjacent channel performance for aπ/4-DQPSK signal (Japanese PHS specification) was around 15 dB.

FET-Based Predistorters

A number of variants on the basic use of a FET source-drain channel as a predistorterelement are shown in Figure 6.8 [10, 11]. These diagrams illustrate the form of thistype of non-linearity, however a wide variety of possible configurations exist.

Figure 6.8(a) shows a basic transmissive-mode non-linearity, which could beemployed as the non-linear element in the predistorter shown in Figure 6.4. The biasvoltage adjusts the degree (severity) of non-linearity created and the variable capaci-tance acts to approximately adjust the phase of the resulting IM products. The balunis used to extract the required signal across the source and drain terminals of theFET, although other methods could be employed to fulfill this function (e.g., a dif-ferential amplifier).


RF input RF output

+V

RFC

RFC

Rbias

CP

CIN COUTDiode

Figure 6.6 Series-diode predistorter.

Figure 6.8(b) now employs the FET in a reflective mode, in this case on one ter-minal of a circulator. A signal entering the circulator is passed to the port connectedto the FET non-linearity and the resulting (distorted) reflected signal then passes tothe output of the circulator. In this way the input and output match of the non-lin-earity may be maintained at a reasonable level over a relatively broad bandwidth(governed ideally by the circulator). The variable bias voltage has a similar affect tothat described above and the variable impedance can provide a degree of bothamplitude and phase control of the signals emanating from the non-linearity.

Finally, Figure 6.8(c) also employs the FET in a reflective mode, in this case inconjunction with a hybrid splitter/combiner. Operation is similar to that of thecirculator-based approach described earlier, with the principal difference being thatthe resistance, R2 may be used to define an amount of undistorted input signalenergy appearing in the output (by making R2 other than a matched load). Thephase of this signal may also be varied by making this impedance other than purelyresistive. If the hybrid used is a 180° type, then this system can be configured as acomplete predistorter, rather than just a non-linear element [in much the same wayas the anti-parallel diode predistorter illustrated in Figure 6.9(c)].

Anti-parallel Diode-Based Predistorter

Arguably the simplest practical form of third-order diode-based predistorter isshown in Figure 6.9 in three different variants [12−17]. In Figure 6.9(a, b), thepredistorter is formed around a T-attenuator (implemented by resistors R1−R3)which serves to sample the main RF signal path and also to reinject the distortioncomponent back in to that path. The non-linearity itself is implemented by twoanti-parallel diodes [Figure 6.9(a)] or by a diode bridge [Figure 6.9(b)]; both config-urations share the property that if the diodes are perfectly matched, then ideallyonly third-order distortion is generated and reinjected into the main path.


RF inputRF output

VGS

RFC

Rbias

Varactordiode

λ/4at 2f0

λ/4at 2f0

RFC

VDD

VD

Figure 6.7 Varactor diode predistorter applied to a single-stage FET amplifier. (From: [8] © IEEE2005)


R2

RFinput

R1

+V

-VGND

Out(B)

In1(U)

In2(U)

RFoutput

Balun

C1

VR1FET

RFinput

R1

+V

-VRFoutput

VR1FET

N

Variableimpedance

Circulator

RFinput

R1RFoutput

VR1FET

RFC

R2

L1

C1C2

Vb

(c)

(b)

(a)

Figure 6.8 FET-based RF predistorter non-linearity: (a) transmissive mode source-drainnon-linearity; (b) reflective mode source-drain non-linearity employing a circulator; and (c) reflectivemode source-drain non-linearity employing a hybrid.


RF input RF output

RF PA

D1 D2

180º

0º

τ

CR

RF input RF output

RF PAR2R1

R3

D2D1

RF input RF output

RF PA

(b)

(c)

(a)

R2R 1

R3

D3D1

D2 D4

Figure 6.9 RF predistorter employing anti-parallel diodes (bias networks not shown): (a)conventional anti-parallel configuration, (b) bridge configuration; and (c) hybrid-basedconfiguration.

If the diodes are not perfectly matched (as will be the case with all practicaldiodes), then second-order distortion will also be generated and this can interactwith the non-linearity of the amplifier and generate unwanted additional IMD prod-ucts [18].

The use of an attenuator as the sampling and injection mechanism is a simplemethod of performing both functions while maintaining an acceptable 50-Ω matchfor both the input and output signals. It will, however, have an affect on noise figureperformance of the overall amplifier and it may be preferable to employ directionalcouplers instead in some applications (with additional amplification in the non-lin-earity path as necessary).

High-speed Schottky diodes are required for D1−D4, with an operating fre-quency range commensurate with the required RF operating frequency. Additionaltemperature (or other) compensation may be required to maintain performance overa range of operating conditions.

In Figure 6.9(c), a 180º hybrid splitter/combiner is used, and this arrangementhas a number of advantages over the previous two variants. The linear impedance(resistance) in the 0º path of the hybrid serves to cancel the residual linear compo-nent at the output of the diode branch; the capacitor appearing in parallel with thisimpedance compensates for the diodes reactance. The hybrid also presents a goodimpedance match for both the input and output signals.

6.2.2.4 Adaptive Control of Predistortion

The IMD improvement obtained from a predistortion system depends upon the gainand phase matching accuracy of the two paths in the predistorter (particularly thegain matching). In order to achieve and maintain optimum performance of thepredistorter, it is therefore necessary to ensure that this matching can be maintainedover the lifetime of the amplifier and over its operational temperature range anddynamic range.

In many cases, the degree of improvement in IMD performance sought frompredistortion is relatively modest, perhaps being in the order of 10 dB, and hence aninitial setting up procedure is all that the product will require. In cases where morestringent specifications are placed upon the predistortion system, some form ofadaptive control of the gain and phase matching will be required (as is also the casefor feedforward systems). In most cases, this control is only required to deal withtemperature changes and component aging and hence the adaption rate needs onlyto be slow.

6.2.3 Feedforward

The feedforward linearisation technique has been in widespread use in base-stationapplications for a number of years. Although it is a relatively complex and expensivetechnique in terms of its hardware implementation, it does have the advantage ofexcellent linearity performance when controlled by a suitable automatic controltechnique. Typical applications within the base-station arena call for IMD specifica-tions of between −55 and −75 dBc over instantaneous bandwidths of between 5MHz and 30 MHz. All of these specifications can be met with the feedforward


technique, either used alone or in conjunction with, for example, RF predistortion.The feedforward technique may also be applied a number of times to provideimproved linearity performance, although this is clearly at the expense of consider-ably increased complexity.

In software defined radio applications, the standard feedforward approach doesnot provide any synergistic benefits (unlike, for example, digital predistortion,where many elements are common between a software defined radio transmitterand a digitally predistorted transmitter). The feedforward technique is applied onlyto the power amplifier and this must be preceded by an upconverter designed to ahigher linearity specification than the feedforward amplifier (such that thefeedforward amplifier IMD dominates). When IMD specifications of −70 dBc orgreater are required, this can represent a significant challenge and may result in arelatively expensive upconverter.

6.2.4 Basic Operation

In its simplest form, a feedforward amplifier consists of the elements shown in Fig-ure 6.10. Its operation may be clearly seen by referring to the two-tone test spectrashown at various points throughout the diagram.

The input signal is split to form two identical paths, although the ratio used inthe splitting process need not be equal. The signal in the top path is amplified bythe main power amplifier and the non-linearities in this amplifier result inintermodulation and harmonic distortions being added to the original signal. Noiseis also added by the main amplifier, although this is generally neglected in mostapplications.

The directional coupler, C1, takes a sample of the main amplifier output signaland feeds it to the subtracter (180º hybrid) where a time-delayed portion of the orig-inal signal, present in the lower path, is subtracted. The result of this subtractionprocess is an error signal containing substantially the distortion information fromthe main amplifier; ideally none of the original signal energy would remain.

The error signal is then amplified linearly to the required level to cancel the dis-tortion in the main path and fed to the output coupler. The main-path signalthrough coupler, C1, is time delayed by an amount approximately equal to thedelay through the error amplifier, A2, and fed to the output coupler in anti-phase to


τ

A1

A2

Mainamplifier

Erroramplifier

Timedelay

τTimedelay

Subtracter

SplitterInput

OutputC1 C2

Figure 6.10 Configuration of a basic feedforward amplifier.

the amplified error signal. The error signal will then cancel the distortion informa-tion of the main path signal leaving substantially an amplified version of the originalinput signal.

For an ideal system, and assuming that the subtracter and coupler C2 providethe required signal inversion for subtraction to take place internally, the followingequations may be derived.

If it is assumed that the input splitter is an ideal 3-dB hybrid, then the output ofthe main amplifier, VA1(t), for a system input signal, Vin(t), is:

( ) ( ) ( )V tA

V t V tAA

inj

dA

11

21= +−e ωτ (6.1)

where A1 is the main amplifier time delay at an angular frequency ω, AA1 is the mainamplifier gain, and Vd(t) is the distortion added by the main amplifier.

The proportion of this signal which reaches the subtracter is determined by thecoupling factor of coupler, C1. If this factor is 1/CC1, then the signal reaching oneinput to the subtracter is:

( ) ( ) ( )V t

A

CV t

V t

CsubA

Cin

j d

C

A1

1

1 121= +−e ωτ (6.2)

The signal reaching the other input, assuming the time delay element to belossless is:

( ) ( )V t

V tsub

in j T2 2

1= −e ωτ (6.3)

where T1 is the delay in the time delay element.Thus the output of the subtracter (assumed lossless) is:

( ) ( ) ( )

( ) ( ) ( )V t V t V t

A

CV t

V t

C

V t

err sub sub

A

Cin

j d

C

inA

= −

= + −−

1 2

1

1 121e ωτ

21e− j Tωτ

(6.4)

It can be seen from (6.4) that for the original input signal to be completelyremoved from this error signal, the following conditions must hold:

τ τT A1 1= (6.5)

and

C AC A1 1= (6.6)

The resulting error signal is then:

( ) ( )V t

V t

Cerrd

C

=1

(6.7)


A similar process takes place in the second part of the loop in which the errorsignal components are removed from the main amplifier output signal to leave sub-stantially an amplified version if the original input signal.

The output from the main amplifier, having passed through the top-path timedelay element is:

( ) ( ) ( ) ( )V tA

V t V tTA

inj

djA T T

21

21 2 2= +− + −e eω τ τ ωτ (6.8)

where T2 is the time delay in the top-path delay element and this element is assumedlossless. This signal forms the main through-path signal for the output coupler, C2.The signal to be injected into the coupled port of this coupler is derived from theerror signal, Verr(t), having been amplified by the error amplifier.

( ) ( )V tA

CV tA

A

Cd

j A2

2

1

2= −e ωτ (6.9)

If the coupler is assumed to possess the necessary phase inversion to facilitatesubtraction of its two signals, then, given that the coupling factor is 1/CC2, the finaloutput signal is:

( ) ( ) ( )V t V t

V t

Cout TA

C

= −22

2

(6.10)

or

( ) ( ) ( ) ( ) ( )V tA

V t V tA

C CV tout

Ain

jd

j A

C Cd

A T T= + −− + −1 2

1 221 2 2e e eω τ τ ωτ − j Aωτ 2 (6.11)

In order for the distortion products, Vd(t), to cancel perfectly, the following con-ditions must hold:

τ τT A2 2= (6.12)

and

A C CA C C2 1 2= (6.13)

The final output signal is then:

( ) ( ) ( )V tA

V toutA

inj A T= − +1

21 2e ω τ τ (6.14)

or, alternatively:

( ) ( ) ( )V tA

V toutA

inj A A= − +1

21 2e ω τ τ (6.15)


Thus the output signal is an amplified and time-delayed replica of the input sig-nal with the distortion from the main amplifier removed.

Note that the above argument assumes that the error amplifier is distortion-freeand hence contributes no additional distortion to the output spectrum. In reality,this will not be the case; however, the error amplifier will generally be operating at amuch lower power level than the main amplifier, and hence can usually be designedto have a greater degree of linearity than that of the main amplifier. It is also pre-dominantly operating on the distortion information from the main amplifier, whichis at a much lower level than the main signal energy, and hence the distortion pro-duced by the error amplifier will be relative to the main amplifier’s distortion leveland thus very significantly lower than the wanted signal energy. It is therefore rea-sonable, to a first approximation, to ignore the distortion added by the erroramplifier in this analysis.

The cancellation achieved by a feedforward system implies a requirement for ahigh degree of matching in both amplitude and phase for virtually all of the systemcomponents. This matching must also be maintained over the bandwidth of interest,which is generally large relative to that of feedback systems. Feedforward systemsare generally applied at frequencies or over operating bandwidths where feedbacksystems are inappropriate. Amplitude and phase matching within the feedforwardloop must therefore be maintained over a wide frequency range.

The lack of an intrinsic feedback path in a basic feedforward system means thatit cannot monitor its own performance and hence correct for gain or phase changesdue to temperature or ageing effects. Although near perfect cancellation may be setup manually upon manufacture, for example, this will drift over time and degradeperformance. A control technique is therefore required to overcome this drift.

Figure 6.11 shows the amount of suppression which can be achieved for a givendegree of phase and amplitude matching in a feedforward amplifier [19].

In order to achieve around 25 dB of cancellation, a typical value in base-stationapplications, an amplitude error of better than 0.5 dB and a phase error of betterthan 5° would need to be achieved. In some applications more than 40 dB of sup-pression is required and the accuracy of the amplitude and phase matching becomesmore stringent at less than 0.1 dB and 0.1°, respectively. This would be extremelydifficult to achieve in a broadband amplifier system.

6.2.5 Power Efficiency

The power efficiency of a feedforward system is dependent upon the efficiencies ofthe main and error amplifiers and the coupling factor of the output coupler. It is pos-sible to derive a relationship for these parameters [20] with the resultantfeedforward efficiency given by:

( )( )

ηη η

η ηffA A DC DC

A DC A IM DC

C C

C F C=

−+ −

1 2

2 1

1

1(6.16)

where:For the main amplifier, A1:

Output power of A1 (per carrier): PA1 (W)


Efficiency: A1 (dimensionless)

Third-order intermod. level relative to carriers: SA1 (dB)

(Two-tone test)

For the error amplifier, A2:

Output power of A2 (per carrier): PA2 (W)

Efficiency: A2 (dimensionless)

For the output coupler, C2:

Coupling factor: Cf (dB)

Through-path insertion loss: Ltp (dB)

and

( )FIM

S A

= 101 10

(6.17)

( )CDCC S= −10 10 (6.18)

Conversely, the optimal coupling factor for a given main amplifier IMD leveland main and error amplifier efficiencies, is given by:

( )C

F F

FDCA IM A A IM

A IM A

=±

−2 4

21 1 2

1 2

η η η

η η(6.19)



10

20

30

40

50

60

70

80

0.02 dB

2.0 dB

0 dB0.01 dB

0.05 dB0.1 dB0.2 dB0.5 dB1.0 dB

Can

cella

tion

(dB)

10−2

10−1

100

1012 2 24 4 43 3 35 5 56 6 67 7

Figure 6.11 Distortion cancellation achievable by a feedforward amplifier with various values ofamplitude and phase error.

Figure 6.12 shows a range of typical efficiency characteristics obtained from(6.16). The six cases considered gradually change from high-linearity class-A mainand error amplifiers, through class-AB and B, to class-C. Although the efficienciesand IMD levels quoted will not be correct at all frequencies and power levels (due todevice technology differences), they allow some insight to be gained of the variouscompromises involved. In particular, note that for the lower-efficiency, more linearsystems, the characteristics are less sharply defined, making the choice of couplingfactor less critical. By contrast, the class-C based characteristics indicate that theoutput-coupling factor is a critical choice in obtaining optimum efficiency.

The peak efficiencies indicated in Figure 6.12 may be optimistic for a high-lin-earity system due to the residual main tone level present in the error signal. Its opti-mum power rating and power efficiency must be compromised in order to ensurethat its IMD contribution at the output is suitably small. Typical error amplifier effi-ciencies in this case could be as low as 1% or 2% (not the 5% assumed here).

Note also that losses present in the main-path delay line and associated samplingcouplers will further degrade the efficiency of the feedforward amplifier. The effi-ciency and optimum coupling factor equations shown above can be modified toincorporate this effect.

The overall efficiency of a feedforward amplifier, incorporating the insertionloss of the main path delay element L, and taking account of the additional powerdrawn by the main amplifier in generating its IMD products, is therefore:

( )( ) ( )

ηη η

η ηffA A DC DC

A IM DC A DC IM

C C

F C C L F=

−− + +

1 2

1 2

1

1 1(6.20)


Coupling factor of output coupler (dB)

Efficiency (%)

3 6 9 12 150

10

20

30 Case 6Case 5Case 4Case 3Case 2Case 1

40

18 21 24 27 30

Figure 6.12 Feedforward amplifier efficiency characteristic with a range of system parameters(given in Table 6.1).

Note that L is dimension-less; i.e., for a 3dB less, L = 0.5The optimum coupling factor for the output coupler, under the same circum-

stances, is then:

( )( )

CF F L F

F L FDC OPT

A IM A A IM IM

A IM A IM, =

± +

− +

η η η

η η1 1 2

1 2

1

1(6.21)

6.2.6 Maintaining Feedforward System Performance

A considerable part of the design effort focused on feedforward amplifiers over thepast 20 years has concerned the development of techniques to ensure the mainte-nance of optimum performance over time. Since the gain and phase-matching char-acteristics of feedforward amplifiers are critical to their performance, it is necessaryto ensure that these can be maintained throughout the designed life of the amplifier.

It is here that one of the major design decisions of any feedforward system mustbe made. There is a compromise between the additional complexity of either envi-ronmental stabilisation, additional circuitry to monitor loop performance and cor-rect for errors (i.e., a control scheme), or additional loops. It is instructive toexamine each of these three alternatives in turn.

6.2.6.1 Environmental Stabilisation

Specialist environmental stabilisation is usually considered impractical due to thecost and size of the necessary equipment; both are usually prohibitive. For certainenvironments this stability may occur naturally, such as in submarine cable applica-tions where the temperature of the seabed at a great depth remains substantiallyconstant throughout the year. However, even in this case, the effects of componentageing are not considered and hence the system performance is likely to degradewith time.

One approach to environmental stabilisation is that of deliberately heating theloop and its components by mounting them on a temperature-controlled heatingplate; the whole may then be thermally insulated from the outside world, thus pro-viding (by two mechanisms) a degree of thermal stabilisation. This method has beenused successfully in an outdoor repeater application, having as its main advantagerelative simplicity and hence reliability.


Table 6.1 Parameters for Figure 6.12

Main AmplifierIMD Level (dBc)

Main AmplifierEfficiency (%)

Error AmplifierEfficiency (%)

Case 1 −35 25 5

Case 2 −30 30 5

Case 3 −25 35 15

Case 4 −20 40 20

Case 5 −15 50 30

Case 6 −15 60 40

6.2.6.2 Performance Monitoring

The idea of using additional circuitry to allow the feedforward system to monitor,and correct for, its own performance has received considerable interest. There are anumber of patented configurations to fulfill this function, as it is arguably the mostelegant solution to the problem. A number of these configurations will be discussedin more detail towards the end of this section.

The idea of allowing the system to monitor its own performance and then per-form the necessary correction, implies some form of feedback system around thefeedforward loop. This feedback system is required to control the gain and phasematching of the two halves of the feedforward loop, termed the error loop and thecorrection loop for convenience (see Figure 6.13). Thus it is evident that two sepa-rate feedback systems are required: the first to correct for the gain and phase mis-matches in the error loop in order to minimise the input signal component of theerror signal, and the second to correct for the gain and phase mismatches in the cor-rection loop in order to minimise the amount of distortion present in the final outputsignal. These two loops are shown conceptually in Figure 6.13.

The gain and phase adjustment components (compensation circuits) shown inFigure 6.14 could appear in a number of different locations around the two halves ofthe feedforward loop. For example, these components in the error loop could beplaced in the top path either before or after the main amplifier (along with a numberof other positions as shown in Figure 6.15). Ultimately, the decision regarding theplacement of these components rests with the system designer; however, a numberof practical points must be considered.

1. Power handling. Since feedforward linearisation is most often appliedto amplifiers having a significant power output, the power-handlingcapabilities of the gain and phase compensation components must beconsidered. A common method of construction of these componentsinvolves the use of 3-dB quadrature hybrid couplers together with either PINor varactor diodes, respectively; however, both of these devices will onlyoperate at low signal levels. It is thus necessary to place them in small-signalparts of the system (i.e., at the inputs to, rather than the outputs from, eitherof the amplifiers).


τ

Mainamplifier

Timedelay

τ

Timedelay

Subtracter

Input

Output

Errorloop

Erroramplifier

Correctionloop

Figure 6.13 Error loop and correction loop in a feedforward system.

2. Linearity. The linearity of the adjustment components is critical to theoverall system performance, since any distortion generated by either willtranslate to the output. In the case of the correction loop, distortion fromthese components will be amplified by the error amplifier (assuming thatthey are placed before it) and appear directly in the output signal. In the caseof the error loop, if they are placed in the reference (lower) path, then theirdistortion will appear in the error signal and be amplified by the erroramplifier as above. If, however, they are placed before the main amplifier,then their distortion will appear as part of that from the main amplifier andit will be corrected as such, at the final output. For this reason a positionprior to the main amplifier is usually considered to be optimum for thesecomponents.

It is also possible to locate the adjustment components for the error loopbetween the sampling coupler and the subtracter (with suitable fixed attenuation asnecessary). The signal levels at this point will, in general, be small; however, any dis-tortion produced here will again appear in the error signal and will be amplified andtranslated to the output signal. A summary of the possible locations of the adjust-ment components is shown in Figure 6.15.

6.2.7 Performance Stabilisation Techniques

A large number of patents have been filed over the last 20 years relating to correc-tion schemes designed to maintain the amplitude and phase balances, discussed ear-lier, over time and temperature. Some of the principles upon which these are basedwill be highlighted in this section. In addition, some generic analysis of control sys-tem performance has been undertaken and is detailed in the literature [21].

6.2.7.1 Adaptive Nulling

Many of the automatic correction systems rely upon adaptive nulling of theunwanted signals at the various stages through the system. In the error loop, it is theinitial system input signals which require removal and hence monitoring the levels


τ

Mainamplifier

Timedelay

τTimedelay

Subtracter

Input

Output

Erroramplifier

Φ

ΦFeedbackcontrol

Feedbackcontrol

Figure 6.14 Feedback control applied to a feedforward amplifier.

of these signals and adjusting the amplitude and phase controls accordingly willensure optimum performance of this section.

The function of the correction loop is to cancel the distortion products from thefinal output of the system and hence it is the distortion component of the final out-put signal which must be monitored and minimised in this case.

In either case, the principles involved are quite similar and can be examinedtogether. For simplicity, it is sufficient to consider a two-tone test signal applied tothe input of the system and to look at the cancellation of these tones in the error sig-nal; this situation is illustrated in Figure 6.16. It will also be assumed thatout-of-band products may be ignored as these are generally removed by filtering andthus only intermodulation products need be considered.

Energy Minimisation

The most straightforward method of assessing the level of the tones within the errorsignal is simply to detect the overall energy of the complete signal. In general, thelevel of the distortion products is small relative to the wanted signals, and thus thewanted signal energy will dominate. Thus a system can be envisaged in which theoverall energy of the error signal is minimised by automatic adjustment of the gainand phase components using voltage control.

The use of energy minimisation in both parts of a feedforward correction loop isillustrated in Figure 6.17. The detector could be any form of broadband energydetector, a simple example being an envelope detector.

This somewhat crude approach may well be all that is required for the error sig-nal in some systems, as large amounts of rejection of the remaining input signalenergy below the level of the intermodulation products is not usually required. Oncethis level is low enough such that the error amplifier power is dominated by theintermodulation products, then this is generally acceptable. If the error amplifierspecification can be relaxed a little, such that it can be more powerful than is strictlynecessary, then the input signal rejection specification can be relaxed still further.The ultimate consideration now becomes the cancellation of the wanted signalenergy in the final output, which may be predicted using the methods outlined inSection 6.2.4. It may be acceptable to sacrifice a few tenths of a decibel of outputpower to the cause of reduced system complexity.


τ

Mainamplifier

τTimedelay

Subtracter

Input

Output

Erroramplifier

Compensationcircuit

Compensationcircuit

Compensationcircuit

Compensationcircuit

Compensationcircuit

Timedelay

Figure 6.15 Summary of the available locations for the gain and phase adjustment components inthe error and compensation loops.

In the case of the correction loop, two detectors are required. An output detec-tor is required to ascertain the level of the signal-plus-distortion present at the out-put and an input detector is necessary to provide an accurate indication of the inputpower level, and more importantly, any changes in that level (e.g., due to powercontrol variations). Whilst it would be possible to utilise an output detector alone,the extremely long time-constant required in that detector (due to the extremely


τ

Mainamplifier

Timedelay

Subtracter

Input

Compensationcircuit

(1)

(2)

(3)

(3)

(2)

(1)

(a)

(b)

Amplitude

Amplitude

Frequency

Frequency

Frequency

Amplitude

Figure 6.16 Two-tone test applied to a feedforward amplifier: (a) error-loop configuration and (b)cancellation of the input tones.

small changes in output level resulting from distortion level changes) means that itcould easily be fooled by even small changes in input (and hence output) level.

Utilising this technique for the correction loop is usually unsatisfactory for thereason outlined earlier. The wanted signal energy present at the output will be verylarge (hopefully) with respect to the remaining distortion and any changes in thisdistortion level will thus have an almost negligible effect on the output signal energy.As a result, the problem of detecting these small changes in energy becomes almostimpossible and an alternative solution is required.

One possibility is that of generating a second error signal from the output signal.The main signal energy should be substantially cancelled in this case and henceenergy detection could yield a more realistic result. Alternatively, it is possible todownconvert the sample of the output signal and use filtering to remove some or allof the main-signal energy, thereby substantially reducing the required detectiondynamic range. Multiple-stage, sharp roll-off filtering is required for this approach,with SAW and crystal filter technologies being typically the most suitable.

Coherent Detection

The obvious solution to the problems inherent in broadband energy detection sys-tems is to employ some form of coherent detection or correlation process instead.Thus, in the case of the error loop, the error signal could be correlated with the origi-nal input signals to generate a suitable feedback error signal to control the error loopgain and phase components. This is the basic approach which many of the patentedschemes employ.

The basic configuration of this approach is shown in Figure 6.18 and is similarto that published in a patent by Gerard and Hobbs [22]. The correction loop corre-lation process utilises the final output signal, and the error signal and this pro-cess assumes that the rejection of the original signal components, remaining in theerror signal, is very good. It is necessary to ensure good rejection of the original sig-nal components, in order to subsequently ensure that the result of the correlationprocess is influenced only by the distortion components and not by the wantedsignals.


τ

Mainamplifier

τ

Subtracter

Input

Output

Erroramplifier

Φ

Φ

Intelligentcontrol

Intelligentcontrol

DetectorDetector

Timedelay

Timedelay

Figure 6.17 Compensation of a feedforward amplifier using energy minimisation techniques.

A number of other patented systems work on a similar principle but utilise dif-ferent positions for their gain and phase adjusting circuits, along with techniques forreducing the tight constraints on the level of wanted signal components present inthe error signal. These include Bauman [23], Olver [24], King [25], and Keningtonet al. [26].

Alternative Coherent Detection Approach Enabled by SDR

Traditionally, feedforward amplifiers have been utilized in multi-carrier RFinput/output applications, in which the complete spectrum has been provided at theamplifier input. Utilising any control technique which requires the provision of sep-arate carriers has therefore been virtually impossible, and certainly prohibitivelyexpensive.

With the advent of SDR, however, the carriers may be provided separately,since the feedforward PA is likely to be one element of a complete transceiver, withall of the design under the control of a single manufacturer. The provision of sepa-rate carriers will still carry a price penalty, however, since separate DACs will berequired for each carrier and separate upconversion must then be employed. Theindividual DACs will require much more modest levels of performance (both interms of conversion speed and, typically, intermodulation performance) than wouldthe single or dual multi-carrier DAC(s) required in a more conventional BTStransmitter.

If an input signal comprising individual carriers is made available, thefeedforward (including control scheme) architecture of Figure 6.19 can beused [26]. This architecture only shows control of the main-signal removal processfrom the error signal, although a similar scheme can be used to create a version ofthe system output signal with substantially reduced main signal energy. Also, onlytwo carrier inputs are shown in Figure 6.19, although the principle could clearly beextended to three or more carriers if desired.


τ

Mainamplifier

Timedelay

τTimedelay

Subtracter

Input

Output

Erroramplifier

Φ

ΦControlcircuits

Correlator

Controlcircuits

Correlator

Figure 6.18 Compensation of a feedforward amplifier using correlation techniques.

258Linearisation

and RF Synthesis Techniques A

pp

lied toSD

RTransm

itters

τ

Mainamplifier

TimeDelay

τTimedelay

Subtracter

Input 1 Output

Erroramplifier

Φ

Φ

Control circuits

Correlator

Control circuits

Correlator

Input 2 Φ

To correlator/control circuitsfor input 1

From input 1 control circuits

To correlator/control circuitsfor input 1

Figure 6.19 Control of a feedforward amplifier using correlation techniques, with separate carrier inputs. Note that only one set of control circuitry is shown for clarity.

The system works by simply providing individual subtraction of the main carri-ers from the error signal and individual control of the subtraction process, for eachcarrier. This results in a number of effectively narrowband cancellation processestaking place, each of which should perform much better than a single broadbandcancellation. The resulting error signal will therefore look much more like thenear-ideal version shown in Figure 6.16(b). Using this signal to correlate with theoutput signal, or, better still, a carrier-reduced version of the output signal, willyield a much more meaningful control signal to control the final output subtractionprocess.

Clearly, this system relies upon the fact that the individual carriers arenarrowband relative to the overall spectral occupancy of the composite carrier spec-trum. If this is not the case, as would occur when transmitting two or three adjacentWCDMA signals, then the benefits obtained from the added complexity will besmall.

6.2.7.2 Carrier Injection

The second main compensation technique involves the injection of an additionalcarrier (or carriers) into the error loop, immediately prior to the main amplifier(although anywhere in that path will produce similar results). The level of this signalis usually significantly less than the level of the main input signal(s), 10 dB or 20 dBbeing typical.

The injected carrier will be amplified by the main amplifier and will pass to theoutput coupler via the time delay element in the usual manner. A sample of thecarrier will also be present in the error signal and will be amplified by the erroramplifier before being fed to the output coupler in anti-phase to its main-path coun-terpart. If the compensation loop is adjusted correctly, then this injected signal willbe cancelled at the final output, and hence the compensation circuitry must aim tominimise its level in the output signal.

This may be achieved by the use of a narrowband receiver tuned to the injectedcarrier frequency and hence receiving the residual carrier level. Some form of intelli-gent controller can then monitor the output of the narrowband receiver and adjustthe gain and phase components to minimise the residual carrier level. The configu-ration of this control strategy is shown in Figure 6.20.

There are a number of disadvantages with this technique. It does not help in anyway with the elimination of the wanted signals from the error signal. This must stillbe performed manually with the attendant problem of drift over time. The erroramplifier must therefore be made more powerful than is strictly necessary for therequired performance (or a different form of control must be used for this loop).

The injected carrier will intermodulate with the wanted signals in the mainamplifier and create additional unnecessary intermodulation products. Theseshould be eliminated from the final output by the action of the feedforward loop,but must still be amplified by the error amplifier, again adding to its power rating,allthough this addition is usually negligible.

Incomplete removal of the pilot is also a problem in some systems and anout-of-band pilot plus additional output filtering is sometimes employed. This isclearly an expensive and inefficient technique and also potentially erroneous as it


relies on the correlation between an out-of-band pilot and amplifier performancewithin the wanted band. This correlation will, at best, be limited.

The narrowband receiver is not, in general, coherent and hence the controllermust alternately adjust amplitude and phase and assess their effect on the output sig-nal continuously. The system must therefore hunt continuously to ensure that it iscorrectly adjusted. This process, in common with any incoherent ‘hill-climbing’technique, will yield a poorer performance than a coherent counterpart.

An example of this type of pilot-aided scheme has been patented by Myer [27].The intelligent controller in this case is provided by a decreasing step-size algorithm,although a microprocessor or digital signal processor could be used to provide asimilar function.

It is possible to employ a coherent detection system, based on the injected car-rier, and this provides improved performance.

Myer has also patented a modification to this scheme [28] in which adjustmentof the error loop components is also attempted. In this case the guarantee of at leastone input carrier within a prescribed frequency range is required in order to permitthe receiver and controller to detect and minimise its presence in the error signal.This obviously begins to restrict the generality of the feedforward system and henceis sacrificing one of its major advantages, although if this restriction can be toleratedin a given application (mobile radio base stations in the case of the Myer patent)then the technique can be made to work adequately. The use of SDR techniques helpto ease this problem, however, as the transmitter will have knowledge of the loca-tion of all of the carriers it is required to transmit. Since this transmitter’s design andmanufacture are likely to be undertaken by a single company and/or design group,this carrier knowledge can be put to good use in alleviating the issues raised by theabove restriction.

There are many variations on the pilot control technique, including frequencyhopping or spreading of the pilot, together with other forms of pilot modulation[29]. It is also possible to derive a pilot signal from the input signal, and such ascheme is detailed in [30].


τ

Mainamplifier

Timedelay

τTimedelay

Subtracter

Input

Output

Erroramplifier

Φ

Φ

Controlcircuits

Narrowbandpilot receiver

Localoscillator

Pilot tone

Figure 6.20 Compensation of a feedforward amplifier using pilot-injection techniques.

6.2.8 Relative Merits of the Feedforward Technique

Some of the advantages of feedforward as an amplifier linearisation technique aredetailed here for software defined radio applications.

1. Feedforward correction does not ideally reduce amplifier gain. This is incontrast to feedback systems in which linearity is achieved at the expense ofgain.

2. Gain-bandwidth is conserved within the band of interest. This is again incontrast to feedback systems which often require very wide feedbackbandwidths in order to provide the required levels of correction.

3. Correction is independent of the magnitude of the amplifier delays withinthe system. A high-gain RF amplifier will often have a significant groupdelay and this is potentially disastrous for any form of feedback system, dueto the large potential for instability.

4. Correction is not attempted based on past events, unlike feedback. Thecorrection process is based on what is currently happening rather than whathas happened in the recent past.

5. The basic feedforward configuration is unconditionally stable (assumingadequate coupler directivity [1]). This is one of the most importantadvantages and follows from the points raised above.

6. Cost is the main limiting factor to the number of stages (or loops) and hencethe level of correction which may be achieved, although size and efficiencymay also be important in some applications. In other words, an arbitrarilyhigh level of correction is possible, as there is no theoretical limitation on thenumber of times which feedforward correction may be applied. In an idealsystem, perfect correction could be achieved with just the basic systemshown in Figure 6.10; however, in reality, the error amplifier itself willdistort the error signal and this will appear directly at the output. Gain andphase matching throughout the system also affect the performance, as wasshown in Figure 6.11.

7. The error amplifier ideally needs only to process the main amplifierdistortion information and hence can be of a much lower power than themain amplifier. Thus, it is likely that a more linear and lower noise erroramplifier can be constructed. This in turn will result in a lower overallsystem noise figure.

8. Fault tolerance. In a single loop feedforward system, the failure of eitheramplifier will result in a degradation of performance and possibly alowering of the final output power; however the system will not failaltogether. In the case of a feedback system there is only one forward-pathamplifier, and if this fails, then the whole system has failed. If multiplefeedforward loops are used, then the overall system will degrade gracefully ifone or more amplifiers should fail.

Feedforward also suffers from some major disadvantages that have in the pastled to its relative unpopularity when compared with feedback. These may be sum-marised as follows:


1. Changes of device characteristics with time and temperature are notcompensated. The open-loop nature of the feedforward system does notpermit it to assess its own performance and correct for time variations in itssystem components. Thus, the performance of a basic uncompensatedfeedforward system can be expected to degrade with time.

2. The matching between the circuit elements in both amplitude and phasemust be maintained to a very high degree over the correction bandwidth ofinterest. The precise levels of matching required for a given level ofcorrection are shown in Figure 6.11.

3. Circuit complexity is generally greater than that of a feedback system,particularly with the requirement for a second (error) amplifier. This usuallyresults in greater size and cost.

6.3 Transmitter Linearisation Techniques

6.3.1 Digital Predistortion

6.3.1.1 Outline of Operation

Digital predistortion (DPD) is emerging as an enabling technology for many soft-ware defined radio systems and also for distributed wireless networks, such as thosedescribed in Chapter 1. While it is, of course, possible to add digital-to-analogueconversion and an upconverter to the input of an existing feedforward-based ampli-fier, this greatly complicates an already large and potentially expensive solution. Itis not realistic to mount such a system at the top of a wireless tower due to size,weight and reliability concerns. In the case of a digital predistortion system, how-ever, additional downconversion and one or more analogue-to-digital convertersare now eliminated from the RF-input/output, feedforward-equivalent solution1.The resulting structure is shown in Figure 6.21.

Digital, adaptive predistortion has long been a promising technique for thenarrowband linearisation of RF amplifiers. Like the Cartesian loop architecture, it isa complete transmitter linearisation technique, as the input signal information is atbaseband and the predistortion system incorporates the upconversion process.Another similarity to Cartesian loop lies in the use of quadrature signals forupconversion and downconversion, in addition to the actual predistortion processitself. The up/downconversion processes are increasingly provided in the digitaldomain, rather than as analogue circuitry, as this eliminates any quadrature errorand carrier leakage issues; these were discussed in Chapter 5. There are thus two setsof coefficients for the two quadrature channels, and both sets may be updated simul-taneously to take account of gain and phase non-linearities within the RF amplifierchain. Note that where the quadrature upconversion and downconversion processesare provided in the digital domain, the resulting digital IF input and output signalsrequire only a single data converter in each direction. This architecture will also bediscussed next.


1. An RF-input/output, feedforward equivalent PA, based on DPD, is a method of utilising a digitalpredistortion transmitter as a PA, with an RF input. The basic concept adds a downconverter and ADC(s) tothe input of the DPD transmitter shown in Figure 6.21.

The increasing speed of digital signal processing devices (DSPs, FPGAs, andASSPs), which can be used to realise the predistorter element, is now beginning toenable predistortion to be considered for wideband, multi-carrier applications, par-ticularly in 3G base stations. A DSP or FPGA device is now capable of performingthe rapid, complex multiplications and table look-up operations required if apredistortion system is to be employed successfully for significant broadband IMDreduction.

A basic form of quadrature baseband predistorter is shown in Figure 6.22. Thedigital signal processor contains the signal separation (into in-phase and quadraturepaths) and the complex weighting functions. These may be constructed in manyways, depending upon the amplifier model chosen (e.g., AM-AM, AM-PM, with orwithout memory, or combinations of these), but are typically formed from look-up

6.3 Transmitter Linearisation Techniques 263

Basebandinput

RF output

Φ

A/D

D/A

A/D

D/A

Digitalsignalprocessor

RF poweramplifier

0ºIn

90º

0ºIn

90º

Figure 6.22 Hardware schematic of a complete transmitter, employing adaptive basebandpredistortion in Cartesian components.

Digitallineariser

DAC Upconverter PA

DownconverterADC

Clock and LOSynthesisers

Figure 6.21 Structure of a digital predistortion linearised transmitter.

tables of complex weighting coefficients at various amplitude levels (for each of thequadrature channels). The look-up tables are accessed by an algorithm whichreceives as its input the fed-back downconverted RF output from the power ampli-fier. The coefficients in the look-up tables may then be updated in the light of the dif-ference between this downconverted signal and the input signal. This adaptionalgorithm has been the basis of much research and is an obvious area whereimprovements in both speed and accuracy enhance the practicality of the adaptivepredistortion technique.

An alternative, and also widely used option, is to form a polynomial approxima-tion to the inverse PA transfer function (in polar or Cartesian form) and to adapt thecoefficients of the polynomial in response to the feedback information. This approachwill typically require a greater number of multiplication operations to be performed,but should result in a smaller amount of memory being required (to store thecoefficients).

Note that although an RF phase shift is included in the local oscillator path inFigure 6.22, this function is often included in the form of a phase rotator at base-band (i.e., within the digital signal processing function) in many implementations. Itperforms a similar function to its counterpart in the Cartesian loop, namely, that ofcompensating for the phase shift between upconversion and downconversion causedby the finite time delay within the RF power amplifier. An alternative, often requiredin (broadband) base-station applications, is to employ a time-delay/ time-alignmentoperation prior to digital quadrature downconversion, within the digital processingfeedback path. Gross time alignment may be provided by imposing a number ofclock delays on the feedback samples, with fine-delay control then being providedby an equalisation filter.

The key difference between the structures shown in Figures 6.21 and 6.22 is thatthe former incorporates the quadrature upconversion and downconversion opera-tions within the digital signal processing and the latter adopts an analogue applica-tions. There are, however, many exceptions to these observations, and neither shouldbe treated as in any way binding.

6.3.1.2 Operation of a Digital Predistorter

Digital predistortion operates by forming a complementary non-linearity to that ofthe PA, in the form of either a look-up table (LUT) or a polynomial approximation(or a combination of the two). This non-linearity is typically contained within aDSP, FPGA, or ASSP and is updated in response to a feedback signal from the outputof the power amplifier. Updating can be based upon the minimisation of adjacentchannel energy, or upon coherent measurement of the error for each coefficient inthe LUT or polynomial approximation.

The signal processing architecture within the DSP block shown in Figure 6.22may be summarized as shown in Figure 6.23. A baseband voice or data input signalis converted to a suitable sampled I/Q format of the desired modulation scheme bythe voice/data coder. The I/Q signals then undergo a complex multiplication withthe relevant coefficients from the look-up table (or interpolated values derived fromit) before DC elimination (if required) and adaptive error correction (based on thedifference between the baseband I/Q and downconverted I/Q signals).


6.3Transm

itterLinearisation

Techniques

265

I/Q errorcorrection

Errorestimationand adaption

DC null andI/Q errorcorrection

From downconverterA/D converters

To upconverterD/A converters

I

Q

I

Q

IQ

Input signal(data or digitizedvoice)

Control path

Signal path

I

Q

Look-uptable

Real Imag( )LUTLUT QIf ,

LUTI

LUTQ

Table indexderivation

Complexmultiplication

UnwantedDCelimination

Voice ordata coder

Figure 6.23 Signal processing architecture for an adaptive baseband predistortion system.

The look-up table is improved by knowledge of its performance derived fromcomparing the original I/Q sampled signals with the equivalent I/Q downconvertedsample of the output signal. The accuracy and hence overall performance of the sys-tem are limited by the quality of this feedback signal. It is therefore essential to elimi-nate all known sources of error (e.g., DC offsets) or distortion from this signal; it isthus usually necessary to operate the downconverter mixers at a relatively low RFsignal level.

The adaption block may also be used to aid in the removal of DC offsets in themain processing path, to eliminate carrier leakage, for example, and also to optimizethe sample timing. The use of discontinuous feedback (i.e., periodic rather than con-tinuous updating of the look-up table coefficients) allows a higher level of correctiongain to be applied than could be accommodated in, for example, the Cartesian loop.This performance gain may be used either to allow a more non-linear and hencemore efficient RF power amplifier to be employed, or to provide a wider margin toaccommodate production spreads for an equivalent level of performance.

6.3.1.3 Alternative DPD Architectures

The digital predistortion architecture discussed above utilises both analogue quad-rature upconverters and downconverters. Analogue-to-digital and digital-to-ana-logue converter technologies have now reached the stage that, in many applications,it is possible to implement one or both of the quadrature upconversion anddownconversion functions digitally. The use of analogue up and downconversionelements has the advantage that the ADC and DAC sample rates are minimised,hence maximizing the available transmit and predistort bandwidths for a given con-verter technology or state-of-the-art performance, at a given point in time. This typeof architecture does, however, introduce a number of performance shortcomingswhich must be addressed:

1. DC offsets in the DAC outputs. These will manifest themselves as a carrierleakage signal at the centre of the upconversion band (assuming that thewanted signals are placed symmetrically around the LO frequency, as isrequired to obtain the maximum upconverted RF bandwidth from a givenconverter sample rate).

2. DC offsets/carrier leakage in the upconversion mixers. Again, these willappear as a carrier leakage signal at the centre of the upconversion band(with the same proviso as above).

3. Imperfect gain balance between the two DACs supplying the upconverter.This will manifest itself as an imperfect signal vector error (and hence anon-zero error vector magnitude). It will also result in an imperfect imagesuppression, which can result in unwanted carriers appearing on vacantcarrier frequencies when transmitting a non-symmetric frequency spectrum(as discussed in Section 5.3.1.1).

4. Imperfect gain balance in the analogue quadrature upconverter. This willhave the same effect as that in the DAC channels, as discussed above.

5. Imperfect quadrature in the analogue quadrature upconverter. This issuerefers to the fact that the quadrature local oscillator signals feeding the


upconversion mixers are likely to have other than a perfect 90° phasedifference between them. This will also result in the same signal vector errorand image-rejection issues discussed above.

6. Imperfect quadrature in the quadrature downconverter. Similarly, this issuerefers to the fact that the quadrature local oscillator signals feeding thedownconversion mixers are likely to have other than a perfect 90° phasedifference between them. This will result in two issues:• It will prevent the predistorter and associated digital signal processing

from correcting errors in the (analogue) quadrature upconverter.• It will result in a reduced predistortion performance (unless corrected) as

there will be an error between the input and feedback samples which doesnot result purely from the PA distortion.

7. DC offsets in the ADC inputs. These will also result in two issues:• They will manifest themselves as a carrier leakage signal at the centre of

the upconversion band (with the same assumptions as above for the equiv-alent DAC case and also assuming that the feedback signal is used as a ref-erence for correction of the upconverter DC offsets).

• They will also result in a reduced predistortion performance (unless cor-rected) as there will again be an error between the input and feedback sam-ples which does not result purely from the PA distortion. In this case, it isusually possible to use AC coupling or averaging and subtraction (effec-tively the same thing as AC coupling) to eliminate this problem for thepredistortion algorithm. It is worth noting, however, that in-band distor-tion, within the bandwidth of the AC-coupling highpass filter, will not becorrected by the predistortion algorithm.

8. DC offsets/carrier leakage in the downconversion mixers. These will resultin the same issues as discussed above for DC offsets in the ADC inputs.

9. Imperfect gain balance between the two ADCs supplying the down-converter. This problem will result in the same two issues as discussed abovein relation to quadrature errors, namely:• It will prevent the predistorter and associated digital signal processing

from correcting errors in the (analogue) quadrature upconverter.• It will result in a reduced predistortion performance (unless corrected) as

there will be an error between the input and feedback samples which doesnot result purely from the PA distortion.One further issue, if the feedback path is used as a reference to correct

errors in the quadrature upconversion path: It will manifest itself as animperfect signal vector error (and hence a non-zero error vector magnitude).It will also result in an imperfect image suppression, which can resultin unwanted carriers appearing on vacant carrier frequencies whentransmitting a non-symmetric frequency spectrum (as discussed in Section5.3.1.1).

10. Imperfect gain balance in the analogue quadrature upconverter. This willhave the same effect as that in the ADC channels, as discussed above.


11. Differential gain and phase ripple in the DAC outputs, reconstruction filtersor quadrature upconverter. This form of gain and phase error is much moredifficult to correct, even when using a perfect feedback reference (see Section6.3.1.4), and will result in similar signal vector error and image problems tothose discussed above. The simplest solution is, so far as is possible, toeliminate these ripple effects by good circuit design and component selection.It is, however, possible to correct them by utilising advanced digital signalprocessing techniques.

Some of these issues were discussed previously and, where relevant, the elementsrequired to reduce their effect are included in Figure 6.23.

6.3.1.4 Use of a Digital IF in the Feedback Path

The use of a digital IF in the feedback path eliminates many of the problems dis-cussed earlier (e.g., quadrature mismatch, DC offsets, and so forth) and hence pro-vides a perfect reference for the predistortion system (assuming that no distortionhas been introduced in the analogue domain, prior to A/D conversion). The architec-ture required for this solution is shown in Figure 6.24 and, in its basic form, it hasalready been discussed earlier in Section 5.3.1.1.


90º

0ºIn

D/A

I-channelDAC

Lowpassfilter

Lowpassfilter

Q-channelDAC

DSPRFoutput

On-channellocaloscillator

Off-channellocaloscillator

In

A/Dconverter

Mixer

Lowpassfilter

NCO

Digital IF(e.g. ~tens of megahertz)

Ideal quadraturereference signals

D/A

A/D

Digitalprocessingsubsystem

RF poweramplifier

90º

0º

Figure 6.24 Digital predistortion transmitter employing an analogue quadrature upconverter and a digitalquadrature downconverter.

When utilising this architecture in a digital predistortion system, the distortion(and noise) performance of the feedback path components becomes critical. It is nolonger possible to ameliorate the effects of in-band and IMD-band noise by filteringor averaging, since the full signal bandwidth is required by the predistortion table(or polynomial coefficient) update algorithm. The gain and phase flatness of thispath is also important, since any errors will impact (ultimately) upon the convergedpredistorter performance.

The use of a digital quadrature downconverter allows the predistortion systemto have a perfect quadrature reference and this can be utilised to correct for quadra-ture errors in the upconverter path (including both deviations from a perfect 90 °phase difference for the signals feeding the upconversion mixers and any gain imbal-ance in the outputs of those mixers). Likewise, its perfect DC performance (i.e., lackof unwanted offsets) also allows this issue to be compensated in the upconversionpath. Overall, therefore, it is the preferred embodiment for a digital predistortionsystem.

The only major issue which needs to be considered is the available performance(and associated cost) of the feedback ADC. If the system is, for example, required totransmit four WCDMA carriers (i.e., a total bandwidth of approximately 20 MHz),then the required (minimum) feedback bandwidth will be 100 MHz, assuming thatall of the spectrum created by both third- and fifth-order IMD products must be cor-rected. Even if this bandwidth is just Nyquist sampled and is placed such that itslower end reaches down to DC at the ADC input (or an appropriate alias thereof),the required ADC sample rate will be 200 Msps. In practice, it will need to begreater than this value and such converters are currently both expensive and, lessimportantly, have a high power consumption. Significantly higher bandwidths,such as those often required in satellite systems, may well go beyond what is the cur-rent state of the art in this area, hence potentially requiring the use of analoguedownconversion (with its associated halving of sample rate).

The cost issue is, however, not all one-sided in the case of the architectureshown in Figure 6.24. Where a relatively narrowband system is being considered(i.e., one in which the ADC requirement is far from state-of-the-art), then it may beadvantageous, in cost terms, to adopt a single ADC architecture. The single ADCrequired may well have a lower cost than would two devices at half its sample rate,since packaging and other production/testing costs may dominate the R&D pay-back and yield issues which usually make state-of-the-art components expensive.

6.3.1.5 Use of a Digital IF in Both Upconversion and Feedback Paths

A digital predistortion transmitter architecture employing both digital up anddownconversion is shown in Figure 6.25 (a more detailed version of Figure 6.21).This architecture has a number of advantages over the configuration described inthe previous section (Figure 6.24):

1. Only a single DAC is required, and hence also a single reconstruction filter,upconversion mixer, and so forth.

2. The quadrature upconverter is perfect; hence, it has no unwanted carrierleakage or quadrature errors (including gain mismatch). It therefore has a


perfect image rejection and no appreciable signal vector error (ignoringquantisation effects).

3. The NCOs can be retuned very rapidly, thereby enabling fast frequency-hopping to be provided with ease (within the band of interest and bandwidthcapability of the DAC).

The primary disadvantages are, again, those of the cost of the DAC and its per-formance limitations, based on the current state of the art at any given point in time.In a digital predistortion application, the DAC must reproduce the wanted spectrum,including the IMD correction bandwidth, and must do so at an appropriate interme-diate frequency, such that upconversion may be effected with realistic filtering. Thearchitecture shown in Figure 6.25 shows only a single analogue upconversion processand therefore assumes typically that the DAC output band, selected by the firstbandpass filter, appears in a zone other than the first Nyquist zone. This will thenallow the second bandpass filter (that following the analogue mixer) to have a realis-tic chance of providing the required image rejection (possibly in conjunction with thenatural bandpass characteristic of the PA matching networks). Alternately, adual-conversion architecture can be employed with the DAC operating in its first (ora higher) Nyquist zone. This architecture is shown in Figure 6.26.

Note that the use of a DAC output IF in a zone higher than the first Nyquist zonewill result in a frequency-response roll-off based on the DACs sin(x)/x response, asshown in Figure 5.10(c). This may be compensated by means of a digital filter withan appropriate inverse response, although a small amount of DAC dynamic rangewill inevitably be sacrificed by this process.


90º

0ºInDSP RF

outputNCO

90º

0ºIn

IF inputADC

Mixer

Lowpassfilter

NCO


Digital IF(e.g. ~tens ofmegahertz)

Ideaquadraturereferencesignals

A/D


IF outputDAC

D/A

Bandpassfilter

Mixer

Bandpassfilter

RF poweramplifier


Figure 6.25 Digital predistortion transmitter employing a digital quadrature upconverter and a digitalquadrature downconverter.

6.3.1.6 Memory Correction

The term memory effects refers to a collection of effects within a power amplifierwhich individually, or together, cause the output power level at a given input powerlevel to vary based upon the previous recent history of the input level. A simple,memoryless (AM-AM and AM-PM) amplifier model cannot therefore be used asthe basis for the predistortion of such an amplifier and more advanced techniquesare required.

Memory effects can arise from both thermal changes within the die of the semi-conductor and from imperfections in the gate (or base) and drain (or collector) biascircuitry. The former will typically dominate at low envelope frequencies (bearingin mind the die size)—say, up to hundreds of kilohertz; the latter will dominate athigher envelope frequencies. Of course, a poor design of decoupling circuit, such asmay be present on a hybrid power module, for example, may well have decoup-ling-based memory effects as its dominant problem throughout the envelopefrequency range of the input signal.

A detailed discussion of memory effects is beyond the scope of this book and isalready covered in the literature [31]. It is important, however, to either compensatefor memory effects in the design of the predistortion algorithm or, alternatively, toimprove the design of the decoupling circuitry such that memory effects are mini-mised. In practice, a combination of these two techniques is typically utilised.

6.3.1.7 Crest Factor Reduction

The peak-to-mean ratio of a signal can have a significant impact upon the cost andpower efficiency of a transmitter. The widespread use of CDMA signals, with anintrinsically high peak-to-mean ratio, has led to significant research being directedtoward the design of methods of reducing the signal peaks, while maintainingacceptable adjacent-channel and EVM performance. Both of the main 3G wirelessstandards, WCDMA and CDMA2000, can benefit significantly from these tech-niques, termed crest-factor reduction (CFR) algorithms.

These algorithms typically operate by removing the peaks (e.g., by hard-limit-ing the signal) and then removing the adjacent-channel energy, which this limitingprocess creates. Care must be taken in this latter process that the filtering operation,for example, which removes the adjacent-channel energy, does not also restore thesignal peaks (or a significant proportion of them). Some peak restoration will, how-ever, typically take place with most algorithms. Note that in most cases, no attemptis made to remove the in-band or in-channel distortion energy created by the clip-ping process. This is effectively the quid pro quo for achieving a reduction inpeak-to-average ratio (PAR) for the signal.

These processes lead to a compromise in all CFR algorithms, between achiev-able PAR, error vector magnitude for the wanted signal(s) (caused by the additionalin-channel distortion), implementation complexity, and propagation delay throughthe algorithm. The goal of any good CFR algorithm is to achieve:

1. Low PAR;2. Low (or acceptable) EVM;3. Low implementation complexity (and hence low cost);


272Linearisation


pp

lied toSD

RTransm

itters

InDSP RFoutput

NCO

90º

90º

0º

0º

In

IF inputADC

Mixer

Lowpassfilter

NCO


Digital IF(e.g. ~tens of megahertz)


A/D


IF outputDAC

D/A

Bandpassfilter

Mixer

Bandpassfilter

RF poweramplifier


Mixer

Bandpassfilter

IF amplifier


Figure 6.26 Digital predistortion transmitter employing a dual (analogue) upconversion architecture with a digital quadrature upconverter and a digital quadraturedownconverter.

4. A small propagation delay—important as it is a contributor to the overallbase-station signal processing delay and hence, ultimately, to the achievabletransmission range

As an illustration of the effects of hard clipping on a high PAR signal, considerFigures 6.27 through 6.30. These figures illustrate the impact of a range ofhard-clipping levels on 3GPP WCDMA signals and are measured, rather than simu-lated, values from a practical transmitter design. The hard-clipping is implementeddigitally within the DSP block and no restorative filtering is employed. The clippingis applied after the root-raised cosine filtering within the transmitter (as this wouldbe likely to act to restore some of the peak energy).

The main point to note from these figures is that even at a clipping level of 5.5dB, both the EVM and peak code domain error values are well within the 3GPPspecification requirements, allowing a significant margin for other system errors(e.g., LO phase noise, quadrature error in the upconverter, and so forth). At thislevel, however, and indeed at much higher PAR levels, both adjacent-channel andmask specifications are significantly compromised, hence the need to utilise filteringor other techniques to allow these specifications to be met.

6.3.1.8 Power Efficiency and Cost Issues

Power consumption is a key issue in handset applications and the requirement, inmany of the newer communications standards, for wide transmission bandwidths,leads to the potential for high power consumption in the ADCs and DACs required


5 6 7 8 9 10

Peak-to-mean ratio (dB)

−50

−45

−40

−35

−30

Adj

acen

t-ch

anne

l pow

er(d

Bc)

Figure 6.27 Effect of hard-clipping on adjacent-channel power for a two-carrier WCDMA signal(3GPP test model 1, 64 users); circular points: first adjacent channel, square points: second adjacentchannel.

for a digital predistortion function. This, coupled with the associated high signalprocessing bandwidths, can lead to digital predistortion having a poor power effi-ciency unless careful design is applied in this area.


5 6 7 8 9 10Peak-to-mean ratio (dB)

0

2

4

6

8Er

ror

vect

orm

agni

tude

(%)

Figure 6.28 Effect of hard-clipping on error vector magnitude for a WCDMA signal (3GPP testmodel 3); circular points: 64 users, square points: 100 users.

5 6 7 8 9 10Peak-to-mean ratio (dB)

−50

−40

−30

Rela

tive

spec

tral

pow

er(d

Bcin

a30

kHz

band

wid

th)

Figure 6.29 Effect of hard-clipping on the spectrum emission mask at a 4-MHz offset, for a WCDMAsignal (3GPP test model 1, 64 users).

Conversely, in a base-station application, digital predistortion techniqueswill typically provide a greater level of power efficiency than that available fromtraditional feedforward systems, although there are inevitably exceptions to thisstatement. Digital predistortion is also typically a lower-cost technique thanfeedforward. This is due to a number of factors, including:

1. Requirement for only a single RF PA—feedforward also requires an erroramplifier.

2. Simpler mechanics (typically)—less screening is generally required betweensubsystems and there is only one PA to consider from a thermal managementstandpoint.

3. Many of the elements required in a digital predistortion system already existwithin a base-station transmitter (DACs, upconversion, and so forth) andhence the added cost of DPD in a typical base station is relatively small(largely that of the control/feedback path components and additional digitalsignal processing).

4. There is no requirement for a high-power delay-line (or filter delay-line); thisis typically an expensive element of a feedforward system.

For these reasons, digital predistortion is becoming a popular technique for usein base-station transmitter systems.


5 7 9 11Peak-to-mean ratio (dB)

−56

−52

−48

−44

−40

Peak

code

dom

ain

erro

r(d

Bc)

Figure 6.30 Effect of hard-clipping on peak code domain error for a two-carrier WCDMA signal(3GPP test model 3); circular points: 64 users, square points: 100 users.

6.3.2 Relative Merits of Predistortion Techniques

Some of the advantages of predistortion as an amplifier or transmitter linearisationtechnique are detailed next for software defined radio applications.

1. Good wideband performance can be achieved from very simple circuitry(with analogue RF predistortion).

2. High levels of linearity improvement (greater than 25 dB) may be achievedover wide instantaneous bandwidths (greater than 20 MHz) with digitalpredistortion techniques.

3. Very wide instantaneous bandwidths and operating bandwidths which arewider still (multi-octave) may be achieved with analogue RF predistortion[32].

4. Gain bandwidth is conserved within the band of interest. This is in contrastto feedback systems that often require very wide feedback bandwidths inorder to provide the required levels of correction.

5. Correction is independent of the magnitude of the amplifier delays within thesystem. A high-gain RF amplifier will often have a significant group delayand this is potentially disastrous for any form of feedback system, due to thelarge potential for instability.

6. Correction is not attempted based on past events, unlike feedback. Thecorrection process is based on what is currently happening rather than whathas happened in the recent past.

7. An open-loop predistortion system is unconditionally stable, and evenclosed-loop systems are easily made stable. This is due to the effectively verynarrow bandwidth of the feedback control system.

Predistortion also suffers from some disadvantages which can limit its applica-bility in some systems. These may be summarised as follows:

1. Predistortion must, in general, take place at a low power level, as the devicesand signal processing required are usually only available at such powerlevels. This is generally only a significant issue in booster type applicationswhere a significant power may be available from the input signal. With mostpredistorters, this power must be attenuated to a low level before supplyingthe predistorter. This is clearly wasteful and hence potentially expensive.

2. Changes of device characteristics with time and temperature are notcompensated (other than in adaptive systems). The open-loop nature of thepredistortion system does not permit it to assess its own performance andcorrect for time variations in its system components. Thus the performanceof a basic (uncompensated) predistortion system can be expected to degradewith time (as with feedforward).

3. The matching between the circuit elements in both amplitude and phasemust be maintained to a very high degree over the correction bandwidth ofinterest. The levels of matching required are similar to those of feedforward,although in the case of baseband and IF predistortion systems, these mustalso be maintained in upconversion and filtering stages, which can be


difficult. Alternatively, digital filtering may be applied to counter the effectsof these issues, in a digital baseband predistortion system.

6.3.3 Feedback Techniques

Feedback techniques have been in use for audio and other narrowband applicationsfor a number of years. Their popularity has been largely due to their excellent dis-tortion reducing properties and relative simplicity. Such techniques, generally in theguise of the Cartesian loop, have also found application in software defined radiosystems and indeed some of the earliest examples of a software defined radio archi-tecture employed this type of transmitter [33].

The feedback techniques which are of primary interest in software defined radioapplications are the polar loop and the Cartesian loop. Both of these techniquesattempt to correct for both amplitude and phase distortions within the RF poweramplifier and may be fed with signals generated digitally at baseband. In both cases,the baseband signal processing may also be used to compensate for imperfections inthe analogue parts of the transmitter. The removal of unwanted carrier leakage(particularly in the Cartesian loop) and unwanted images are both possible withappropriate baseband compensation.

6.3.4 RF Feedback

The two simplest and most common forms of passive RF feedback are similar totheir audio frequency counterparts, namely, series feedback and shunt feedback.Both are concerned with linearising an individual stage, rather than a complete mul-tistage amplifier and both are extremely simple to implement.

They may be applied to linearise class-A, class-AB, or class-B stages and hencewill not result in a high efficiency amplifier. However, the improvement in distor-tion performance is stable and predictable and the relative simplicity of the twomethods makes them popular for high-reliability applications.

They are most often applied to correct for linear distortion (i.e., gain and phaseripple) in broadband amplifiers and also to provide gain stabilisation for a design,where a particular level of gain is required for a large number of production units, forexample. They are not generally applied to reduce IM distortion due to the accompa-nying gain reduction and its associated cost implications for the driver stages. A stagewhich has only 14 dB of gain (typical for a 2-GHz RF power transistor) will haveonly 4 dB of gain following the application of 10 dB of RF feedback. Most outputstages require more that 10 dB of IMD improvement in order to meet specification,hence explaining the relative unpopularity of RF feedback in most applications.

A number of variants have been suggested to overcome this disadvantage. Theseinclude active feedback [34−36], difference-frequency feedback [37], and distortionfeedback [38]. They all result in relatively modest linearity improvements and henceare not generally suitable for software defined radio applications. Further informa-tion on each is contained in [1].

It is also possible to apply Cartesian compensation in order to improve the levelof feedback gain achievable from an RF feedback system [39]; however, this resultsin a system of similar complexity to a Cartesian loop. The addition of a further


upconverter, required in a software defined radio application, together with itspoorer IMD correction performance, again renders it less than ideal for this type ofsystem. Again, further information is available in [1].

6.3.4.1 Transmitter Architectures Employing RF Feedback PAs

It is possible to utilise a simple, RF feedback linearised PA, in a software definedradio transmitter. The basic architecture for such a system is shown in Figure 6.31.This is essentially a conventional transmitter architecture, with the PA linearised tothe required degree by an RF feedback technique. The key thing to note with thisarchitecture (and also with its feedforward equivalent) is that the upconversionchain must be sufficiently linear that the (linearised) PA dominates in the generationof adjacent-channel energy. A prudent design would place the IMD (and adja-cent-channel noise) generated by the complete upconverter (including the DAC) atleast 6 dB below that of the linearised PA, and more generally 10 dB or more.

For higher RF carrier frequencies, multiple stages of upconversion may berequired, as was highlighted in Chapter 5.

One of the advantages of this approach over, say, the Cartesian loop, is thatthere is no requirement for a quadrature feedback path, since the digital upconverterwill have perfect image rejection and carrier leakage suppression. This not onlypotentially reduces cost, depending upon the complexity and cost of the RF feed-back technique employed, but also removes the need for a high-specification quad-rature downconverter. Since it is this element of a Cartesian loop whichpredominantly determines the image-rejection and carrier leakage performance ofthe overall transmitter, it generally requires a good specification in these areas (inaddition to its obvious requirement for good linearity).

6.3.5 Envelope Feedback

The use of envelope (or modulation) feedback is a logical extension to the basicnotions of feedback in RF amplifiers. By returning the feedback problem to an essen-tially baseband frequency environment, many of the stability problems, althoughnot eliminated altogether, are considerably alleviated.


90º

0ºInDSP RF

outputNCO

Digital processing subsystem

IF outputDAC

D/A

Bandpassfilter

Mixer

Bandpassfilter

RF feedbacklinearised PA

Localoscillator

Figure 6.31 Transmitter subsystem employing digital quadrature upconversion and an RF feedbacklinearised PA.

Figure 6.32 shows a general schematic of an envelope feedback system, incor-porated into a polar-modulation SDR transmitter. Its operation is as follows. Thedigital signal processor generates separate amplitude and phase modulation wave-forms and these are each converted to analogue signals and reconstructed usinglowpass filters. The phase modulation signal phase-modulates the on-channel localoscillator synthesizer and the resulting signal forms the RF input to the modulationamplifier (or amplitude modulator). The modulation input of this amplifier (ormodulator) is formed by subtracting the AM-demodulated feedback signal from thewanted input amplitude modulation signal. The error signal resulting from this sub-traction forms the amplitude modulation signal to the modulation amplifier. Theamplitude and phase modulated RF output signal from the modulation amplifierthen feeds the RF power amplifier, the output of which is sampled to form the inputto the feedback path. The feedback path further attenuates the sample of the PAoutput signal and AM-demodulates it using, for example, an envelope detector; theresulting baseband waveform forms the feedback input to the subtracter, asdescribed earlier.

Note that this linearisation scheme operates on a complete transmitter, since theinput signal is now the required modulation and the output waveform generated, isan RF signal containing that modulation.

The most basic form of envelope feedback employs non-coherent (envelope)detection and therefore cannot compensate for phase distortions within the ampli-fier. This simple technique is thus most often employed in full-carrier AM transmit-ters, where detection will ultimately be performed by an envelope detector, andphase information is not required. It can also be successfully applied to amplifiers inwhich the AM-AM distortion dominates over the AM-PM distortion (by, say, 10dB). Some bipolar transistor amplifiers fall into this category, although manyMOSFET-based (e.g., LDMOS) amplifiers do not. More advanced derivatives ofthe basic technique preserve the phase information lost in the basic system by utilis-ing polar or Cartesian signal formats. Both of these will be described in detail in thefollowing sections.

The feedback bandwidth required of an envelope feedback transmitter willdepend upon the modulation format(s) employed in the transmitter. Some signal


DSP


BasebandoutputDAC

D/A

ModulationamplifierLocal

oscillator

BasebandoutputDAC

D/A

Lowpassfilter

Lowpassfilter

A

RF PARFoutput

Envelopedetector

1/K

Voltagedivider

Amplitudemodulationsignal

Phasemodulationsignal

Subtracter

Figure 6.32 Schematic of an SDR transmitter employing envelope feedback.

types can result in a very large feedback bandwidth being required, despite the mod-ulation bandwidth (at RF) being more limited. A good example of this is a two-tonetest, which has an envelope of the form of a full-wave rectified sinewave (see [1],Chapter 2). This waveform has a cusp as the envelope goes through its minimumand hence potentially a very wide bandwidth. It will consequently require a largeenvelope feedback bandwidth for complete linearisation.

6.3.6 Polar Loop

The polar-loop transmitter [40] is an extension of two previous linearisationschemes, namely, envelope feedback (described earlier) and envelope eliminationand restoration (see Section 6.4.1 for details on the transmitter equivalent of thistechnique). It overcomes some of their principal disadvantages and results in anextremely linear transmitter architecture.

A schematic of the transmitter is shown in Figure 6.33 (note that this is funda-mentally a transmitter, rather than an amplifier, linearisation technique). The RFsection of the transmitter is extremely simple and consists of a voltage-controlledoscillator (VCO) or voltage-controlled synthesiser, operating at the final output fre-quency, and an RF amplifier stage (or chain). The final stage of the RF amplifierchain forms the amplitude modulator, for correction of the distortions introduced inprevious stages (and its own). This aspect of operation is similar to that described forenvelope feedback.

The input to the transmitter is provided in amplitude and phase (polar) form asseparate envelope and phase-modulation signals. The phase modulation signal isused to phase-modulate a VCO or synthesiser, operating at a convenient IF, andthis, as will be described, forms one input to the phase correction loop.


RF PA

Attenuator

RFoutput

Downconverter

Synthesiser

Limiter

Modulationamplifier

VCO

Loopfilter

Demodulator

Differentialamplifier

Loopamplifier

Lowpassfilter

Phasemodulationinput

Amplitudemodulationinput

VCO Phasedetector

Figure 6.33 Polar-loop transmitter.

The input envelope signal is compared with a detected version of the output sig-nal and the resulting error signal feeds the final stage modulator. This is therefore abasic envelope feedback system. The AM detection process consists of a limiter anda coherent detector, with the limiter providing a constant-envelope, phase-modu-lated reference to coherently detect the amplitude modulation information presenton the feedback signal.

The output phase information (the output of the limiter mentioned earlier) issimilarly compared with the phase of the input signal (at an IF) and the resultingerror signal controls the VCO; the IF input signal to this process is formed from thephase modulation input to the transmitter and the IF VCO. The resultingphase-control portion of the system is therefore a simple phase-locked loop. Usingthese two independent loops, both the amplitude and phase of the transmitter’s out-put signal can be carefully controlled within independent feedback processes.

The analysis of the system may be separated into two parts, both of which arealready well understood. The amplitude correction loop is analytically similar to theenvelope feedback system described earlier and its analysis proceeds in a similarmanner (see [1], Chapter 4). The phase correction loop may be analysed byphase-locked loop techniques [41] and suitable choices made for the loop filter,VCO constant, and loop amplifier. When considering two-tone test signals, thesharp phase discontinuities inherent in that type of signal mean that a first-orderloop is ideally required.

These phase discontinuities result in a potentially wide feedback bandwidthbeing required for the phase-feedback loop. For similar reasons to those discussedearlier, with respect to envelope feedback, the envelope feedback loop bandwidthcan also be large. These high feedback bandwidth requirements are a major limitingfactor in the performance of the polar loop technique.

The polar loop transmitter has many advantages over earlier, incoherent feed-back linearisation schemes. Some of these advantages may be summarised asfollows:

1. Since the VCO and the RF modulator (which can appear prior to the finalamplifier stage) are included within the feedback loop, their linearityperformance is not critical. Low-cost modulators of virtually any type maytherefore be utilised without compromising the final system performance.

2. High-efficiency class-C amplifiers may be utilised in the RF chain,creating a power-efficient linear transmitter (but only in very narrowbandapplications).

3. The RF portion of the transmitter is very simple, as it contains only a VCOand high-efficiency power amplification, all operating at the final outputfrequency.

4. No upconversion is employed in the RF chain and hence image-rejectfiltering is not required.

5. The use of gate modulation is permissible in the final stage, despite itsinherently poor linearity, and hence a low-power modulating (differential)amplifier may be used.

6. The use of feedback means that the transmitter is insensitive to tuning,component aging, supply voltage variations, and so forth.


7. The technique is applicable to a wide range of narrowband modulationschemes and has been successfully applied to single-carrier GSM-EDGEapplications [42].

6.3.6.1 Application of the Polar Loop in a Software Defined Radio Transmitter

This polar loop technique lends itself well to application within a software definedradio transmitter. One configuration for such a system is shown in Figure 6.34 andits operation may be described as follows. Dealing first with the phase-modulationloop (which is essentially a phase-locked loop), this is formed from the phase detec-tor, VCO, amplifier chain, and feedback path (including the limiter). The inputphase modulation is generated in the digital processing subsystem and converted toan analogue modulating signal by the phase modulation DAC. For some signal types(as was noted earlier), this could be a very wideband signal and hence a high sam-pling rate DAC may be required. In the case of many modern digital modulation for-mats, however, this will not be the case, as they are designed to minimise the phasetransitions required between symbols, hence limiting the phase modulationbandwidth.

The analogue phase modulation signal is used to phase-modulate the channelsynthesiser for the transmitter, typically by applying modulation to the varactordiode used in the synthesiser VCO. The channel synthesiser operates at the finaldesired carrier frequency. This phase-modulated carrier signal forms one input tothe loop phase detector, with the other coming from a limited version of the feed-back signal, as will be described next.

The output of the phase detector feeds a loop filter and loop amplifier, which areused to set the loop dynamics to provide an appropriate response. The resultingerror signal drives the VCO, which also operates at the final carrier frequency. TheVCO output passes through the modulation amplifier (where it receives the requiredamplitude modulation, as described later) and is amplified to the desired outputpower, by the (quasi-linear) RF PA. Finally, the output of the PA is sampled by adirectional coupler, before being attenuated and limited to feed the other input ofthe phase detector. Limiting is required to remove the amplitude variations presenton the polar modulated carrier signal, to prevent unwanted AM detection from alsotaking place in the phase detector.

The amplitude loop is formed from the differential amplifier/loop filter, modu-lation amplifier/PA, feedback path, and demodulator. The input amplitude modula-tion signal is generated in the digital processing subsystem and converted to ananalogue modulating signal by the amplitude modulation DAC. Following lowpassfiltering, this signal forms one input to the loop differential amplifier. The otherinput of the differential amplifier, is formed from a coherent amplitude detection ofthe feedback signal, coming from the PA output sampling coupler. The coherentdetection process, in turn, takes place in the demodulator, which has, as its input sig-nals, the phase-modulated input carrier signal and the PA output feedback signal.Note that this differs slightly from the arrangement shown in Figure 6.33, as thatconfiguration utilised a limiter on in the feedback path to provide the reference sig-nal for the AM demodulation process. In the configuration shown in Figure 6.34, aphase-shifter (or delay line) may be required (as shown) to ensure that the AM


6.3Transm

itterLinearisation

Techniques

283

RF PA

Attenuator

RFoutput

Modulationamplifier

VCO

Loopfilter

Demodulator

Differentialamplifier/loopfilter

Loopamplifier

DSP


AmplitudemodulationDAC

D/A

Lowpassfilter

PhasemodulationDAC

D/A

Lowpassfilter

Synthesizer

Phasedetector

Limiter

Phasemodulationinput

ΦPhaseshifter

Figure 6.34 Polar loop transmitter with digital baseband signal generation.

detection process takes place coherently, with no phase offset between the referenceand feedback signals.

In this way, two independent feedback loops are formed: one for phase and theother for amplitude. Since these loops are operating on orthogonal signals, they canbe configured independently to match the amplitude and phase bandwidths of thedesired input signal set. When considering a multi-mode software defined radio, thiswill require the analysis of a number of different modulation schemes in terms oftheir amplitude and phase signal bandwidths, with a compromise set of loop param-eters being chosen to satisfy all cases. In some circumstances one or both of the loopsmay be disabled, such as where a constant-envelope modulation format is beingtransmitted (e.g., GMSK for the GSM or PCS bands).

6.3.7 Cartesian Loop

The Cartesian loop technique [43, 44] was first proposed by Petrovic in 1983 as asuperior form of modulation feedback transmitter. It was primarily designed for SSBtransmission, but has since been applied to many other linear and quasi-linear mod-ulation schemes.

A block diagram of the basic Cartesian loop transmitter is shown in Figure 6.35.The operational principle is similar to the polar-loop described earlier; however, thebaseband signal information is now processed in Cartesian (I and Q) form. Themodulating signal is provided in quadrature components by a DSP; typically thisprocess, or an equivalent data generation process, is performed digitally in softwaredefined radio applications. The resulting quadrature baseband signals are fed intodifferential amplifiers, which form the subtraction process in order to generate theerror signals and also incorporate the loop filtering process. In most practical


90º

0ºIn

90º

0ºIn

RF PA

AttenuatorBasebandop-amps

RFoutputDifferential

amplifiers andloop filter

Carrier frequencyoscillator

Basebandinputs

Φ Phase-shift

I-channel

Q-channel

Figure 6.35 Cartesian loop transmitter.

embodiments, the filtering process takes the form of an integrator (one for each ofthe I and Q channels) and the resulting loop is first order. These loop integrators canbe formed from the same differential amplifiers which are used for the subtractionprocess, thereby maintaining the hardware simplicity of the technique.

The outputs of the differential amplifiers are upconverted to RF utilising aquadrature RF oscillator. The resultant RF signals from the two paths are then com-bined to produce the complex RF output signal. This low-power RF signal is thenamplified by the quasi-linear power amplifier before feeding the output samplingcoupler and, subsequently, the antenna.

The output from the RF amplifier is sampled by a directional coupler andattenuated to a suitable level to feed the downconversion mixers. These mixers arefed with exactly the same local oscillator signals (appropriately phase-shifted) asthe upconversion mixers were and hence the upconversion and downconversionprocesses are coherent. The downconverted output signal forms the feedback pathto the differential amplifiers, closing the two loops. The orthogonal nature of thefeedback system means that the two feedback paths operate completely independ-ently, thus ensuring that both the AM-AM and the AM-PM characteristics arelinearised.

A phase-shift is required between the upconversion and downconversion pro-cesses and is provided in the local oscillator path feeding one or other of these com-ponents. The phase shift is adjusted to ensure that the upconversion anddownconversion processes are correctly synchronized, despite the finite time delayof the RF power amplifier (and any IF processing, if an IF is employed within theloop). Any error in the setting of this phase shift will degrade the loop phase marginand this issue is covered in detail in [1], Chapter 4.

The operation of the Cartesian loop has a number of advantages over that of thepolar-loop and these may be summarised as follows:

1. Removal of the need for a dynamic PLL/VCO. The requirement for a fastPLL to track the rapid phase changes which can occur in some linear signalsis no longer a problem. The consequent tracking and phase-error problemsare also eliminated. The PLL arrangement in the polar loop can also haveproblems tracking/locking at low envelope levels, such as those that occurwhen the IQ vector passes through zero. This will occur with a two-tone test,an SSB signal and with some digital modulation formats (e.g., 16-QAM).

2. The modulation process is reduced to a simple mixer, and the need for aseparate modulator at the final output frequency is eliminated.

3. Simplicity of implementation.4. Applicable to any modulation scheme.5. A standard hardware configuration results, which allows a flexible

approach to the choice of modulation scheme.6. Significant reduction (and equalisation) of the two feedback loop bandwidth

requirements. This is a key benefit of the Cartesian loop technique over bothenvelope feedback and the polar loop. It is this benefit which largelyexplains the popularity of the Cartesian loop technique and the relativeunpopularity of polar loop.


Although it is possible to generate the required baseband quadrature signals usinganalogue hardware techniques, this is an unnecessary added complexity and expensein a software defined radio application. A much better method is to use a DSP deviceto generate the modulation signals in a quadrature form and this approach has verymany advantages. It allows the required quadrature signals to be generated with avery high degree of accuracy, by means of a Hilbert transform filter and this methodhas been employed successfully in a software defined radio application [33].

6.3.7.1 Application of the Cartesian Loop in a Software Defined Radio Transmitter

The Cartesian loop technique lends itself well to application in a software definedradio transmitter. One configuration for such a system is shown in Figure 6.36 andits operation is straightforward, based on the earlier description of the basic Carte-sian loop. The required quadrature input signals are generated in the digital process-ing subsystem, based upon the desired modulation format. These signals areconverted to analogue form using the I-channel and Q-channel modulation DACs. Itis worth noting that, in general, these two DACs will require the same sampling rate,something not necessarily true (indeed, generally not true) for the polar loop trans-mitter described previously. The filtered output from these DACs then forms theinput to the subtraction/loop filtering op-amps of the Cartesian loop.

Note that Figure 6.36 is similar in most respects to the digital predistortiontransmitter shown in Figure 6.22—the primary difference (from a hardware per-spective) is that in the latter case, two analogue to digital converters are employed todigitize the feedback signals. It is therefore likely to be a more expensive techniqueand consume more power (due both to the ADCs and to the required higher perfor-mance digital signal processing components) than an equivalent Cartesian loop.


Φ

RFoutput

RFoscillator

Phase-shifter

RF PA

DSP


I-channelmodulationDAC

D/A

Lowpassfilter

Q-channelmodulationDAC

D/A

Lowpassfilter

90º

90º

Figure 6.36 Cartesian loop transmitter with digital baseband signal generation.

Predistortion is, however, capable of much higher operational bandwidths withmodern ADC and DAC components, whereas Cartesian loop will always berestricted in terms of its gain-bandwidth-delay product (see [1], Chapter 4).

Note also that the digital processing subsystem enables the input signals to theCartesian loop to be predistorted in terms of their gain and quadrature error. Thisallows any shortcomings in the image rejection performance of the (analogue)quadrature downconverter (and hence the whole of the Cartesian loop transmitter)to be compensated, leading to an improved signal vector error and/or image rejec-tion specification for the system as a whole (again, see [1], Chapter 4, for details onthe form of this predistortion).

6.4 RF Synthesis Techniques

RF synthesis techniques do not attempt to create the desired amplitude and phasemodulated RF signal at the input to the RF power amplifier, as with traditional lin-ear or linearised PA techniques. Instead, they intentionally create signals which canbe amplified using the switching classes of power amplifier (e.g., class-D, class-E,and class-S), thereby maximizing DC-RF conversion efficiency. The desired,high-power amplitude and phase-modulated output signal is generated by a combi-nation of the switching amplifier output signals at the output of the transmitter. Theefficiency benefits are thereby theoretically, at least, preserved throughout the trans-mitter. The detailed operation of these techniques is covered in [1] and only theapplication of them, within the context of a software defined radio, will be includedhere.

6.4.1 Polar RF Synthesis Transmitter

The polar RF synthesis (or envelope restoration) technique is derived from the enve-lope elimination and restoration (EE&R) technique [45]. The operation of a com-plete EE&R transmitter is, in many respects, simpler than that of the correspondingEE&R amplifier. The complete transmitter is shown in Figure 6.37.

The input signals are generated at baseband, as separate amplitude and phasemodulating signals, in a similar manner to that required for the polar loop transmit-ter (described in Section 6.3.6). This is comparable to the generation of the I and Qsignals required by the Cartesian loop transmitter (see Section 6.3.7) and may beperformed by a digital signal processor in a similar manner.

Generating the amplitude and phase (polar) signals by this technique removesthe need to modulate the carrier elsewhere in the transmitter architecture and alsoeliminates the requirement for a limiter and amplitude detector to perform the com-ponent separation process at the input. It is therefore an obvious way of realising theefficiency benefits of the EE&R technique in the context of a software defined radioarchitecture.

An alternative form of Polar RF Sythesis transmitter is shown in Figure 6.38.This configuration removes the requirement for the VCO (or synthesiser) generat-ing the phase-modulated carrier signal to operate directly at the carrier frequency.The operation of a VCO directly at the final carrier frequency is often undesirable,

6.4 RF Synthesis Techniques 287

as it is prone to unwanted pickup from the high-power output signal of the transmit-ter. This will typically result in unwanted modulation of the VCO, which will mani-fest itself as an increase in phase noise and hence a degradation in EVM (whentransmitting a digital modulation signal). The VCO may now operate at any conve-nient frequency and the operating channel frequency may be determined by a sepa-rate synthesiser. This arrangement is considerably more convenient, particularly forchannelised systems.

Any non-linearities present in the upconversion mixer, amplifiers, and filteringwill not affect the (in-band) output spectrum, since the signals being processed bythese components are constant-envelope. The only new concern is in ensuring thatthe unwanted mixer products fall outside of the bandwidth of the RF amplifier, orare suitably attenuated by the bandpass filter. This filter may be of any suitablehigh-Q design (including ceramic or crystal), since it is only required to processlow-power signals.

Figure 6.39 includes the use of a class-S switching amplifier to provide the drainmodulation for the RF power amplifier. The use of a class-S technique significantlyenhances the efficiency of the overall transmitter, since both amplifiers are now ofhigh efficiency. The pulse-width modulation (PWM) signal, required to drive theclass-S amplifier, may be generated directly by the digital signal processing function.This then eliminates the need for a wideband DAC and hence potentially saves cost.The sampling rate required for the class-S modulator will depend upon the quality ofthe transmit (bandpass) filtering employed in the system (and also on the lowpass fil-tering provided in the class-S modulator output), since filtering cannot easily beemployed on a channel-by-channel basis.


GS2( ) cost = [ω t t+ φ( )]c

S1( ) ( )t V t=

RF amplifier(nonlinear)

Baseband linearamplifier

GS1( )t S2( )tVDD

VCO/synthesizer

Amplitudemodulation signal

Mixer

Bandpassfilter

Localoscillator

Basebandinput

Digital signalprocessing

PM

AM

D/A

D/A

Figure 6.38 An envelope restoration transmitter incorporating an IF.

GS2 ( ) = cost [ω t t+ ( )]φc

S1( ) ( )t V t=

RF amplifier(non-linear)

Baseband linearamplifier

GS1( )t S2( )tVDD

VCO/synthesizer

Amplitudemodulation signal

Phasemodulation signal

Voice/datainput


PM

AM

D/A

D/A

Figure 6.37 An envelope restoration transmitter employing a conventional linear baseband poweramplifier as the envelope modulator.

Again, it is possible to utilise a separate channel synthesiser and upconverterarrangement, as shown in Figure 6.38, in this arrangement. The same set of issuesand design criteria will also apply here.

One of the key issues in an EE&R amplifier is that of equalising the delaybetween the envelope and phase modulation paths, to ensure that the signals arriveat the output with the correct time-alignment. Incorrect time alignment will result inthe introduction of intermodulation distortion and hence it must be eliminated sofar as is possible ([1, Chapter 7; 46]). In the case of an envelope restoration trans-mitter, this is relatively straightforward, as the relevant delays may be introduceddigitally; in a typical EE&R transmitter, delay-filtering or long lengths of coaxialcable are required. In most designs, the delay in the envelope path is much longerthat that of the phase-modulation path and hence the relevant delay must be intro-duced in this latter path, as shown in Figure 6.40. This is true even when an IF isimplemented in the upconversion path. Note that the delay could be introducedanywhere in the phase-modulation path, for example:

1. In the digital domain (as shown);2. Following the DAC (i.e., in the analogue baseband path);3. Within the IF (if present);4. In the RF path to the PA.

The difficulty and expense of implementation will, however, increase roughly inline with the position adopted in the above list, with number 1 being the least expen-sive and (typically) number 4 being the most expensive.


G


Class-Sswitchingamplifier

VDD

VCO/synthesizer

PWM (amplitude)modulation signal

Phasemodulation signal

Bandpassfilter

RFoutput

Basebandinput


PM

AM

D/A

Figure 6.39 An envelope restoration transmitter employing a class-S switching power amplifier asthe envelope modulator.

G


Class-Sswitchingamplifier

VDD

VCO/synthesizer

PWM (amplitude)modulation signal

Phase modulationsignal

Bandpassfilter

Basebandinput


τPM

AM

RFoutputD/A

Figure 6.40 Delay-compensation in an envelope restoration transmitter.

6.4.2 LINC transmitter

The LInear amplification using Nonlinear Components (LINC) technique was firstproposed by Cox in 1974 [47] as a method of achieving linear amplification atmicrowave frequencies—a feat which was virtually impossible at the time, due tothe lack of suitable linear devices in those bands. It followed on from work byChireix [48], who proposed a similar form of outphasing modulator in the 1930s.The intention of the LINC technique was to create a complete linear amplifier (i.e.,an amplifier with a linear input-output relationship, where the intermediate stagesof RF power amplification could employ highly nonlinear devices). It is, however,much more applicable now to linear transmitter systems, with the advent of DSPtechniques greatly simplifying the otherwise complex signal processing involved.

There are many potential advantages of utilising the LINC technique for appli-cation software defined radio transmitters:

1. The use of highly nonlinear RF amplifiers (e.g., class-C, class-D, class-E, andso forth) results in the potential for very high efficiencies indeed to berealised.

2. The technique is capable (theoretically, at least) of an ideal 100% efficiencyat all envelope levels of the output RF signal, that is, not just at full outputpower. Any degradation due to, for example, non-ideal components,practical power amplifier efficiencies and so forth will therefore be adegradation from an ideal 100% efficiency. This contrasts with, forexample, class-A amplification (with a maximum theoretical efficiency of50% at full output) or class-B amplification, with a maximum theoreticalefficiency of 78%.

3. The ability to use nonlinear devices permits the technique to be used at highmicrowave and millimetric-wave frequencies.

4. High-power phase-locked signal sources can also be employed by thetechnique. These are often easier to construct at high frequencies and withhigh efficiencies than amplifiers of equivalent power.

5. Many of the complexities of the technique, from a hardware perspective, canbe incorporated within the digital signal processing of a software definedradio. In particular, the generation of the required modulating signals (tocreate the two constant-envelope, phase-modulated signals which form thebasis of the technique) is greatly simplified by the use of DSP techniques, as ishighlighted later in this section.

The basic schematic of a LINC transmitter is shown in Figure 6.41. The desiredRF output signal is derived from a combination of two constant-envelope,phase-modulated signals, which are generated by digital signal processing andupconversion processes. Each of these two signals is fed to its own non-linear RFpower amplifier. The power amplifiers separately increase the power of these signalsby an identical amount, before feeding them to an ideal summing junction forrecombination. The resulting output signal from the summing junction is then anamplitude and phase-modulated carrier, with all of the unwanted portions of theoriginal constant-envelope signals having been cancelled out; this cancellation


process occurring in the output combiner. The result of this process will ideally con-tain no unwanted distortion products or other unwanted, out-of-channel emissions.

The desired output signal, Sout(t), is given by:

( ) ( ) ( )[ ]S t V t t tout c= +cos ω φ (6.22)

where V(t) is the amplitude modulation present on the signal, ωC is the carrier fre-quency and φ(t) is the phase-modulation component of the signal. The output signalis formed from two constant-envelope, phase-modulated signals, S1(t) and S2(t),where:

( ) ( )[ ]S t V t tc1 = +max cos ω ϕ (6.23)

and

( ) ( )[ ]S t V t tc2 = +max cos ω θ (6.24)

where:

( ) ( ) ( )ϕ φ αt t t= + (6.25)

and

( ) ( ) ( )θ φ αt t t= − (6.26)

For these signals to combine and produce the desired amplitude and phase mod-ulated output signal, the following relationships must also hold:

( ) ( ) ( )2 1 2S t S t S tout = + (6.27)

and

( ) ( )[ ]α t V t V= −cos max1 (6.28)


Non-linearamplifier

RF output

G

G

Non-linearamplifier

Localoscillator

Bandpassfilter

Bandpassfilter

DSP


IF-outputDAC

D/A

Bandpassfilter

IF-outputDAC

D/A

Bandpassfilter

S1(t) = Vmaxcos [ (t)]ω ϕt +c

G S t S t ( ) + ( )1 2S ( )t2 = Vmaxcos[ cω t t( )]+ θ

Figure 6.41 LINC transmitter.

Thus, these signals, S1(t) and S2(t), must be successfully and accurately generated(in the DSP) in order for the benefits of the LINC technique to be realised.

If the input signal is provided in quadrature form as:

( ) ( ) ( )s t s t js tI Q= + (6.29)

Then the two LINC component signals may be defined as:

( ) ( ) ( )( ) ( ) ( )

s t s t e t

s t s t e t1

2

= += −

(6.30)

where

( ) ( )( ) ( )( ) ( )

( ) ( )( )e t s ts t s t

js ts t s t

Q

I Q

I

I Q

= −+

− ++

−11

11

2 2 2 2(6.31)

Quadrature signal components are commonly provided by digital modulationformats and can be generated easily, using DSP techniques, for any modulation for-mat which can be described within the processing bandwidth of the DSP device(which could be an FPGA or an ASSP, in addition to a traditional DSP processor).

The LINC transmitter shown in Figure 6.41 incorporates the use of digital IFsfor the two signal paths, followed by conventional IF upconversion, filtering, and soforth. This architecture has similar implications for DAC performance to those dis-cussed previously (in terms of sample rates, sin(x)/x roll-off and so forth); however,as the signals are constant-envelope, phase-modulated waveforms, DAC linearitybecomes unimportant (other than, perhaps, in the generation of harmonic-relatedspurs). An alternative architecture is shown in Figure 6.42.

In this case, the DACs operate at baseband and generate the phase-modulatingsignals themselves. These signals are linear, that is, they will possess a full range ofenvelope variations and hence DAC linearity is an issue and must be appropriatelyhigh for the system in question. The phase-modulation signals then phase-modulate


Non-linearamplifier

RFoutput

G

G

Non-linearamplifier

VCO/synthesizer

DSP


Basebandoutput DAC

D/A

Lowpassfilter

Basebandoutput DAC

D/A

Lowpassfilter

VCO/synthesizer

Figure 6.42 Alternative form of the LINC transmitter, utilising baseband-output DACs and VCOs forupconversion/modulation.

the two VCOs to produce the familiar constant-envelope LINC signals; these arecombined, after power amplification, to generate the wanted linear signal. Theadvantages of this architecture, over that shown in Figure 6.41, are:

1. Lower sample-rate, baseband output DACs can be used, hence saving cost.2. No upconversion and associated filtering are required, again saving cost.3. High-power oscillators could be employed as the VCOs, hence reducing (or

eliminating) the number of stages in the power amplifiers.4. The DSP burden is also lower for this configuration.

The disadvantages of this architecture, over that shown in Figure 6.41, are:

1. The VCOs operate on the final output frequency and hence are prone topulling by the high-power output signal (as discussed previously forenvelope restoration transmitters). This can lead to spectral spreading, poorphase noise, and high EVM, unless adequate screening is employed.

2. Fabrication of good VCOs, with the desired characteristics (e.g., linearvoltage-to-phase conversion, flat frequency response, and so forth), may bedifficult at the required output frequency.

In an analogue implementation of LINC, the requirement to accurately generatethe cos−1 term in (6.7) is extremely problematic. The advent of digital signal process-ing has made this task relatively straightforward and hence the use of DSP tech-niques within a LINC transmitter has many advantages. The use of DSP techniquesmoves the limitation on linearity performance from the signal generation/separa-tion process to the gain and phase match which may be achieved in the RF path. Ifthis is maintained to a high degree, very good linearity performance may beachieved. Results reported in the literature [49, 50] indicate that two-tone IMD lev-els of −60 dBc (max) may be achieved in a practical implementation. The fact thatthe LINC architecture fits well with DSP implementation technique also makes itideal (from that perspective) for use in a software defined radio.

A major issue with DSP implementation is, however, the modulation signalbandwidths which must be generated. These are typically 10 or more times thebandwidth of the modulation to be transmitted (e.g., over 50 MHz for a singleWCDMA carrier). This is clearly a significant issue with wideband systems, as is themaintenance of the required amplitude and phase match for the two paths over sucha large bandwidth. For narrower bandwidth systems (e.g., GSM-EDGE), the signalprocessing and RF path bandwidths become more realistic and the issue thenbecomes more one of the combiner losses involved and the implementation of effi-cient combiner techniques. GSM-EDGE is also better here (than CDMA-based waveforms), as its relatively low peak-to-mean ratio (3.2 dB) should resultin lower losses in the cancellation process for the unwanted parts of the twoconstant-envelope, phase-modulated waveforms.

An example of the baseband signal processing required for a DSP implementa-tion of a LINC transmitter, employing quadrature upconversion, is given in Figure6.43. The equations defined by the look-up table have been outlined earlier [in(6.10)].


294Linearisation


pp

lied toSD

RTransm

itters

Digitalinputsignals

I

Q

Look-up table

I-channel Q-channel

11

22 −+

=QI

IIOUT

11

22 −+

−=QI

QQOUT

IQ

IOUTQOUT

In

90º

0º

90º

0º

In

Digital signal processing

NCO

Quadraturemodulator

Quadraturemodulator

D/A

D/A

Bandpassfilter

Bandpassfilter

IF-outputDAC

IF-outputDAC

Localoscillator

Bandpassfilter

Bandpassfilter

RF PA

RF PA

Combiner

RFoutput

Figure 6.43 Use of DSP in the generation of LINC signals.

6.4.3 Sigma-Delta Techniques

The use of sigma-delta modulation for RF amplification has been suggested in anumber of papers (e.g., [51–53]). The aim of the technique is, again, to allowhigh-efficiency amplification to be applied in creating an amplitude and phase-mod-ulated signal. Early work applied the use of bandpass sigma-delta modulation to theRF carrier. While this approach is clearly valid, the switching speeds required of thelogic within the modulator become extremely high for many mobile communica-tions frequency bands (e.g., the 1.9-GHz PCS and 2.1-GHz 3G bands). Such circuitsare expensive and difficult to realise and also consume significant power, leading todevice cooling issues. This type of technique is therefore potentially restricted (atpresent) to lower frequency applications.

An alternative option is shown in Figure 6.44. This figure shows the applicationof envelope sigma-delta techniques within a complete quadrature transmitter. Inthis system, it is the signal envelope that is sampled using the sigma-delta modula-tor, hence meaning that the maximum switching rate required of the digital logic,within the modulator, is now based upon the signal bandwidth. Since this switchingrate is many orders of magnitude lower than that required for a carrier-frequencysigma-delta modulator, the resulting circuitry is much simpler to implement andlower in cost and will have fewer cooling issues. Furthermore, the class-S amplifierdoes not need to maintain a good input match over a multi-octave bandwidth (aswas the case with a carrier-frequency sigma-delta modulator-based system)—thisamplifier is therefore much easier to design.

In the approach shown in Figure 6.44, the DSP generates the I and Q-channelwaveforms in a conventional manner and these are then converted into two binarystreams by the two three-level delta-sigma modulators. These sequences are then apulse-width modulated representation of the baseband I and Q waveforms. Theupconversion and combining process needs to ensure that the resulting combinedwaveform remains a two-level signal; a simple summation following upconversionwith a conventional quadrature local oscillator would yield a three-level waveform.One way of ensuring that the combined, upconverted signal retains the two-levelform of the I and Q channels is to time-duplex the signals entering the combiner. Asimple method of realising this is to multiply the I-channel by a 1010 mask and theQ-channel by a 0101 mask, for example, by modulating the I and Q channel local


Class-S poweramplifier

RFoutputDSP


1-bit delta-sigmamodulator

∆ Σ/

1-bit delta-sigmamodulator

∆ Σ/

Bandpassfilter

I-channel

Q-channel

Localoscillatorinput

Localoscillatorinput

Time-duplexingcombiner

Figure 6.44 High-efficiency transmitter employing bandpass sigma-delta techniques.

oscillator outputs with the relevant sequence. The resulting (combined) waveform isa pulse-width, quadrature amplitude modulated (PWQAM) waveform.

This binary waveform is then amplified by the class-S amplifier and the resultinghigh-power switching waveform is band-pass filtered to remove the out-of-bandswitching products. The resulting signal is then the desired high-power amplitudeand phase modulated carrier.

This technique has a number of potential advantages over the envelope restora-tion and LINC techniques discussed earlier:

• The only combining process required takes place at low power (and is, effec-tively, digital); hence, losses are unimportant.

• The class-S amplifier does not need to drive the drain (or collector) of another(RF) device, so there are no concerns about the linearity of this process, nor ofthe practicalities in achieving it.

• High-power baseband-frequency lowpass filtering is not required at the out-put of the class-S modulator. This process may, typically, involve relativelylarge and perhaps costly components (e.g., large inductors).

It also, however, suffers from some potential disadvantages:

• The switching frequencies involved, to ensure that all switching noise/prod-ucts appear well out of band (not just out of channel) and hence can be filtered,are still high for most current cellular systems (e.g., CDMA and WCDMA).

• High-quality, low-loss transmit filtering is required at the transmitter outputand this will be relatively expensive to provide. Although such filtering isalready a part of most transmitter systems, the specification of the filteringrequired in a system based upon sigma-delta techniques is likely to be morestringent than that required in the transmit section of a typical duplex filter.

• Leakage of high-power switching noise inside a handset, for example, may bea major issue and providing sufficient screening (e.g., of the receiver compo-nents) may not be practicable.

• The realisation of suitable high-power switching amplifiers is currently nottrivial using existing device technologies. This is particularly true for base-sta-tion applications, where it may be some time before suitable devices anddesigns become available.

6.5 Power Efficiency

Power efficiency is a crucial parameter in SDR systems, particularly those whichmust operate with 3G air interface standards, since their performance in this areawill be poorer than that of existing 2G transmitter solutions. Given that a transmit-ter must operate on a 3G standard, however, the fact that it is SDR compatibleshould not unduly impact its power efficiency relative to that of a 3G-only transmit-ter. In other words, there should not be a significant power penalty in adopting an


SDR approach to a 3G handset or base-station design, at least so far as the RFaspect of the transmitter is concerned.

In the case of 3G systems, power efficiency has been of particular concern forthe base station, due to the significantly poorer efficiency expected from this aspectof the system in the early network and system design studies undertaken forWCDMA. Existing GSM power amplifiers are generally in excess of 40% efficient,whereas early predictions for WCDMA PAs were in the vicinity of 3–5%. This is asomewhat distorted picture, since GSM PAs must be combined (since they are gen-erally single-channel) and this is often done passively—a very lossy process. Eventaking account of this, however, it was clear that PA efficiency was going to be amajor challenge for 3G systems.

Feedforward has proved to be an available and moderately efficient solutionand is used in a number of first generation 3G systems. It can typically achieve effi-ciencies of between 8% and 10% depending upon the peak-to-mean ratio of theinput signal and the precise specification it is expected to meet (assumed to havesome margin over that required by 3GPP). It is unlikely to significantly exceed thisfigure in the future (with conventional PAs), as it is close to its optimum perfor-mance level, having benefited from many years of commercial development.Predistortion, however, is still in the early stages of its development cycle and isalready capable of efficiency levels exceeding that of feedforward. Although the effi-ciency benefits may seem small in percentage terms (e.g., increasing from, say, 10%to 14% for early systems), this will still save around 86W per transmitter (i.e.,almost 260W total for a trisectored base station), assuming a 30-W mean outputpower from each PA-which typically translates to roughly 20W at the antenna.Developments are already underway which will significantly enhance the powerefficiency of predistortion systems and these should lead to better than a halving inpower consumption, relative to existing feedforward-based solutions (althoughthese are clearly also improving in efficiency).

6.6 Summary of the Relative Merits of Various Linear Amplifier andTransmitter Techniques

This chapter has covered a wide range of techniques in both power amplifierlinearisation and transmitter linearisation. This section is intended to briefly sum-marize some of the main characteristics and relative merits of these techniques. Thesummary is provided in Table 6.2. Note that this table does not cover every conceiv-able application of these techniques; it concentrates on the main application areasonly. For example, analogue predistortion can be applied at baseband; however, itrarely is in mobile communications systems, so this option is ignored in the table.

6.6 Summary of the Relative Merits of Various Linear Amplifier and Transmitter Techniques 297

298Linearisation


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Table 6.2 Summary of the Main Characteristics and Relative Merits of the Various Linear Power Amplifier and Transmitter Techniques Covered in this Book

CharacteristicClass-A orClass-AB PA

ModulationFeedback (e.g.,polar loop,Cartesian loop)

AnaloguePredistortion Feedforward

DigitalPredistortion LINC EE&R

Sigma-DeltaTechniques

Architecturetype

PA Transmitter PA PA Transmitter orPA

Transmitter Transmitter orPA

Transmitter

Input signaltype

RF Analoguebaseband

RF or IF RF Digitalbaseband

Digital baseband RF, analoguebaseband ordigital baseband

Digital baseband

Handset orinfrastructuretechnique?

Both Both Both Infrastructure Both Both Both (but mainlyinfrastructure atpresent)

Both (but mainlyinfrastructure atpresent)

Operationalbandwidth

Very wide Wide (primarilydetermined by LOrange andbandwidth ofquadraturecircuits)

Wide (primarilydetermined bybandwidth overwhich goodtransfercharacteristicmatching can beachievedbetween PA andpredistortionelement)

Wide (primarilydetermined bydelay filterbandwidth, ifapplicable, orRF PAbandwidths)

Wide (primarilydetermined byLO range andbandwidth ofquadraturecircuits, ifapplicable)

Wide (primarilydetermined by LOrange andbandwidth ofquadrature circuits,if applicable. Maybe determined byPA bandwidth ifsome types ofhigh-efficiency PAare used)

Very wide (ifapplied as a PAtechnique)

Wide (if appliedas a transmittertechniquefor thesame reasons asLINC)

Wide (primarilydetermined by theswitching speedcapability of thesystem)

Linearisationbandwidth

N/A Narrow (typicallytens or hundredsof kilohertz)

Fairly wide(typically 15% ofcenter frequency,but can be muchhigher)

Fairly wide(typically 15%of centerfrequency, butcan be muchhigher)

Fairly wide(typically tensof megahertzand increasingas ADC, DAC,and digitalprocessingtechnologyadvances)

Narrow (typicallytens or hundreds ofkilohertz, primarilylimited by therequirement forvery good matchingto achievecancellation)

Fairly wide(typicallymegahertz andincreasing asADC, DAC, anddigital processingtechnologyadvances)

Fairly wide (typicallymegahertz andincreasing as digitalprocessing technologyadvances)

6.6Sum

mary of the Relative M

erits of Various Linear Am

plifier and Transm

itter Techniques

299

Table 6.2 Continued.






Typicalefficiencycharacteristicsfor highlinearity(unaided PA)*

Poor (<10%) Good (up to 60%narrowband withclass-C PA)

Fair (510%region, withclass-AB PA)

Fair (515%region, withclass-AB PA)

Good (1020%region, withclass-AB PA)

Very good(potentially 40%+with class-C,class-D, or class-EPAs and losslesscombining or lowPAR waveform)

Very good(potentially40%+ withclass-C, class-D,or class-E PAand class-Senvelope PA)

Very good(potentially 40%+with class-C, class-D,or class-E PAs)

Relativecomplexity

Very low Low Very low High High, butgetting lower astechnologyintegration takesplace

High, but shouldget lower astechnologyintegration takesplace

High, but shouldget lower astechnologyintegrationtakes place

High, but should getlower as technologyintegration takesplace

Control schemerequired?

N/A No (inherent inthe feedbacksystem)

No (but can beused to improveperformance)

Yes (typically,but lowperformancesystems cansometimes dowithout)

Yes Yes Yes (typically,but lowperformancesystems cansometimes dowithout)

No (theoretically, butfew practical systemsexist to verify this)

Mainadvantages(not coveredabove)

Goodreliabilitydue to lowcomplexity

No setup onmanufacturerequired

Good reliabilitydue to low com-plexity

Basic techniqueis inherentlystablelittlechance ofinstability

Basic techniqueis inherentlystable

Inclusion ofother digitalfunctionality(e.g., crest-factorreduction) isstraightforward

Degree of pathmatchingrequired is muchlower than forLINC

Intensely digitaltechnique, hencegood potential forintegration in thefuture

300Linearisation


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Table 6.2 Continued.






Maindisadvantages(not coveredabove)

Very highheatdissipation

Potential forinstability (e.g.,due to poorantenna VSWRor componentfailure)

Difficult(complex) toachieve highlevels ofcorrection

Relatively largesize, due to delaylines andrequirementfor two PAs

Manufacturingsetup can bemore complexthan for othertechniques

Very high degreesof cancellation arerequired over a verybroad bandwidth(> 10 × channelbandwidth)—muchmore so than for,for example,feedforward; this isdifficult to achieveand maintain

Signal processingbandwidth requiredis > 10 × thechannel bandwidth

High signalprocessingbandwidths canbe required forthe envelope andphase signals forsome modulationschemes

Technique still in itsinfancy for RFtransmitters and PAs

* Unaided, in this context, refers to a lack of efficiency-boosting assistance, such as using envelope tracking or adaptive biasing. Using these techniques will improve upon the efficiency figures quoted here for systemsbased on class-AB amplifiers.

References

[1] Kenington, P. B., High Linearity RF Amplifier Design, Norwood, MA: Artech House,2000.

[2] Aihara, S., et al., GaAs FET Power Amplifiers as Substitutes for TWT Amplifiers in aMulti-Level QAM Digital Radio System, Proc. of International Conference on Communi-cations, Vol. 1, Seattle, WA, June 7−10, 1987, pp. 1.2.1−1.2.5.

[3] Kumar, M., J. Whartenby, and H. Wolkstein, Predistortion lineariser Using GaAsDual-Gate MESFET for TWTA and SSPA Used in Satellite Transponders, IEEE Trans. onMicrowave Theory and Techniques, Vol. MTT-33, December 1985, pp. 1,479−1,488.

[4] Egger, A., M. Horn, and T. Vien, Broadband linearisation of Microwave Power Amplifiers,Proc. of 10th European Microwae Conference, Warsaw, Poland, September 1980,pp. 490−494.

[5] Sun, J., B. Li, and Y. W. M. Chia, A Novel CDMA Power Amplifier for High Efficiency andLinearity, Proc. of 50th IEEE Vehicular Technology Conference, Fall 99, Vol. 4, September1999, pp. 2,044–2,047.

[6] Sun, J., B. Li, and M. Y. W. Chia, linearised and Highly-Efficient CDMA Power Amplifier,IEE Electronics Letters, Vol. 35, No. 10, May 13, 1999, pp. 786–787.

[7] Yamauchi, K., et al., A Novel Series Diode lineariser for Mobile Radio Power Amplifier,Proc. of IEEE Symposium on Microwave theory and Techniques, 1996, pp. 831–834.

[8] Yu, C. S., W. S. Chan, and W. L. Chan, 1.9GHz Low Loss Varactor Diode Predistorter, IEEElectronics Letters, Vol. 35, No. 20, September 30, 1999, pp. 1,681–1,682.

[9] Maeda, M., et al., Source Second Harmonic Control for High Efficiency Power Amplifiers,IEEE Trans. on Microwave Theory and Techniques, Vol. MTT-43, December 1995,pp. 2,952−2,957.

[10] Katz, A., and S. S. Moochalla, Non-Linearity Generator Using FET Source-to-Drain Con-ductive Path, U.S. Patent No. 5,038,113, August 6, 1991.

[11] Dorval, R., MMIC linearisers for C and Ku-Band Satellite Applications, IEEE MTT-SWorkshop on Advances in Amplifier linearisation, paper 7, June 8, 1998.

[12] Nazarathy, M., et al., Predistorter for High Frequency Optical Communication Devices,U.S. Patent No. 5,424,680, 1995.

[13] Blauvelt, H., et al., Predistorter for linearisation of Electronic and Optical Signals, U.S. Pat-ent No. 4,992,754, 1991.

[14] Grebliumas, J., et al., Microwave Predistortion lineariser, U.S. Patent No. 5,523,716, 1996.[15] Namiki, J., An Automatically Controlled Predistorter for Multilevel Quadrature Amplitude

Modulation, IEEE Trans. on Communications, Vol. COM-31, May 1983, pp. 707−712.[16] Nojima, T., T. Murase, and N. Imai, The Design of a Predistortion linearisation Circuit

for High-Level Modulation Radio Systems, Proc. of GLOBECOM 85, 1985,pp. 1,466−1,471.

[17] Bernardini, A., and S. DeFina, Analysis of Different Optimization Criteria for IFPredistortion in Digital Radio Links with Nonlinear Amplifiers, IEEE Trans. on Communi-cations, Vol. 45, No. 4, April 1997, pp. 421−428.

[18] Huang, W., and R. E. Saad, Residual Second Order Intermodulation Suppression in ThirdOrder Distortion Generators, IEEE MTT-S Conference Digest, Vol. 3, June 1998,pp. 737−740.

[19] Kenington, P. B., and R. J. Wilkinson, The Specification of Error Amplifiers for Use inFeedforward Transmitters, IEE Proceedings Part G, Vol. 139, No. 4, August 1992,pp. 477−480.

[20] Kenington, P. B., Efficiency of Feedforward Amplifiers, IEE Proceedings Part G, Vol. 139,No. 5, pp. 591−593, October 1992.

[21] Cavers, J. K., Adaptation Behavior of a Feedforward Amplifier Lineariser, IEEE Trans. onVehicular Technology, Vol. 44, No. 1, February 1995, pp. 31−40.


[22] Gerard, R. E. J., and G. N. Hobbs, Improvements in or Relating to Amplifiers, U.K. PatentNo. GB 2,107,540B, June 26, 1985.

[23] Bauman, R. M., Adaptive Feed-Forward System, U.S. Patent No. 4,389,618, June 21, 1983.[24] Olver, T. E., Adaptive Feedforward Cancellation Technique That Is Effective In Reducing

Amplifier Harmonic Distortion Products As Well As Intermodulation Distortion Products,U.S. Patent No. 4,560,945, December 24, 1985.

[25] King, N. J. R., Feedforward Amplifiers, U.K. Patent Application No. GB 2,167,256A (with-drawn), May 21, 1986.

[26] Kenington, P. B., et al., Apparatus and Method for Reducing Distortion in Amplification,U.S. Patent No. 5,157,345, October 20, 1992.

[27] Myer, R. E., Automatic Reduction of Intermodulation Products in High Power LinearAmplifiers, U.S. Patent No. 4,580,105, April 1, 1986.

[28] Myer, R. E., Feed Forward Linear Amplifier, U.S. Patent No. 4,885,551, December 5, 1989.[29] Kenington, P. B., J. P. McGeehan, and M. A. Beach, Spread Spectrum Pilot Tone for Distor-

tion or Instability Correction, U.K. Patent No. GB 2,273,622, June 22, 1994.[30] Kenington, P. B., A Feedforward Distortion Correction Arrangement in Which a Pilot Sig-

nal Is Derived from the Input Signal, U.K. Patent No. GB 2,335,811, September 29, 1999.[31] Vuolevi, J., and T. Rahkonen, Distortion in RF Power Amplifiers, Norwood, MA: Artech

House, 2003.[32] Kenington, P. B., S. J. Gillard, and A. E. New, An Ultra-Broadband Power Amplifier Using

Dynamically-Controlled linearisation, Proc. of IEEE International Symposium on Micro-wave Theory and Techniques, Anaheim, CA, Vol. 1, June 1319, 1999, pp. 355−358.

[33] Bateman, A., D. M. Haines, and R. J. Wilkinson, Direct Conversion Linear TransceiverDesign, IEE 5th International Conference on Mobile Radio and Personal Communications,Warwick, United Kingdom, December 1989, pp. 53−56.

[34] Perez, F., E. Ballesteros and J. Perez, linearisation of Microwave Power Amplifiers UsingActive Feedback Networks, IEE Electronics Letters, Vol. 21, January 1985, pp. 9−10.

[35] Ballesteros, E., F. Perez, and J. Perez, Analysis and Design of Microwave linearised Amplifi-ers Using Active Feedback, IEEE Trans. on Microwave Theory and Techniques, Vol. 36,March 1988, pp. 499−504.

[36] Pedro, J., and J. Perez, An MMIC linearised Amplifier Using Active Feedback, IEEE Inter-national Microwave Symposium Digest (MTT-S), Atlanta, GA, Vol. 1, June 1993,pp. 95−98.

[37] Hu, Y., J. Mollier, and J. Obregon, A New Method of Third-Order Intermodulation Reduc-tion in Nonlinear Microwave Systems, IEEE Trans. on Microwave Theory and Techniques,Vol. MTT-34, February 1986, pp. 245−250.

[38] Gajda, G., and R. Douville, A linearisation System Using RF Feedback, IEEE InternationalElectrical and Electronics Conference, Toronto, Canada, 1983, pp. 30−33.

[39] Faulkener, M., D. Contos, and M. Johansson, linearisation of Power Amplifiers Using RFFeedback, IEE Electronics Letters, Vol. 31, 1995, pp. 2023−2024.

[40] Petrovic, V., and W. Gosling, Polar-Loop Transmitter, IEE Electronics Letters, Vol. 15, No.10, May 10, 1979, pp. 286−288.

[41] Gardner, F. M., Phaselock Techniques, New York: Wiley, 1979, pp. 168−170.[42] Fergus, T. J., EDGE ModulationHow linearisation Improves Amplifier Performance, RF

Design, October 2002, pp. 18–30.[43] Petrovic, V., and C. N. Smith, Reduction of Intermodulation Distortion by Means of Modu-

lation Feedback, IEE Colloquium on IntermodulationCauses, Effects and Mitigation, Lon-don, England, April 9, 1984, pp. 8/1−8/8.

[44] Petrovic, V., Reduction of Spurious Emission from Radio Transmitters by Means of Modu-lation Feedback, IEE Conference on Radio Spectrum Conservation Techniques, September1983, pp. 44−49.


[45] Kahn, L. R., Single-Sideband Transmission by Envelope Elimination and Restoration, Proc.of IRE, Vol. 40, July 1952, pp. 803−806.

[46] Raab, F. H., Intermodulation Distortion in Kahn-Technique Transmitters, IEEE Trans. onMicrowave Theory and Techniques, Vol. 44, No. 12, December 1996, pp. 2,273−2,278.

[47] Cox, D. C., Linear Amplification with Nonlinear Components, IEEE Trans. on Communi-cations, Vol. COM−22, December 1974, pp. 1942−1945.

[48] Chireix, H., High Power Outphasing Modulation, Proc. of Institute of Radio Engineers,Vol. 23, No. 11, November 1935, pp. 1,370–1,392.

[49] Hetzel, S. A., A. Bateman, and J. P. McGeehan, LINC Transmitter, IEE Electronics Letters,Vol. 27, No. 10, May 9, 1991, pp. 844−846.

[50] Hetzel, S. A., A. Bateman, and J. P. McGeehan, A LINC Transmitter, IEEE Vehicular Tech-nology Conference, St. Louis, MI, May 19−22, 1991, pp. 133−137.

[51] Jayaraman, A., et al., Linear High-Efficiency Microwave Power Amplifiers Using BandpassDelta-Sigma Modulators, IEEE Microwave and Guided Wave Letters, Vol. 8, No. 3,March 1998, pp. 121–123.

[52] Iwamoto, M., et al., Bandpass Delta-Sigma Class-S Amplifier, Electronics Letters, Vol. 36,No. 12, June 8, 2000, pp. 1,010–1,012.

[53] Wang, Y., A Class-S RF Amplifier Architecture with Envelope Delta-Sigma Modulation,IEEE Radio and Wireless Conference, RAWCON 2002, August 11–14, 2002, pp.177–179.


Appendix A90° Phase-Shift Networks

A.1 General Structure

The general structure of a passive broadband 90º splitter network, based upon anall-pass filter configuration, is shown in Figure A.1. Its transfer function is of theform:

( )( )( )( ) ( )( )( )( ) ( )

F ss s s s

s s s s

n

n

=− − − −

+ + + +

α α α α

α α α α

1 2 3 2

1 2 3 2

K

K(A.1)

where the total network complexity of both the N and P networks is n. The valuesfor for the N and P networks are tabulated in Tables A.1 to A.8. The values inthese tables are normalised such that:

ω ωl u = 1 (A.2)

where ωl and ωu are the lower and upper angular frequency limits, respectively. Thenetworks derived from these tables yield an equiripple all-pass filter, with a 90ºphase difference between the two outputs (within the bounds of the upper and lower

305

R

R

Vs

N-network

P-network

R

Figure A.1 General structure of a passive broadband 90º splitter.

frequency limits defined above). As the filter complexity, n, is increased, the accu-racy of the quadrature increases (i.e., the ripple decreases) for a given bandwidth.Conversely, for a given phase ripple (error), the useable bandwidth increases.

Note that it is also possible to generate an active version of the network, basedupon operational amplifiers (or equivalent circuits) [1].

306 Appendix A

Table A.1 Pole-Zero Locations for a 90º Phase-ShiftNetwork, Where ωu/ωl = 1146

FilterOrder, n

Phase Ripple(Degrees) N P

6 6.84 43.3862 8.3350

2.0264 0.4935

0.1200 0.0231

8 2.12 59.7833 14.4159

4.8947 1.6986

0.5887 0.2043

0.0694 0.0167

10 0.66 75.8845 20.4679

8.3350 3.5631

1.5279 0.6545

0.2807 0.1200

0.0489 0.0132

Table A.2 Pole-Zero Locations for a 90º Phase-ShiftNetwork, Where ωu/ωl = 573.0

FilterOrder, n


6 4.99 34.3132 7.0607

1.9111 0.5233

0.1416 0.0291

8 1.39 47.0857 11.8249

4.3052 1.6253

0.6153 0.2323

0.0846 0.0212

10 0.39 59.6517 16.5238

7.0607 3.2112

1.4749 0.6780

0.3114 0.1416

0.0605 0.0168

A.1 General Structure 307

Table A.3 Pole-Zero Locations for a 90ºPhase-Shift Network, Where ωu/ωl = 286.5

FilterOrder, n


4 13.9 16.8937 2.4258

0.4122 0.0592

6 3.43 27.1337 5.9933

1.8043 0.5542

0.1669 0.0369

8 0.84 37.0697 9.7136

3.7944 1.5566

0.6424 0.2636

0.1030 0.0270

10 0.21 46.8657 13.3518

5.9933 2.8993

1.4247 0.7019

0.3449 0.1669

0.0749 0.0213

Table A.4 Pole-Zero Locations for a 90°Phase-Shift Network, Where ωu/ωl = 143.2

FilterOrder, n


4 10.2 13.5875 2.2308

0.4483 0.0736

8 0.46 29.3327 8.0126

3.3531 1.4921

0.6702 0.2982

0.1248 0.0341

10 0.10 37.0091 10.8375

5.1050 2.6233

1.3772 0.7261

0.3812 0.1959

0.0923 0.0270

308 Appendix A

Table A.5 Pole-Zero Locations for a 90° Phase- ShiftNetwork, Where ωu/ωl = 81.85

FilterOrder, n


4 7.58 11.4648 2.0883

0.4789 0.0918

6 1.38 18.0294 4.5017

1.6316 0.6129

0.2221 0.0555

8 0.25 24.4451 6.8929

3.0427 1.4432

0.6929 0.3287

0.1451 0.0409

10 0.046 30.7953 9.2085

4.5017 2.4248

1.3409 0.7458

0.4124 0.2221

0.1086 0.0325

Table A.6 Pole-Zero Locations for a 90° Phase-ShiftNetwork, Where ωu/ωl = 57.30

FilterOrder, n


4 6.06 10.3270 2.0044

0.4989 0.0968

6 0.99 16.1516 4.1648

1.5873 0.6300

0.2401 0.0619

8 0.16 21.8562 6.2817

2.8648 1.4136

0.7074 0.3491

0.1592 0.0458

10 0.026 27.5087 8.3296

4.1648 2.3092

1.3189 0.7582

0.4331 0.2401

0.1201 0.0364

Reference

[1] Bedrosian, S. D., Normalized Design of 90º Phase-Difference Networks, IRE Trans. on Cir-cuit Theory, June 1960.

A.1 General Structure 309

Table A.7 Pole-Zero Locations for a 90° Phase-ShiftNetwork, Where ωu/ωl = 28.65

FilterOrder, n


4 3.57 8.5203 1.6157

0.5387 0.1177

6 0.44 13.1967 3.6059

1.5077 0.6633

0.2773 0.0758

8 0.056 17.7957 5.2924

2.5614 1.3599

0.7354 0.3904

0.1890 0.0562

10 0.0069 22.3618 6.9242

3.6059 2.1085

1.2786 0.7821

0.4743 0.2773

0.1444 0.0447

Table A.8 Pole-zero locations for a 90° Phase-ShiftNetwork, Where ωu/ωl = 11.47

FilterOrder, n


4 1.31 5.9339 1.5027

0.5055 0.1280

6 0.10 10.4285 3.0425

1.4180 0.7052

0.3287 0.0959

8 0.0075 14.0087 4.3286

2.2432 1.2985

0.7701 0.4458

0.2310 0.0714

Appendix BPhase Noise in RF Oscillators

B.1 Leesons Equation

The theoretical phase noise performance of an RF oscillator is governed by Leesonsequation [1]. This appendix provides further details of this model and its implica-tions for oscillator circuit design.

B.1.1 SSB Phase Noise Characteristic of a Basic Oscillator.

The form of the phase noise characteristic exhibited by a typical RF oscillator (with-out external interference and hence spurs) is given in Figure B.1. This figure showsthe three main regions in the characteristic:

• Flicker noise: At low offsets from the oscillation frequency, flicker noise in theactive device dominates the phase noise characteristic. This is characterised bya 1/f frequency response and leads to a slope of 9 dB per octave [2].

• Leesons equation: At larger offsets, such that the 1/f noise component hasdecayed to an appropriate degree, Leesons equation applies, and the phasenoise characteristic decays at 6 dB per octave.

• Intrinsic noise floor: At still larger offsets, the intrinsic noise floor of the sys-tem dominates and this is flat with frequency. This may be set by the thermalnoise of the active device itself, that of subsequent amplification or other simi-lar mechanisms.

B.1.2 Leesons Equation

The level of SSB phase noise present in an oscillator output, as a function of fre-quency, in the region between ff and fl in Figure B.1, is given by Leesons equation:

( )N fFkT

AQ

f

fSSB m

L m

=

108 2

0

2

log dBc Hz (B.1)

where:

A is the oscillator output power level (W).

311

F is the noise factor of the active device, when operating at an output powerlevel of A.

k is Boltzmanns constant [= 1.38 × 10-23 (J/K)].

T is the temperature (K).

QL is the loaded Q of the oscillator-tuned circuit (dimensionless).

f0 is the frequency of oscillation (hertz).

fm is the frequency offset from f0 (hertz).

In practice, phase noise is the dominant source of noise close to carrier, whileAM noise dominates at larger frequency offsets.

It can be seen from this equation that:

• Doubling of the loaded Q of the oscillator resonant circuit improves phasenoise by 6 dB.

• Doubling of the oscillation frequency degrades the phase noise by 6 dB.• Increasing the output power of the oscillator improves the relative level of the

phase noise.• Similarly allowing the temperature of the circuit to increase will decrease

phase noise performance.• An ideal oscillator is therefore a high-output system, operating at a low tem-

perature and a low frequency (not usually a variable in most systems),designed with a high-Q resonant circuit.

References

[1] Robins, W. P., Phase Noise in Signal Sources, London, England: Peter Peregrinus Ltd.,1982, p. 53.

[2] Vizmuller, P., RF Design Guide, Norwood, MA: Artech House, 1995, Chapter 4.

312 Appendix B

Phase noise(dBc/Hz)

Offset frequency,(log scale, Hz)

fm

Flicker noise9 dB/octave

SSB phase noise(from Leesons equation)6 dB/octave

Noise floor(flat)

flff

Figure B.1 Phase noise density as a function of offset frequency for a theoretical oscillator.

Acronyms and Abbreviations

2G Second generation (referring to generations of cellular mobilecommunications standards)

3G Third generation (referring to generations of cellular mobilecommunications standards)

3GPP Third Generation Partnership Project (standards body for theWCDMA standard for 3G)

3GPP2 Third Generation Partnership Project (standards body for theCDMA2000 standard for 3G)

A/D Analogue-to-digital converterACM Adaptive computing machineADC Analogue-to-digital converterADI Analogue Devices (International)AGC Automatic gain controlALU Arithmetic logic unitAM Amplitude modulationAMPS Advanced Mobile Phone System (1G analogue cellular stan-

dard)ASIC Application-specific integrated circuitASIP Algorithm-specific instruction set processorBER Bit-error rateBTS Base-station transceiver systemC/I Carrier-to-interference (ratio)CAT5 Standard for twisted-pair cabling, often used for in-building

data communicationsCCM Configurable computing machineCD Compact discCDE Code-domain errorCDMA Code-division multiple access (modulation format adopted by

3GPP2 for its 3G standard, CDMA 2000, also used in IS-95cellular systems in the United States)

CFR Crest-factor reductionCPRITM Common public radio interfaceCW Continuous-wave (or, sometimes, carrier-wave)D/A Digital-to-analogue converter

313

D/C DownconverterDAC Digital-to-analogue converterD-AMPS Digital AMPS (2G digital cellular standard)dB DecibelDCR Direct-conversion receiverDCS Digital cellular system (GSM in the 1,800-MHz band, mostly

used in Europe)DDS Direct-digital synthesis (or synthesiser)DECT Digital equipment cordless telephone (EU short-range cordless

handset system)DMA Direct memory accessDNL Differential non-linearityDPD Digital predistortionDQPSK Differential quadrature phase-shift keyingDSP Digital signal processor (or digital signal processing)ECL Emitter-coupled logicEDGE Enhanced data(-rate) for GSM evolutionEE&R Envelope-elimination and restorationENOB Effective number of bitsETSI European Technical Standards InstituteEVM Error vector magnitudeFAR Flexible architecture radioFDD Frequency division duplexFET Field-effect transistorFFT Fast Fourier transformFIR Finite impulse responseFM Frequency modulationFPFA Field programmable function arrayFPGA Field programmable gate arrayFSD Full-scale deflectionGMSK Gaussian minimum-shift keying (modulation format used in

GSM)GPRS General Packet Radio ServiceGSM Global system for mobile communications (originally named

after the committee which defined the standard: GroupSpeciale Mobile)

GSPS Gigasamples per secondI/O Input/outputIC Integrated circuitICI Intercarrier interferenceIF Intermediate frequencyILP Instruction-level parallelism

314 Acronyms and Abbreviations

IM IntermodulationIMD Intermodulation distortionINL Integral non-linearityIP2 Second-order intercept pointIP3 Third-order intercept pointI-Q (or I/Q) In-phase and quadratureIR Image-rejectLC Inductor-capacitorLDMOS Laterally diffused metal-oxide semiconductorLIF Low intermediate frequencyLINC Linear amplification using non-linear componentsLNA Low-noise amplifierLUT Look-up tableMAC Multiply-accumulateMCPA Multi-carrier power amplifierMIN Matrix interconnect networkMIP(s) Million instructions per secondMIT Massachusetts Institute of TechnologyMMIC Monolithic microwave integrated circuitMOSFET Metal-oxide semiconductor field-effect transistorMSPS Megasamples per second (or millions of samples per second)MST Multi-standard terminalMVCE Mobile Virtual Centre of ExcellenceNCO Numerically controlled oscillatorNRE Nonrecurring expense (typically used to refer to the research

and/or development costs of an item)OAM&P Operation, administration, maintenance, and provisioningOBSAI Open base-station architecture initiativeOEM Original equipment manufacturerOFDM Orthogonal frequency division multiplexingPA Power amplifierPAR Peak-to-average ratioP-ASSP Programmable application-specific standard productPC Personal computerPCB Printed circuit boardPCDE Peak code domain errorPCN Personal communications network (name also given to GSM

in the 1,800-MHz band, mostly used in Europe)PCS Personal communications system (U.S. version of GSM in the

1,900-MHz band)PDC Personal digital cellular (Japanese 2G cellular standard)


PECL Positive emitter-coupled logic (ECL circuits which run from asupply of +5V and ground, similar to TTL)

PIN Positive-intrinsic-negativePLL Phase-locked loopPMR Private Mobile Radio (U.K./European name given to profes-

sional radio systems, such as those used by the police, taxi ser-vices, and security firms)

P-N [code] Pseudorandom code sequence, often used for spreading in aspread-spectrum system

PROM Programmable read-only memoryPWM Pulse-width modulation (or modulator)PWQAM Pulse-width quadrature amplitude modulatedQAM Quadrature amplitude modulation (e.g., 16-QAM)QPSK Quadrature phase-shift keyingRAM Random access memoryR-C Resistor-capacitorRCP Reconfigurable communications processorRF Radio frequencyRFPA Radio frequency power amplifierRISC Reduced instruction-set computerRMS or rms Root mean squareROM Read-only memoryRRC Root-raised cosineRRH Remote RF headRx ReceiverRZ Return-to-zeroS/H Sample and holdSAW Surface acoustic waveSDR Software defined radioSFDR Spurious-free dynamic rangeSINAD (ratio of) Signal to interference, noise, and distortionSMR Specialized Mobile Radio (U.S. name given to professional

radio systems, such as those used by the police, taxi services,and security firms)

SNR Signal-to-noise ratioSOTA State of the artSPD Six-port discriminatorSPDT Single-pole, double-throwSPN Six-port networkSSB Single-sidebandSVE Signal vector errorTDD Time-division duplex

316 Acronyms and Abbreviations

TDM Time-division multiplexTDMA Time-division multiple accessTETRA Trans-European trunked radio (EU PMR/SMR standard)TMA Tower-mounted amplifierTRx TransceiverTTL Transistor-transistor logicTx TransmitterU/C UpconverterUMTS Universal mobile telecommunications system (general term

given to 3G systems worldwide)VCO Voltage-controlled oscillatorVC-TCXO Voltage-controlled, temperature-compensated crystal oscillatorVSWR Voltage standing wave ratioWCDMA Wideband code-division multiple access (modulation format

adopted by 3GPP for its 3G standard)WWRF Worldwide Research ForumZIF Zero intermediate frequency (i.e., direct conversion)

- Delta-sigma (usually refers to a type of modulator, often usedin DACs and ADCs)


About the Author

Peter B. Kenington received his B.Eng. (with first-class honours) and Ph.D. from theUniversity of Bristol, United Kingdom, in 1986 and 1989, respectively. His Ph.D.work concerned the design of novel receiver systems for satellite communications.

From 1989 to 1990 he was employed as a research assistant at the University ofBristol, performing research on novel transmitter and receiver architectures as wellas on the EMC issues surrounding mobile radio technology. In 1990 he became alecturer and continued research on high-linearity RF amplifier and transmitter sys-tems and software radio techniques, in addition to performing many commercialdesign and consultancy contracts. In 1995, he jointly founded Wireless SystemsInternational Ltd., joining the company full-time in 1997. As the chief technologyofficer, he led the technology development activities of both the initial radio systemsconsultancy/design business and the subsequent linear RF power amplifier andtransceiver business until its acquisition by Andrew Corporation in 2002.

He is currently the director of advanced technology within the RF power ampli-fier group at Andrew Corporation and also holds the position of technical chair inthe Open Base Station Architecture Initiative (OBSAI).

Dr. Kenington received the Institution of Electrical Engineers (IEE) prize forOutstanding Academic Achievement in 1986, the IEE Mountbatten Premium in1989, and the IEE Engineering Science and Education Journal Premium in 1999. Hehas served on the IEE Professional Group E9 (Satellite Communications) and on theIEE Science, Education and Technology Divisional Board. He has also served onCISPR (International Special Committee on Radio Interference) and on the editorialboard of a number of scientific journals. Dr. Kenington is a chartered engineer, afellow of the IEE, and a senior member of the IEEE. He is the author of more than100 published papers and over 40 patents in the radio technology field. He is alsothe author of High Linearity RF Amplifier Design (Artech House, 2000). He may becontacted at [email protected].

319

Index

1/f noise, 733GPP2, 13516-QAM, 590° phase-shift networks, 311–15

general structure, 311–15passive broadband splitter, 311pole-zero locations, 312, 313, 314, 315

AActive all-pass filter, 216–17advantages/disadvantages, 217

defined, 216illustrated, 217

Adaptive algorithm, 264Adaptive Computing Machine (ACM), 40

architecture illustration, 41market-specific, 40

Adaptive nulling, 253–59alternative coherent detection, 257–59coherent detection, 256–57correction loop, 254energy minimisation, 254–56error loop, 253–54use of, 253

See also Performance stabilisationA/D converters, 10–11

analogue bandwidth, 52–53background, 41–42clock jitter and, 111–17communications architectures, 102–4component imperfections, 95dynamic range, 44, 45efficiency, factor of merit, 46–47factor of merit, 52flash converter architecture, 101generic, 42–43high-speed architectures, 101–4impedance matching, 91minimum theoretical power consumption,

48, 49, 50, 51noise, 90–92noise figure, 118–20performance, 42

performance assessment, 104–6performance trends, 51–53power consumption, 41–43, 51–52quantisation noise ratio, 44resolution, 53sample rate, 53SNR, 41–43specifications, 28–29spurii, reducing with dither, 107–9spurious signals, 97–107

See also D/A convertersAdjacent channel power ratio (ACPR), 240Algorithm-specific instruction set processor

(ASIP), 36–37Analogue predistortion, 234–44Analogue quadrature receiver design, 57–58Analogue quadrature upconversion, 186–94

error compensation, 187error compensation automation, 188EVM performance, 194I/Q gain, 187–90issues and mitigations, 187–94LO leakage suppression, 190–91LO phase noise, 193out-of-channel/band DAC, 191–93phase imbalance, 187–90

See also UpconversionAnalogue-to-digital converters.

See A/D convertersAntennas

smart, 18–22specifications, 27

Anti-parallel diode-based predistorters,241–44

defined, 241high-speed Schottky diodes, 244illustrated, 243matched diodes, 244

See also PredistortersAperture error, 110–11

defined, 110impact, 111

Application-specific integrated circuits (ASICs),32–33

321

Application-specific signal processors (ASSPs),32, 33, 201

Automatic gain control (AGC)level, 81switched, 80system design, 80

BBandwidths, 86

detection, 89feedback, 279–80linearisation, 186Nyquist, 88operational, 185–86

Baseband beamforming, 18Base-station model, 7–11Base-station transceiver system (BTS)

alternative digital processing options, 33–35digital interfaces, 7ideal model, 8new business model, 8–10radio parts, 10upgrade vs. replacement and, 10–11

See also BTS hotelingBroadband 90° splitter, 219–20Broadband quadrature networks, 215–29

active all-pass filter, 216–17applications, 215–16highpass and lowpass filters, 217–20introduction to, 216Lange coupler, 227–28multiplier-divider techniques, 228–29multi-zero, 225passive all-pass, 222–25phase splitter, 225–27polyphase filtering, 221–22BTS hoteling, 16–18advantages, 17–18deployment costs, 18introduction, 16maintenance, 17, 18network expansion, 18power consumption, 17reliability, 18remote RF head, 17

Business model, 7–13base-station, 7–11handset, 12–13introduction, 7OBSAI and CPRI, 11–12

Butler matrix, 19

CCalibration

DC, 67–69smart antenna issues, 21–22

Cancellationanti-phase, 153auxiliary transmitter, 157–58controlled, 152distortion, 249implementation options, 153–57multi-path, 157

Capacitive coupling, 67, 69Carrier frequency, 203Carrier injection, 259–60

defined, 259disadvantages, 259–60illustrated, 260modification, 260

Cartesian loop transmitter, 284–87advantages, 285application, 286–87block diagram, 284defined, 284illustrated, 286outputs, 285phase-shift, 285

See also Transmitter linearisationCascaded interception point, 93–94Cascaded non-linearity techniques, 178–79

illustrated, 179predistorter/postdistorter configuration, 178,

179predistortion configuration, 178, 179

Circulators, 146specifications, 27–28for transmit/receive isolation, 146

Civilian mobile communication, 2Clock jitter, 111–17

ADC SNR and, 114, 115combined noise performance and, 113–15conversion process effect, 112impact, 111–13oscillator phase noise impact, 115–16oscillator spurs impact, 116–17SNR and, 112, 113source, 111

Clock oscillator, 115–17phase noise impact, 115–16spurs impact, 116–17

Code-division multiple access (CDMA), 9, 143Coherent detection, 256–57

alternative, 257–59

322 Index

illustrated use, 257, 258Common Public Radio Interface (CPRI), 7,

11–12Configurable computing machine (CCM), 33Constant-envelope upconversion architectures,

210–15PLL-based directly-modulated VCO

transmitter, 211–12PLL-based input reference modulated

transmitter, 212–13PLL-based reference transmitter, 210–11PLL-based transmitter with modulated

fractional-N synthesis, 213–15Consumers, 13Correlation techniques, 256–57Costs

cooling, 31development time/resource, 31direct, 30feedforward correction and, 261interfacing device, 30NRE, 30tools/training, 30–31

Crest-factor reduction (CFR) algorithms,271–73

defined, 271goals, 271–73hard clipping and, 273–75

Cubic predistorters, 238–39defined, 238illustrated, 238

DD/A converters

component imperfections, 95drawbacks, 206dynamic range, 270high-speed, 197, 204–5imperfect gain balance between, 266interpolating, 194interpolating, structure, 197for LO leakage suppression, 192multi-carrier, 257RF, 205–9specifications, 29

See also A/D convertersDC offsets, 65–70

in ADC inputs, 267capacitive coupling, 67compensation, 66–70in DAC outputs, 266

DC calibration, 67–69

in downconversion mixers, 267effect of, 65frequency modulation, 66–67gain/phase error combination, 70–72servo control loops, 69–70static DC error, 65–66in upconversion mixers, 266

Detection bandwidth, 89Differential gain, 268Differential non-linearity (DNL)

in ADC transfer characteristic, 99in dynamic environment, 98–100dynamic problems, 107errors, 98, 99, 106, 107high-speed converter impact, 106input waveform effect, 100

Digital IF, 268–70in feedback path, 268–69in upconversion/feedback paths, 269–70

Digital IF receiver, 58–60architecture, 58–59digital processing, 59–60illustrated, 59multi-carrier architecture, 61

Digital IF upconversion, 198–99advantage, 199defined, 198illustrated, 199output, 199

See also UpconversionDigital predistortion (DPD), 262–77

advantages, 276alternative structures, 266–68cost issues, 273–75crest factor reduction (CFR) algorithms,

271–73defined, 262digital IF in feedback path, 268–69digital IF in upconversion/feedback paths,

269–70disadvantages, 276–77emergence, 262hardware schematic, 263memory correction, 271operation, 264–66power efficiency, 273–75relative merits, 276–77signal processing architecture, 265transmitter structure, 263

See also PredistortionDigital quadrature downconverters, 269, 272Digital quadrature upconverters, 269–70, 272

Index 323

Digital signal processors (DSPs), 31–32as enabling technology, 31LINC transmitter, 293, 294specifications, 29

Digital-to-analogue converters (DACs). See D/Aconverters

Diplexers, 141construction, 142disadvantages, 142–43elimination by cancellation, 152–58elimination configuration, 154, 155, 156frequency spacing, 142problem, 142–58problem example, 143size, 142spectrum inefficiency, 142–43switched, 145–46, 151–52use of, 142

Direct conversion receiversarchitecture illustration, 82baseband and digital IFs, 81–82baseband filter technologies, 81gain control element locations, 80multi-mode issues, 80–81second-order distortion effect, 77six-port network, 82–84

See also ReceiversDirect-digital synthesiser (DDS), 213Dither

for ADC spurii reduction, 107–9amount of, 109defined, 107

DNL errors and, 109out-of-band technique, 110

Divider modulated transmitters, 210–11Downconversion

alias, 88digital quadrature, 269, 272imperfect gain balance, 267mixers, DC offsets, 267

Duplexerselimination schemes, 146specifications, 27–28for transmit/receive isolation, 146

Dynamic range enhancement, 170–80cascaded non-linearity techniques, 178–79feedback techniques, 171–73feedforward techniques, 173–78

EEffective number of bits (ENOBs), 90Energy minimisation, 254–56

compensation using, 256correction loop, 255–56defined, 254second error signal generation, 256use of, 254

Enhanced FPGAs, 33Envelope elimination and restoration (EE&R)

technique, 287, 289Envelope feedback, 278–80

bandwidth, 279–80defined, 279non-coherent detection, 279schematic, 279SDR transmitter employing, 279

Envelope restoration transmitter, 287–89with class-S switching PA, 289defined, 288delay-compensation, 289with IF, 288input signals, 287with linear baseband power amplifier, 288

See also RF synthesis techniqueEnvironmental stabilisation, 251Equipment manufacturers, 12–13Error vector magnitude (EVM), 118, 120

average, 130comparison with predicted performance,

130–31example results, 127–31gain/phase errors effect, 122for gain/phase errors range, 131LO phase noise in, 125–27measured, 134measured results, 127–30measured vs. predicted performance, 134multi-stage system, 131–34PCDE relationship, 134–35phase noise influence on, 120–34plotting, 122–23total, 133transmitter, 194

European projects, 23

FFactor of merit, 51

A/D converter efficiency, 46–47for A/D converter ICs, 52

FastMATH processor, 40–41Feedback techniques (dynamic range

enhancement), 171–73advantages, 171–72defined, 171

324 Index

IF/RF feedback with vector subtraction,172–73

mixer linearisation, 172RF feedback, 172

Feedback techniques (transmitter linearisation),277–80

envelope feedback, 278–80RF feedback, 277–78

Feedforward amplifiers, 245–48basic configuration, 245cancellation, 248correction loop, 252correlation techniques compensation, 257correlation techniques control, 258directional coupler, 245disadvantages, 261–62environmental stabilisation, 251error loop, 252error signal, 245, 246fault tolerance, 261feedback control applied to, 253ideal system, 246illustrated, 245output, 247performance maintenance, 251–53performance monitoring, 252–53pilot-injection techniques compensation, 260power efficiency, 248–51, 297relative merits, 261–62two-tone test, 255

Feedforward linearisation, 244–45Feedforward techniques, 173–78

configuration, 174configuration illustration, 174defined, 173—74linearisation of cascaded front end, 176–78linearisation of LNA, 173–76noise factor, 175noise figure, 175

See also Feedback techniquesFET-based predistorters, 240–41

defined, 240non-linearity, 242reflective mode, 241, 242

Field programmable function arrays (FPFAs),37–38

architecture, 37defined, 37processor tile architecture, 38

Field programmable gate arrays (FPGAs), 1, 32enhanced, 33revolution, 32

Flash converters, 101Flexible architecture radio (FAR)

defined, 1term adaptation, 25

Fractional-N-based upconversion system,213–14

Frequency conversion, with undersampling,84–85

Frequency-division duplex (FDD), 143Frequency modulation (FM), 2Frequency multiplication

in linear upconverter, 209–10odd-order, 210

Frequency planningconverter harmonics and, 87techniques, 87–88

GGain

balance, 266–67differential, 268feedforward correction and, 261IF/RF feedback and, 173I/Q, 187–90with oversampling, 85–86phase errors and, 122phase errors combination, 70–72SNR, 86See also Imperfect gain balance

Garp architecture, 35–36design, 35desirable features, 36illustrated, 35

Gaussian noise, 109General Packet Radio Service (GPRS), 4Glitch impulses, 205Global roaming, 4Global System for Mobile (GSM)

communications, 1

HHandset model, 12–13

consumer, 13equipment manufacturers, 12–13network operator, 13

Handsetsalternative digital processing options, 35–41architecture, 4operating systems, 7

Hard clipping, 273–75Hardware specifications, 27–30

Index 325

Hardware specifications (continued)A/D converter, 28–29antenna, 27circulator or duplexer, 27–28D/A converter, 29DSP, 29receiver anti-alias filtering, 29RF power amplifier, 29

High IF, 158–59Highpass and lowpass filters, 217–20High-speed converters, 101–4, 106High-speed DACs, 197

distortion mechanisms, 204non-ideal performance, 204–5response illustration, 205step response, 204–5See also D/A converters

IIdeal SDR architecture, 26–27

anti-alias and reconstruction filtering, 27circulator, 26–27digital processing subsystem, 26illustrated, 26linear power amplifier, 27See also Software-defined radio (SDR)

IFdigital, in feedback path, 268–69digital, in upconversion/feedback paths,

269–70envelope restoration transmitter with, 288high, 158–59

IF/RF feedback, 172–73advantage, 173defined, 172disadvantages, 173gain/phase matching, 173illustrated, 172See also Feedback techniques

Image rejectionachieving, 158–70high IF, 158–59mixing, 159–70

Image-reject mixers, 159–70, 215–16advantages, 169alternative forms, 161–62basic configuration, 160control based on direct multiplication,

166–68control based on LO nulling, 162–65control based on sounding tone injection,

165–66

enhancement, 162–68multiplication-based control, 167–68polyphase filtering in, 168–70Weaver, 161

Imperfect gain balancein analoque quadrature upconverter,

266–67in downconversion mixers, 267in quadrature downconverter, 267See also Gain

Inherently linear processing, 183–84Integral non-linearity (INL)

data-converter correction, 108defined, 106error, 106–7

Interception point cascaded, 93–94Intermodulation distortion (IMD), 11, 88

from front-end non-linearity, 144level in receiver design, 94–95performance, 95

Interpolated bandpass upconversion, 197–98defined, 197illustrated, 198

Interpolationfrequency-domain effect, 196quadrature upconversion with, 194–97time-domain effect, 195

LLange coupler, 227–28

as broadband 90° phase splitter, 227defined, 227design, 227drawbacks, 227tolerances, 227–28

Leesons equation, 317–18Legacy systems, 2–3LINC transmitter, 290–94

advantages, 290, 293alternative form, 292analogue implementation, 293defined, 290digital IFs, 292disadvantages, 293

DSP, 293, 294output signal, 291schematic, 290, 291See also RF synthesis techniques

Linearisationbandwidth, 186of LNA, 173–76mixer, 172

326 Index

PA techniques, 233–62transmitter techniques, 262–87

Linear upconversion architectures, 186–210Local oscillator (LO)

image-reject mixer control with, 163, 164leakage suppression, 190–91nulling, 162–65phase noise, 193phase noise characteristic, 124–25phase noise in EVM, 125–27test signal results, 128–29Look-up tables (LUTs), 264, 266Low-noise amplifiers (LNAs), 176error amplifier basis, 176feedforward vs., 176mixer combination, 178

Low voltage differential signaling (LVDS), 197

MManual download, 6–7Markets Committee (SDR Forum), 22Massively parallel processor arrays, 34Matrix Interconnect Network (MIN), 40Memory correction, 271Memory effects, 271Mixers, 141Moore’s law, 11Multi-band receivers

design, 140–42ideal, 170problems, 140See also Receivers

Multi-carrier DACs, 257Multicarrier power amplifiers (MCPAs), 19

efficiency, 21output power, 20

Multi-carrier receiver designs, 60Multi-carrier reception, 92–93Multi-carrier upconversion, 199–201

architecture illustration, 200defined, 199NCOs, 199, 201See also Upconversion

Multi-mode ADC, 104Multi-path cancellation, 157Multiplier-divider techniques, 228–29Multi-stage systems, 131–34Multi-standard terminals (MSTs)

benefits, 3–5defined, 1, 3economies of scale, 4

global roaming, 4key requirements, 5–6multi-band operation, 5multi-mode operation, 5–6operational requirements, 5–7reconfigurable mechanisms, 6–7service upgrading, 4–5software-definable operation, 5

Multi-zero networks, 225

NNetwork operators, 13Noise

ADC, 90–92phase, 117–18, 317–18quantisation, 117thermal, 117

Noise factor, 88–89cascaded system, 89defined, 88feedforward, 175

Noise figure, 88–92ADC noise, 90–92cascaded, 89converter, 118–20defined, 89feedforward, 175, 176overall system, 88–90

Non-linear capacitance, 204Non-linear slewing, 205Non-recurring expense (NRE), 30Numerically controlled oscillators (NCOs), 60Nyquist bandwidth, 88Nyquist sample rate, 84Nyquist sampling, 50, 85Nyquist zone, 85, 88

OOpen Base-Station Architecture Initiative

(OBSAI), 7, 11–12Open-loop non-linearities, 204Operational bandwidth, 185–86Organisation, this book, xi–xiiOriginal equipment manufacturers (OEMs), 7,

8, 12Orthogonal frequency division multiplexing

(OFDM), 9multi-carrier environment, 65pilot sequence, 65quadrature mismatch impact, 72

Over-air download, 6

Index 327

PPA linearisation techniques, 233–62

analogue predistortion, 234–44basic operation, 245–48feedforward, 244–45power efficiency, 248–51predistortion, 234See also Power amplifiers (PAs)

Passive all-pass networks, 222–25circuit, 224component values, 224defined, 222illustrated, 223pole values, 223

Passive RF feedback, 277Peak code domain error (PCDE)

defined, 134EVM relationship, 134–35

Performance monitoring, 252–53Performance stabilisation, 253–60

adaptive nulling, 253–59carrier injection, 259–60

Phase-locked loop (PLL), 197Phase noise

density, 318EVM influence, 120–34impact on SDR receiver performance,

117–18LO, 125–27, 193local oscillator characteristic, 124–25non-uniform distribution, 118in RF oscillators, 317–18SSB characteristic, 317See also Noise

Piecewise approximation, 125Pilot control technique, 260PIN diodes, 219PLL-based transmitters, 210–15

DDS for modulation, 213directly-modulated VCO, 211–12divider modulated, 210–11input reference modulated, 212–13modulated fractional-N synthesis, 213–15reference, 210–11See also Transmitters

Polar loop transmitters, 280–84advantages, 281–82application, 282–84with digital baseband signal generation, 283illustrated, 280input, 280

input envelope, 281output phase information, 281schematic, 280See also RF synthesis techniques

Polar RF synthesis transmitter, 287–89class-S switching PA, 289defined, 287delay-compensation, 289with IF, 288with linear baseband power amplifier, 288non-linearities, 288

Polyphase filters, 221–22advantages, 169application illustration, 170application in image-reject mixer, 168–70illustrated, 169second-order, 221–22

Power amplifiers (PAs), 9–10comparison of requirements, 184–85constraints, 184–85efficiency, 185linearisation, 13–14, 184, 185–86multicarrier (MCPAs), 19operational bandwidths, 185–86output power, 184size, 184

Power consumptionA/D converter, 41–43, 51–52BTS hoteling, 17examples, 47–51minimum, derivation of, 43–47smart antenna issues, 19–21

Power efficiency, 248–51, 296–97dependency, 248DPD, 273–75error amplifier, 249feedforward, 248–49, 297importance, 296overall, 250range of system parameters, 250–51

Power handling, 252Predistorters

anti-parallel diode-based, 241–44cubic, 238–39digital (DPD), 262–77FET-based, 240–41practical circuits, 239–44scalar, 238–39series-diode, 239–40varactor diode, 24

Predistortion, 234adaptive control, 244

328 Index

analogue, 234–44defined, 234linearisation scheme, 235RF, 234system operation, 234theory of operation, 235–38

Programmable application-specific standardproduct (P-ASSP), 33–34

Pseudorandom binary sequence (PRBS), 107Pulse-width, quadrature amplitude modulated

(PWQAM) waveform, 296Pulse-width modulation (PWM), 288

QQuadrature

downconverters, 215imperfect, 266–67mismatch compensation, 63–65mixers, 186upconverters, 215

Quadrature phase-shift keying (QPSK), 5Quadrature techniques, 215–29

active all-pass filter, 216–17highpass and lowpass filters, 217–20introduction, 216Lange coupler, 227–28multiplier-divider techniques, 228–29passive all-pass, 222–25polyphase filtering, 221–22tunable broadband phase splitter, 225–27

Quadrature upconversionanalogue, 186–94with interpolation, 194–97in linear transmitter, 186

Quantisation noise, 117Quasi-linear amplifiers, 236–37

RRaw processor, 38–39

architecture, 38benefits, 39internal architecture, 39programmable tiles, 38

Receivers, 57–135ADC spurious signals, 97–107anti-alias filtering, 29architecture options, 57–84blocking and interception point, 93–94converter performance limitations, 95–97direct-conversion, 82–84

frequency conversion with undersampling,84–85

IMD level, 94–95implementation, 84–120multi-band design, 140–42multi-carrier designs, 60multi-carrier reception, 92–93processing gain with oversampling, 85–86sensitivity, 92–93single-carrier designs, 57–60single-carrier reception, 92spurious products elimination, 86–88universal architecture, 141zero IF architectures, 60–82

Reciprocal mixing, 118Reconfigurable Compute Fabric (RCF), 34–35Reconfigurable mechanisms, 6–7

handset operating systems, 7manual download, 6–7over-air download, 6

Reconfigurable radio, 1Regulatory Committee (SDR Forum), 22Remote RF heads (RRH), 14RF

channel bandwidth, 50digital separation, 14feedback, 172oscillators, phase noise, 317–18power amplifier specifications, 29power requirements, 14receivers, 57–135synthesis techniques, 184Tx/Rx switch, 145, 146–50RF black boxinternal structure, 17SDR system, 9use of, 15RF DACs, 205–9advantages, 207–8dual, 209linear transmitters using, 205–9operation, 206–8structure, 206–8structure illustration, 207transmitter architecture using, 208–9See also D/A converters

RF feedback, 277–78illustrated, 278passive, 277shunt, 277transmitter architectures, 278

RF synthesis techniques, 287–96

Index 329

RF synthesis techniques (continued)LINC transmitter, 290–94polar transmitter, 287–89sigma-delta, 295–96

SScalar predistorters, 238–39Schottky diode-based frequency tripler, 211Schottky diodes, 244Scope, this book, xiSDR Forum, 22–23

defined, 22Markets Committee, 22Regulatory Committee, 22Technical Committee, 22–23

Second-order distortion, 74in direct conversion receiver, 77impact, 77level, 78requirements, 73–79

Second-order intercept point, 74Second-order polyphase filter, 221–22Series-diode predistorters, 239–40

defined, 239illustrated, 240

Schottky diode, 239Service upgrading, 4–5Servo control loops, 69–70Shunt feedback, 177Sigma-delta converters, 103Sigma-delta techniques, 295–96

advantages, 296defined, 295disadvantages, 296high-efficiency transmitter employing, 295See also RF synthesis techniques

Signal to interference, noise, and distortion(SINAD), 95–96

Signal-to-noise ratio (SNR), 96clock jitter and, 112, 113gain, 86ideal N-bit A/D converter, 90

Signal vector error (SVE), 120calculation without phase noise disturbance,

122–24LO test signal results, 128–29sources, 121

Single-carrier receiver designs, 57–60analogue quadrature, 57–58digital IF, 58–59digital processing, 59–60

Single-carrier reception, 92Single downconversion receiver, 62Six-port discriminators (SPDs), 83–84

basic, 83digital receiver using, 84format, 83

Six-port networks (SPNs), 82–84defined, 83operation, 83

Slew rate, 111Smart antenna systems, 18–22

architectures, 19calibration issues, 21–22downlink, 20, 21introduction, 18power consumption issues, 19–21

Software defined radio (SDR)architectures, 25–26BTS business models enabled by, 8–10business model, 7–13defined, 1digital aspects, 30–41digital hardware, 30–33handportable, 28handset architecture, 4hardware architecture use, 12hardware specifications, 27–30ideal architecture, 26–27introduction, 2requirement for, 2–3RF black box system, 9superconducting technology impact, 54–55

Sounding tone injection, 165–66advantages, 165defined, 165disadvantages, 166

SpeakEasy programme, 2Specialised mobile radio (SMR)

channels, 3deployments, 2FM scenario, 3

Spurious-free dynamic range (SFDR), 96–97alternative improvement techniques, 109defined, 96maximum value, 97measure, 97

Stallion processor, 39–40State-of-the-art (SOTA) devices, 32Subranging, 102Superconducting quantum interference device

(SQUID), 54Superconducting SDR resolution, 54–55

330 Index

advantages, 54crycoolers, 54–55disadvantages, 54–55packaging costs, 55size, 55

Switched diplexers, 145–46, 151–52defined, 151disadvantages, 152illustrated, 151See also Diplexers

TTechnical Committee (SDR Forum), 22–23Thermal noise, 117Time-division duplex (TDD), 143Time-division multiple access (TDMA), 143Tower-top mounting, 15–16

defined, 15delay, 16issues, 15maintenance, 15–16weight, 16

Transmitter linearisation, 184, 262–87Cartesian loop, 284–87digital predistortion, 262–77feedback techniques, 277–80polar loop, 280–84

Transmittersbasic architecture, 183Cartesian loop, 284–87constraints, 184–85directly-modulated VCO, 211–12divider modulated, 210–11efficiency, 185envelope restoration, 287–89EVM performance, 194high-linearity, 183LINC, 290–94linear upconversion architectures, 186–210output power, 184PLL-based, 210–15polar loop, 280–84relative merits, 297–300with RF DAC, 205–9size, 184

Tunable broadband phase splitter, 225–27Tx/Rx switch, 145, 146–50

isolation, 147isolation series-shunt, 150linearity, 147loss, 147

operation, 148power-handling capability, 147quarter-wave line for, 149series-shunt, 148SPDT, 150

UUndersampling, 84–85

defined, 84importance, 84–85

Upconversionanalogue quadrature, 186–94constant-envelope architectures, 210–15digital IF, 198–99fractional-N-based, 213–14frequency multiplication in, 209–10interpolated bandwidth, 197–98linear architectures, 186–210multi-carrier, 199–201noise floor, 191–93quadrature, with interpolation, 194–97Weaver, 201–4

VVaractor diode predistorters, 240Voltage-controlled oscillators (VCOs), 193

modulation, 193PLL-based directly modulated transmitter,

212

WWeaver image-reject mixer, 161Weaver upconversion, 201–4

baseband input signal spectrum, 202defined, 201output signal spectrum, 203SSB generator, 201See also Upconversion

Wideband code-division multiple access(WCDMA), 1

3GPP signals, 273four-carrier, 189three-carrier, 19

Wireless Systems Processor, 33World Wide Research Forum (WWRF), 23

ZZero IF receiver architectures, 60–82

1/f noise, 73baseband and digital IFs, 81–82

Index 331

332 Index

Zero IF receiver architectures (continued)baseband filter implementation, 81DC offsets, 65–70DC offsets and gain/phase error, 70–72gain control requirements, 79–80illustrated, 62multi-mode issues, 80–81

quadrature mismatch, 63quadrature mismatch impact, 72second-order distortion requirements,

73–79single downconversion, 62See also Receivers

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