Microelectronics Reliability xxx (2015) xxx–xxx

MR-11718; No of Pages 6

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Microelectronics Reliability

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RF functional-based complete FA flow

A. Fudoli a,⁎, G. Martino b, A. Scrofani b, P. Aliberti b, D. Gallo a, M. Cason aa STMicroelectronics, Agrate Brianza, Italyb STMicroelectronics, Catania, Italy

⁎ Corresponding author.E-mail address: alessandra.fudoli@st.com (A. Fudoli).

http://dx.doi.org/10.1016/j.microrel.2015.07.0230026-2714/© 2015 Elsevier Ltd. All rights reserved.

Please cite this article as: A. Fudoli, et al., RFj.microrel.2015.07.023

a b s t r a c t

a r t i c l e i n f o

Article history:Received 25 May 2015Received in revised form 20 June 2015Accepted 6 July 2015Available online xxxx

In this paper, we present a case study on Radio Frequency device,where a complete failure analysisflowhas beenapplied, built through integration of transversal competences from design, testing, and application teams.Key point is using functional failure as electrical fault activation. Indeed this approach allows enlarging the cov-erage of Failure Analysis to many functional failures reproducible through application board.The device under analysis is a frequency synthesizer, operating in the range of 2 GHz to 4 GHz, built in BiCMOStechnology, failing on application at low temperature (−36 °C). Fault Isolation step is based on the replicationof functional failure mode, through application board as electrical stimulus to activate the fault. Moreover,since failure is depending on temperature and voltage conditions, a Dynamic analysis through Laser Stimulushas been implemented (DLS) with a RTVM-like approach. This setup required specific adaption of applicationboard in order to cope with mechanical and electrical constraints of DLS while reproducing failure mode in theGHz range. The amplitude variation of failing RF output signal wasmonitored by an additional circuitry that con-verted information of loss of signal in a suitable logic signal for DLS analysis. Fault Isolation pointed out to specifichigh frequency bipolar transistors on a divider block. Physical Analysis addressed to these components, which arekey for this kind of products, put in evidence dislocations inside Si–Ge layer.

© 2015 Elsevier Ltd. All rights reserved.

1. Introduction

Exponential growing of data communication through different gen-eration of Wide Area Network systems (WCDMA, HSPA, LTE) is today amatter of fact. A key point in the system is the wireless infrastructure.For example, a single Macro base station actually covers more than10,000 users at the same time. If a single base station fails, there arehuge costs in terms of QoS (Quality of Service). As typically lifetime isin the order of 10 years and extreme temperature conditions can bemet in these applications, reliability of such devices is a fundamental re-quirement. Failure Analysis in the early stage of product lifetime is a keypoint tominimize potential field issues towards product quality of 0 de-fective parts per million.

This represents a challenge for Failure Analysis because we under-stand that standard Fault Isolation techniques are no more sufficientto cover such kind of Failure Modes. Integration between application,design, testing and Failure Analysis competences is a potential winningstrategy to improve Failure Analysis effectiveness.

We present a case study where a functional-based Failure Analysisflow has been applied. It starts from detailed analysis of failure modein application environment and its correlation with test, and, throughdynamic fault isolation technique based on functional fault activation,finally drives Physical Analysis to discover the physical defect.

functional-based complete FA

Failure Mode in application was first detected and claimed by cus-tomer as a loss of signal at low temperature (−36 °C) at nominal volt-age supply. This failure was correlated, through design analysis, to aspecific block and it was then replicated at room temperature but atlower voltage, exercising only the specific suspect block.

Since the dependence of failure by voltage and temperature condi-tion, it was considered a good candidate to be submitted to DLS (Dy-namic Laser Stimulation) Fault Isolation technique. This technique hasbeen applied while Device Under Test was stimulated to its functionalfailure mode through the real application board.

To be able to use the application board with DLS equipment and tocorrectly drive the DUT, severalmechanical modificationswere needed.

Furthermore, the loss of signal observed at the output of applicationboard, had to be converted in a signal suitable to be detected by DLS. Itwas then selected an additional circuitry, a limiting amplifier, whoseauxiliary output is a digital signal, that switches when loss of signal am-plitude is detected. Thanks to this RTVM-like approach [1,2], the failureis correctly interpreted by DLS system and is then able to provide a pixelmap of sensitive components inside circuit, which appeared to be bipo-lar transistors, key structures for this kind of products [3,4].

2. Design/application/testing analysis

As first step, failure was analyzed by designer, trying to understandwhich block could be involved and to formulate hypothesis to explainfail.

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Fig. 1. Characterization (output power dBm vs Vdd).

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Considering that the product is a PLL-based frequency synthesiz-er (phase locked loop) that extends its frequency range using fre-quency dividers at RF output, the failure showed a stable lockedcondition while no signal appears at its output. The main candidatehas been identified in the frequency divider and dedicated tests con-firmed it. As typically frequency divider failures show some incorrectdividing ratios (for example a divider by 2 sometimes divides by 2/3)due to divider architecture, our investigation has been oriented to-wards the active circuits inside the divider, the main differentialstage of the bipolar flip-flop. A similar failure mode is expected atnominal supply voltage, low temperature (as Vbe temperature coef-ficient is ~−2mV/C) or at ambient temperature with reduced supplyvoltage.

Back to our RF lab, we have been able to reproduce the failure at−36 °C in our characterization board using our internal GUI. It contains

Fig. 2. Backside view

Please cite this article as: A. Fudoli, et al., RF functional-based complete FAj.microrel.2015.07.023

the possibility to do dedicated tests (embedded into the registers/testmodes) that normally are not used in the final application, as it has allsupply voltage pins available separately. Using a spectrum analyzerwe have observed that, at temperature below 0 °C there is a progressivedegradation of noise generated by the RF divider, at−15 °C the dividerstarts to decrease the RF power output and the division ratio changes, at−36 °C the signal disappears. As similar behavior is expected decreas-ing the supply voltage (at ambient temperature), we have done thesame test on a good part and on the failed part comparing results. Weobserved a similar behavior on both parts, but at different supply volt-age thresholds. Having in our lab also parts from corner's lot (specialdiffused lot that represent the maximum spread of process parame-ters) we have repeated (at final test) the test using these corners toverify that the threshold of the failed part was not depending on pro-cess parameters spread (Fig.1). As all these verifications gave

of modified PCB.

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Fig. 3. Loss of signal detected at room temperature on fail sample and on good sample.

Fig. 4. Application board and limiting amplifier.

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positive results, finally we have been able to correlate the results ofour tests (Lab and Testing) with failed part, being sure to identifythe failure with a dedicated test at ambient temperature but lowersupply voltage.

3. Sample preparation and board adaption

Based on this preliminary and important analysis, a reproducibleFailure Mode at room temperature and a quite well defined block in-side the circuit to focus in the Fault Isolation step were available.Failure Mode was reproduced through application board, in orderto monitor output sinusoidal signal @2GHz. This was presenting adifficulty for Fault Isolation step, because application board are usu-ally not designed to provide accessibility to silicon die surface. Espe-cially for die backside surface, whose exposition is the most effectiveapproach for Fault Isolation. Moreover, for such a kind of application,backside of package has to grant ground contact to maintain goodhigh-frequency performances.

These problems were solved adapting application board to matchwithmechanical and electrical constraints of typical Failure Analysis en-vironment equipment.

Particularly, in order to allow inspection and stimulationthrough laser beam of backside die surface, an aperture hasbeen executed on the PCB and sample, backside mechanicallydecapsulated, has been mounted on board. Ground contact, whichis so critical for RF signal integrity, is granted through selectivebackside decapsulation, which preserves ground ring contact(Fig.2).

This specific Failure Mode is driven by a single power supply var-iation, as observed in application lab through a dedicated character-ization board and diagnosis software. Thus, an additional adaptionhad to be applied on the main application board, to isolate thispower supply, which would be instead hardware connected into agroup.

4. Electrical characterization

Thanks to preliminary study performed by design, application, andtesting teams, the FailureMode observed at low temperaturewas corre-lated to a different one, reproducible at room temperature, but depen-dent on voltage supply of a specific circuit block.

Specifically, at room temperature, it was found that the pass/failthreshold on divider block power supply, is higher than on a good refer-ence sample.

In the following table, full characterization performed at room tem-perature through application board is reported.

This characterization allowed individuating a voltage thresholdbelow which the fail parts shows loss of signal (2.4 V for fail part, vs2 V for good part) (Table 1).

Through Failure Analysis setup,with the board alreadymodified, thesame Failure Mode was reproduced and the same characterization per-formed: results are reported in Table 2. They showa very goodmatchingwith values found in application environment.

Failure at cold temperature was also reproduced, but room temper-ature condition was selected to perform the measurement and FaultIsolation.

In Fig. 3 the loss of output signalmonitored in good and fail sample isshown, to compare voltage level threshold.

Because of the sensitivity of electrical behaviour to voltage and tem-perature, a Dynamic Laser Stimulation techniquewas applied. This tech-nique indeed leverages on sensitivity of defect to temperature variationinduced by laser beam.Working point of electrical setup is set to thresh-old condition between good and fail behaviours, and laser beam, whilescanning silicon die surface, is able to induce transition between thesedifferent states.

Please cite this article as: A. Fudoli, et al., RF functional-based complete FAj.microrel.2015.07.023

This application is an analogue application; we have to monitor anoutput power or amplitude variation of a 2 GHz sinusoid. For this rea-son, several approaches were considered, either analogue or digitalDLS and finally we implemented a RTVM-like solution, but convertinguseful information in a digital signal.

Indeed, while amplitude of signal was uniformly and proportionallydecreasing by decreasing voltage from nominal to threshold value,when threshold value is reached, a sudden decrease and distortion ofsignal was detected (see Fig. 3). This observation leads thus to considerconverting into digital format the amplitude of output signalmonitored.Themost suitable solutionwas considered to add an additional circuitry,a limiting amplifier, connected to the output of DUT application board(Fig.4).

This is a device frequently used in RF application, to modify ampli-tude and edges of an input high frequency signal, whose auxiliary out-put provides a DC signal when input signal amplitude is lower thanprogrammed threshold.

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Table 1Output power (dBm) vsDivider Block voltage (V) in application environment. Fail vs goodsample.

VDD_Div2 [V] Pout Div2 2 GHz VCO A [dBm]

Ref. Good Fail

3.3 −1.45913 −1.939443.25 −1.47325 −1.954053.2 −1.49221 −1.970243.15 −1.51024 −1.989433.1 −1.53026 −2.007583.05 −1.54395 −2.027463 −1.57157 −2.049322.95 −1.59714 −2.075052.9 −1.61583 −2.096842.85 −1.64003 −2.118262.8 −1.68423 −2.147222.75 −1.74055 −2.195412.7 −1.79222 −2.250192.65 −1.85701 −2.329142.6 −1.93719 −2.461562.55 −2.04538 −2.726262.5 −2.21633 −3.337022.45 −2.46979 −4.88872.4 −2.83943 −59.19232.35 −3.35044 −74.19282.3 −4.0004 −53.20052.25 −4.78428 −89.6592.2 −5.72089 −88.31822.15 −6.87925 −84.82812.1 −8.87522 −76.58652.05 −14.2367 −86.97622 −79.9355 −86.5171.95 −85.5594 −77.9307

Fig. 5. Rise transition of pass/fail signal.

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The threshold of the limiting amplifier was programmed in order tobe able to detect the loss of signal in the suitable operating range of oursetup. Output DC signal amplitudewas suitable to be read byDLS equip-ment, so no additional signal processing was required. It was also char-acterized in terms of rise and fall time, in the range of 2 μs, to assure thebest synchronization with laser scanning system. A rise transition ex-ample is reported in Fig. 5.

Having considered all the single stages of setup needed for fault iso-lation, we proceeded with the integration of all of them.

5. Fault isolation setup and results

The setup implemented for fault isolation is sketched in the follow-ing scheme (Fig.6):

Table 2Output signal amplitude (mV) vs voltage (V) in FA environment. Fail vs good sample.

VDD_Div2 [V] RFOUT 2 GHz VCO BPk–Pk [mV]

Ref. Good Fail

3.3 747 7303.2 740 7203.1 735 7153.0 725 7152.9 720 7102.8 715 7052.7 705 7002.6 705 6902.5 685 6652.4 645 5652.35 620 420 distortion2.3 580 150

Please cite this article as: A. Fudoli, et al., RF functional-based complete FAj.microrel.2015.07.023

Based on fine characterization, previously performed at bench, allthe electrical conditions were already defined. Through dedicatedsoftware the application board was driven to output desired signalfrequency (2GHz) to be monitored. Always through PC, a differentsoftware was used to program the Limiting Amplifier threshold, inorder to properly screen the fail condition. Application board was bi-ased keeping separate control of specific power supply that wasinfluencing fail. Working point V= 2.35 V, was adopted as operatingcondition for DLS mode.

Maintaining this operating condition on DUT, and continuouslymonitoring its output, the laser beam at 1.3 um was scanning back-side die surface. While laser was scanning its surface, die appeared,only on some specific areas, extremely sensitive to local heating in-duced by laser beam itself, inducing fail transition, easily moni-tored through DC signal and detected by the system. Goodbehavior was then recovered suddenly when laser beam scannedother areas.

These points, where a PASS/FAIL transition was detected, aremapped by DLS software, providing spot on image. Fine tuning ofscanning frequency and acquisition time for each frame accordingwith rise time of digital PASS/FAIL signal, allowed refining spot sizeand individuating specific components potentially affected by de-fects (Fig. 7). Spots appeared in HBT transistors inside divider blockalready suspected by analysis done by designer and application engi-neer. This result was thus encouraging because the good match withinitial hypothesis.

6. Physical Analysis

Physical Analysis has been addressed based on the Fault Iso-lation results, focusing on HBT structures. Delayering was firstcarried out down to Metal1 and then HBT were submitted toFIB x-section. After that, TEM inspection was performed. Bythis analysis it was possible to discover dislocations inside Si–Ge layer into Base–collector junction. Fig. 8 shows detailedview of Emitter–base–Collector junction, and dislocation isvisible.

Just at bottom of Si–Ge layer, a dislocation has been observed.Dislocations can appear in this kind of technology, due togrowth of Si–Ge layer, which induces stress into lattice. Suchkind of dislocations can generate leakage into junction andclearly modify HBT behavior. This can explain changing ofthreshold voltage value at elementary components and thus atglobal level.

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Fig. 7. DLS acquisition.

Fig. 8. TEM DarkField detector.

Fig. 6. Scheme of fault isolation setup.

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7. Conclusions

In this paper a case study has been presentedwhere a complete Fail-ure Analysis flow for RF functional failures has been applied, which al-lows enlarging coverage of functional failure for such kind of products.It leverages on deep collaboration between design, test, applicationand failure analysis functions. In order to support application of theflow to the real case, specific developments in the Electrical Characteri-zation, Sample Preparation and Fault Isolation steps have been intro-duced and reported.

Please cite this article as: A. Fudoli, et al., RF functional-based complete FAj.microrel.2015.07.023

Physical Analysis concluded the flow, allowing discovering disloca-tions at Base–collector junction of HBT components, which are consis-tent with electrical failure mode.

Acknowledgments

We would like to thank especially Morgan Cason, divisional FailureAnalysis Manager, who encouraged and supported this activity. DavideCaccialanza and Roberto Parolini, who supported us in hard samplepreparation and board reworking in Agrate FA lab. Special thanks alsoto Alessandra Pagani, Physical Analysis Engineer, for patient and accu-rate physical analysis performed and to Emanuela Ricci, Physical Analy-sis Engineer,whohelped us to positively conclude this challengingworkthrough TEM analysis.

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References

[1] L. Saury, Parametric defect localization on integrated circuits— from static laser stim-ulation to real-time variation mapping (RTVM), Microelectronics Reliability 54(2014) 366–373.

[2] L. Saury, S. Cany, Dynamic defect localization using FPGA to monitor digital values,Microelectronic Reliability 51 (2011) 1701–1704.

Please cite this article as: A. Fudoli, et al., RF functional-based complete FAj.microrel.2015.07.023

[3] J.D. Cressler, SiGe HBT technology: a new contender for Si-based RF and microwavecircuit applications, IEEE Trans. Microwave Theory Tech. 46 (5) (May 1998) 572–589.

[4] D.C. Ahlgren, G. Freeman, S. Subbanna, R. Groves, D. Greenberg, J. Malinowski, D.Nguyen-Ngoc, S.J. Jeng, K. Stein, K. Schonenberg, D. Kiesling, B. Martin, S. Wu, D.L.Harame, B. Meyerson, A SiGe HBT BiCMOS technology for mixed signal RF applica-tions, Proceedings of 1997 Bipolar/BiCMOS Circuits and Technology Meeting 1997,pp. 195–197.

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RF functional-based complete FA flow1. Introduction2. Design/application/testing analysis3. Sample preparation and board adaption4. Electrical characterization5. Fault isolation setup and results6. Physical Analysis7. ConclusionsAcknowledgmentsReferences