RF Hardware Design and Integration 4x4 MIMO for Ultra Wide Band Base Station

Senior Design Project Report, submitted on May 26, 2009

Report Submitted to Dr. Afshin S. Daryoush and the Senior Design Project Committee of the

Electrical and Computer Engineering Department, Drexel University

Team Number: ECE-24

Team Members:

Paul Miranda Electrical Engineering Christopher Hinton Electrical Engineering Vaibhav Mistry Electrical Engineering

Our team would recommend to Dr. Daryoush to become more visual when explaining system level requirements and designs.

Executive Summary

Purpose and Scope of the Project: The purpose of this Senior Design project is to research, develop, and design the system

components for an Ultra Wide Band Base Station. The motivation behind this Base Station is to provide the latest technology for the upcoming 4th Generation communication systems. The success of this project will see it being implemented in ever growing field of commercial communications requiring larger bandwidth as well as other military based operations which require greater sampling rates. Methods:

We are going to design a 4G wireless base station with a super heterodyne receiver as our overall theme. There has been previous work done by other teams and we are going to implement some of their devices with our designs to create the base station. A power analysis was done in order to provide accurate specifications for each device. The individual specifications of the different devices would contribute to overall success of the entire system. Once all of the prototypes are built and performing correctly, we are going to fully integrate the devices and perform a design verification test to ensure the system is working properly. Results:

Compared to our timeline we are ahead in the development of the footprints, connections, and layouts of the prototypes. We have recently received the bad news that the Drexel PCB shop is down due to a broken motor; this presents our team with a large problem. Dr. Daryoush has his own LPKF PCB milling machine that can fabricate the circuits on 15 mil thick FR4 substrate. This should be an adequate replacement while we wait for the Drexel PCB machine shop. In the mean time, we will implement the following testing and calculations: noise figure measurements, system level power supply calculations, system level power calculations, local oscillator testing.

At the moment, we are under budget. The major accomplishments so far consist of circuit layouts. The team learned how to make layouts in the software, Advanced Design System (ADS). Through trial and error we eventually became very proficient at it. To date we have built two prototypes boards, the LO & PP Board and the 1:4 Power Divider Board, and are almost finished with the other two prototype boards, The Digital Transmitting Board and the Digital Receiving Board. Physical testing will be done while waiting for the Printed Circuit Boards (PCB) to return from fabrication. Conclusions:

The major challenge we have faced so far was learning ADS software in order to design layouts with it. Another challenging task was to familiarize ourselves with different test equipment like a Spectrum Analyzer and a Network Analyzer for testing our circuits. At times, we were unable to measure different circuit parameters because we had to share our instruments with the other labs. So far we have done S-Parameter measurements on the Low Noise Amplifier (LNA) and the Power Amplifier (PA). Both are functioning as required. Recommendations:

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Abstract

Our design project has focused on hardware aspects of the RF front end for 4x4 Multiple

Input and Multiple Output (MIMO) base station designed for the first Orthogonal Frequency Division Multiplexing (OFDM) channel of the Ultra Wideband (UWB) wireless standard (i.e., 3.1 to 3.6 GHz). The 4x4 MIMO RF front-end requires 4 Receiver and 4 Transmitter Boards. A Local Oscillator (LO) board is needed for providing a coherent signal at 3.158GHz for frequency up and down conversion. Prototype circuits for each sub-system module were designed, laid-out on 25 mils RO3006 high frequency laminate boards, fabricated and tested. The performance was compared between the data sheets, evaluation boards, and prototype boards leaving similar results. The successful layouts were incorporated to the digital transmitter and receiver boards in collaboration with team ECE-23.

We remain on schedule with each prototyping module. Unfortunately, we are behind in the system integration due to the time consuming process of trouble shooting the amplifiers. In comparison to our original proposed out of pocket budget given in the fall, we are definitely over budget. In the original budget we considered the price of driving to Hybrid Tech for wire-bonding; but as the project continued, we relied on Advanced Control Components for wire-bonding. While they graciously provided the necessary wire-bonding for free, the number of trips and the amount of miles increased.

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1. Title Page pg. 1

Table of Contents

2. Executive Summary pg. 2 3. Abstract pg. 3 4. Table of Contents pg. 4 5. Body of Report pg. 5

5.1. Abbreviation Table pg. 5 5.2. Problem Description pg. 5 5.3. Progress toward a Solution pg. 5 5.4. Local Oscillator and Poly-phase Board pg. 5

5.4.1 Local Oscillator pg. 5 5.4.2 Poly-phase pg. 6 5.4.3 System Integration pg. 7

5.5. Receiver and Transmitter Boards pg. 7 5.5.1 Low Noise Amplifier (LNA) pg. 7 5.5.2 Buffer Amplifier (BA) pg. 8 5.5.3 Power Amplifier (PA) pg. 9

5.6. Constraints pg. 10 5.7. Budgets pg. 11 5.8. Gantt Chart and Teamwork pg. 13 5.9. Summary & Conclusions pg. 14 5.10. References pg. 14

6. Appendices pg. 15

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Abbreviation Table

COTS Components Off the Shelf DRB Digital Receiver Board RFIC Radio Frequency Integrated Circuit GCM Gilbert Cell Mixers UWB Ultra-Wideband DTB Digital Transmitter Board BPF Band Pass Filter LO Local Oscillator LPF Low Pass Filter SNR Signal-to-Noise Ratio

OFDM Orthogonal Frequency Division Multiplex BPSK Binary Phase-Shift Keying PA Power Amplifier BA Buffer Amplifier

LNA Low Noise Amplifier FPGA Field Programmable Gate Array RF Radio Frequency IF Intermediate Frequency

ADC Advanced Design System DSP Digital Signal Processing Table 1. Abbreviation Table

Problem Description:

Ultra wide band communication is the 4th Generation (4G) for advancing wireless

communications systems. Consumers demand for faster, more reliable mobile applications is evident [1]. UWB technology will be able to provide a comprehensive IP solution where voice, data and streamed multimedia can be given to users at higher data rates than existing forms of wireless technology. Some of the applications of UWB are, but not limited to: high speed broadband access to the internet and secure communications [2]. The specific problem our team we are addressing is the need for a 4G Telecommunication Base Station.

Our senior design team has focused on the hardware implementation of both the receiving and transmitting portions of the system. The main focus will be the incorporation of the 4x4 Multiple Input Multiple Output (MIMO) transceiver composed of four 2x2 sub-array antennas with a Super-Heterodyne Receiver and Transmitter system. The block diagram for up-conversion and transmitting can is shown in Figure A1, while the receiving block diagram can be found in Figure A2. The block diagram for the stable Local Oscillator and Polyphase Board can be found in Figure A3.

In summary, the necessary components in the RF front end of both the receiver and transmitter are: a PA, a LNA, a LO, and a Poly-phase Shifter. These circuits are essential in order to construct the RF front end electronics channel of a broadband OFDM UWB base station ranging from 10 to 100 meters. Our project will be complimented by ECE-23 whose focus will be on the back end electronics such as: the FPGA, DSP Algorithms, the GCM, and the various filters (LPF and BPF).

Progress toward a solution Local Oscillator and Poly-phase Board: Local Oscillator

In our communication schemes the LO is used to up convert a baseband signal, via a differential Gilbert Cell Mixer, to a RF or Microwave frequency to carry the information. This year, as opposed to previous years, a COTS LO was successfully implemented. This process started in the fall term when we identified FWS200400-100[3] made by Synergy Microwave Corporation.

We received 3 samples and an evaluation board (see Figure B2) from Synergy Microwave Corporation. In the winter term we began experiments on the provided evaluation board, with a 10 MHz Crystal Oscillator [4] as a reference. Unfortunately, while going through the testing of the

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evaluation board we ran into a connectivity issue. Synergy Microwave Corporation made a GUI to program the LO’s PLL to a specific frequency through a DSUB-25 Connector. This connectivity issue was solved by borrowing an old laptop from the ECE department and downloading a beta version of Synergy’s software.

Once we successfully programmed the LO’s PLL with the computer, we characterized the evaluation board. After receiving good results, we designed our own layout on Rogers 3006 High Frequency Laminate (see Figure B4). We then milled out the prototype board (see Figure B1) and compared the Phase Noise to both the data sheet and the evaluation board (see Table 2). In addition, we fully characterized the Harmonic Suppression, Spurious Suppression, Phase Noise, and Output Power (for Output Power and spectrum see Figure B3) for 5 frequency points every 100 MHz, starting at 3.158 GHz (see Table 3).

Phase Noise, dBc/Hz @ 3.25 GHz

@ 1 kHz offset @ 10 kHz offset @ 100 kHz offset Data Sheet -85 dBc/Hz -85 dBc/Hz -110 dBc/Hz

Evaluation Board -100 dBc/Hz -110 dBc/Hz -110 dBc/Hz Prototype Module -88 dBc/Hz -90 dBc/Hz -112 dBc/Hz

Table 2. Phase Noise comparison between Data Sheet, Evaluation Board, and Prototype Module

Output Frequency,

GHz

Output Power, dBm

Spurious Suppresion,

dBc

Harmonic Suppression,

dBc Phase Noise with offset of, dBc/Hz

30 Hz

90 Hz

100 Hz

500 Hz

1 kHz

10 kHz

100 kHz

3.158 0 -72 -12 86 -90 -87 -88 -90 -88 -113 3.258 0 -71 -13 -82 -84 -86 -84 -88 -90 -112 3.358 0 -70 -11 -86 -87 -91 -82 -87 -87 -111 3.458 0 -71 -10 -85 -83 -87 -81 -91 -90 -114 3.558 -2 -70 -11 -85 -84 -87 -85 -93 -102 -110 3.658 -1 -70 -11 -85 -88 -90 -90 -95 -91 -111

Table 3. Full Characterization of LO over full bandwidth of interest Poly-phase Circuit

In order to provide the differential Gilbert Cell Mixer with the appropriate signals for both the I & Q Channel of our super-heterodyne receiver, a Poly-phase Circuit was require to split a signal to 0°, 90°, 180°, and -90°. The Poly-phase Integrated Circuit (IC) was developed by under Dr. Daryoush in previous years (see Figure C3 and C4).

In order to place the Poly-phase on Rogers RO3006 High Frequency Laminate, we purchased 15 Leadless Chip Carriers (LCC) from Evergreen Semiconductors (see Figure C5). The cost was rebated by the ECE Department, thus not effecting our out of pocket budget.

The LCC has dimensions in comparison to the IC in which wire-bonding could not be accomplished without a ‘jumping’ process, due to the structural integrity of the 1mil in diameter gold wire (see Figure C2). After simulating for the effect of wire-bonds being ‘jumped’ to capacitors, we informed the technicians at Advanced Control Components (ACC) to place the capacitors and the IC in specific positions. The IC was then epoxied to the LCC along with single layer capacitors (see Figure C6).

We then developed a footprint for the LCC and designed a layout to test the Poly-phase capability (see Figure C1). Subsequently, we fabricated the prototype module and surface mounted using solder the necessary DC biasing capacitors and RF chokes (see Figure C7). Because the IC is extremely sensitive to soldering fumes, we surface mounted the LCC with conductive epoxy.

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The Poly-phase circuit was then tested (see Figure C8) for the phase delay and amplitude difference between the four different outputs. The results (see Figure C9) demonstrated that V270 had a large difference in amplitude (V270). System Integration

As stated earlier, in order to feed 4 Receiver and 4 Transmitter Boards, each with differential Gilbert Cell Mixers for both I and Q Channels, we had to design a board with a phase and power distribution network. The challenge of this board was to provide four different phases, 0°, 90°, 180°, and -90° to 8 separate boards. This over all board was mechanically laid out in the winter term (see Figure D1) and designed in ADS in the spring term (see Figure D2).

This was accomplished by designing and implementing prototype circuits for a Balun Circuit (see Figure D5 and D6) and a 1 by 2 Power Divider Circuit (see Figure D9 and D10). We received samples from Johansson Technology for the Balun [5] and samples from Mini-Circuits for the 1 by 2 Power Divider [6]. After trial and error, final circuit layouts were constructed in ADS and were implemented on Rogers R03006 High Frequency Laminate. Subsequently we tested both circuits and received favorable results (see Tables D1-D4 and Figures D7, D8, D11, and D12).

Once we were satisfied with the Balun and Power Divider circuits we filled in the mechanical layout (see Figure D2) with the respective circuit components. We then milled out the board and populated the board (see Figure D3 and D4). Due to the board’s large size, approximately 5.5” by 10”, we developed a metal back plane to add structural integrity in the Drexel metal shop. We then incorporated the alumina board electrically by using conductive grease and drilling screw holes. The screws and the conductive grease provided us with a solid ground plane and the additional support we needed. Only initial testing (see Figure D13) due to time constraints and assembly difficulties.

Transmitter & Receiver Boards Low Noise Amplifier

An amplifier usually amplifies the noise along with the signal. A LNA is used to amplify the signal and limit the noise as much as possible. It is used on the receiver board between the antenna and filter. In 2005-06, Team 32 designed an LNA to work at 2.45 GHz. The previous year senior design team worked on the impedance matching circuit to stabilize it over 3.1 GHz, but they faced oscillations because of the coupling errors. This year we chose to go for the COTS LNA from RFMD (P/N: RF3866) [7]. The primary requirements for the LNA are summarized in Table 4.

Parameter Requirements

Frequency (GHz) 3.1-3.6 GHz Gain (dB) 20 dB

Noise Figure (dB) 1 dB Table 4: Requirements for the LNA

The first step towards a design of the LNA was to test the evaluation board from the

company and verify the results (see Figure E5). After getting satisfactory results from the device (see Figure E3), our next plan was to design a layout based on the schematic provided by the company and fabricate our own prototype board (see Figure E1). The layout for the LNA had to go through various design changes because it is very easy for an amplifier to oscillate if it is not matched properly. We soon discovered that any additional length of the transmission line will add parasitic reactance to the matching network. Another design consideration was the grounding plane for the

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center pad of the chip. It needed to have as many as four via-holes or rivets to provide a proper grounding of the thermal pad. Unfortunately, we did not have extremely small rivets; we could only accommodate one rivet under the center pad. Test, with a single rivet underneath the center pad, gave poor gain. We could not achieve stable gain throughout the full frequency range of interest.

Another problem we faced dealt with the lumped components. We soon discovered that all the lumped components have to be as close to the circuit as possible, otherwise the extra length of line between the components and the pad will again add reactance. In addition, we discovered that the shunt components grounding had to be applied as close as possible with a via-hole or rivet. If both of these did not happen the matching network for the amplifier would change and cause unwanted oscillations.

We fabricated another amplifier this time with lumped components as close to the pad as possible (see Figure E4). With our latest design, we were able to get a stable gain of 20 dB (see Figure E7) for the full frequency bandwidth of 3.1-3.6 GHz. Also the IP3 and Noise figure (see Figures E8 and E9) for the prototype board was very close to the values mentioned in the datasheet. The Table 5 compares the parameter of the evaluation board and the prototype board. Hence after various design changes we were successfully able to design the low noise amplifier which met all our design needs.

Parameter Evaluation Board Prototype Board Gain (dB) 20 dB 20 dB IP3 (dBm) 16.9 dBm 16.75 dBm

Noise Figure (dB) 0.8 dB 1.1 dB Table 5: Comparison of Evaluation and Prototype Board

Buffer Amplifier

A buffer amplifier (BA) is an amplifier which transfers a voltage from a circuit having higher impedance to a circuit which has a lower impedance level. The received signal is sent to the ADC for conversion of the analog signal to digital signal. The BA helps prevent the ADC from interfering with the down conversion operation and the LPF of the receiver board. Since the buffer amplifier receives the down-converted differential signal from the Gilbert Cell Mixer (GCM) being designed by ECE-23, the buffer amplifier was designed to have differential input and also differential output so that it can be connected to the ADC which is also a differential input ADC. The COTS part that was chosen was an operational amplifier (op-amp) P/N: THS4513 from Texas Instruments [8]. This op-amp is fully differential and has a bandwidth of 1600 MHz with a slew rate of 5100 V/ s. Designing the layout for buffer amplifier proved to be difficult because of its fully differential configuration. A slight change in the length of transmission lines will change the phase of the signal. The other design consideration was the distance between the two transmission lines. Since the pads of the chip are so close to each other, the transmission lines coming out of them will couple, which is undesirable. Therefore, the layout had to be designed to facilitate symmetry and not coupling.

The IC from TI is very small that it was not possible to drill holes underneath the center pad. So we drilled a hole very close to the chip but not directly underneath it. Once the layout was finalized we fabricated the circuit and tested it. After providing the necessary biasing conditions and the differential input signals we saw output signals were 180 degrees out of phase from one another but they had very small amplitude. It means the buffer amplifier which is designed to have a gain more than unity was not amplifying the signal. It just gave two differential signals at the output. These may be because of the leakage from the chip. So we decided to mount another chip and test it again.

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We tested it but again it started to oscillate at high frequencies. It was highly unstable at high frequencies. In our latest prototype, we used the same method we have used for the LNA. We have very fine holes underneath the ground pad for fine wire for proper grounding (see Figures F2 and F3). We also simulated out design on PSpice and tuned the circuit to give us a gain of 2dB and the flat gain bandwidth of 540 MHz. The results of PSpice are shown in Figure 4. We were able to practically implement this design but instead getting a gain of 2 dB we got a gain of 1dB (see Figure 5). But as can be seen from the Figure 6, both the inputs and outputs are 180 degree of phase and we have a flat gain bandwidth of around 540 MHz. Power Amplifier

A Power Amplifier is a device used to take a small input signal and convert it into a larger output signal. A COTS power amplifier is used for \direct up-conversion for a digital transmitter board. In such configuration, the power amplifier receives the signal from the Gilbert Cell Mixer and amplifies it before sending it to the antenna. Power amplifiers are usually optimized to have high efficiency, high P1dB compression, good return loss, good gain, and good heat dissipation. The choice of power amplifier depends on the application, cost, maximum transmit frequency, maximum stable gain (GMSG), thermal conduction, breakdown voltage, and the power handling capacity.

In previous years, senior design teams under Dr. Daryoush have used the P/N: AWM6430 by Anadigics, Inc. Unfortunately the amplifier was not stable in the low end of our desired frequency range (below 3.3 GHz). We therefore began talking with Anadigics’ engineers about our need for a stable amplifier for the full bandwidth from 3.1 to 3.6 GHz.

Eventually in the winter term, Anadigics mailed us samples and an evaluation board for a power amplifier P/N: AWT6283R (see Figure G4) that is still in development stage and is not in the market yet. We then verified the evaluation board against their preliminary data (see Figures G6, G8, G10). Once we were satisfied with the amplifier’s performance we designed a layout using Rogers RO3006 High Frequency Laminate (see Figure G1). We then milled out the board and populated it (see Figure G2).

In order to begin testing the amplifier and to solve some grounding issues we were concerned about, we designed a heat sink, at the Drexel Metal Shop, for the amplifier (see Figure G3). As it can be seen in the figure, the heat sink has fins on the bottom to dissipate the heat and has a protruding square in the top. This square fits into the hole where the heat pad of the power amplifier sits and is the same height as the RO3006 board. Adding heat sink compound and tapped screw holes provided us with the necessary grounding and heat dissipation.

After developing the heat sink we fully tested and characterized the power amplifier. Specifically we found the IP3, P1dB, Gain, Intermodulation distortion. Finally we found the S parameters (see Figure G5, G7, G9). We then tabulated the results and compared them to the Anadigics’ evaluation board (see Table 8). With similar results we incorporated the layout to the LO Poly-phase board (see Figure D1-D4).

Parameter Requirement

Frequency Range (GHz) 3.1-3.6 GHz Output Power (W) 0.5 W

Gain (dB) at least 60 dB AGC (dB) at least 40dB

Table 6. Requirement for Power Amplifier

Parameter AWM6430(old) AWT6283R(new) Frequency Range (GHz) 3.3-3.6GHz 3.4-3.8 GHz

Output Power(W) 0.25 W 1.5 W

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Gain (dB) 27 dB 30 dB Table 7. Comparison between AWM6430 and AWT6283R Power Amplifier

Parameter AWT6283R (Evaluation Board) AWT6283R(Prototype Board)

Output Power(W) 1.5 W 1.5 W Gain (dB) 30 dB 30 dB

P1dB (dBm) 31 dBm 30 dBm IP3 (dBm) 16.7 dBm 16.05 dBm

Table 8. Comparison between AWT6283R Evaluation Board and Prototype Board

Constraints Our senior design project had some setbacks throughout the year because of the need for

wire-bonding. In order to properly assemble the poly-phase circuit we need the assistance of an RF company to wire bond our die to a leadless chip carrier. This process would have cost us up to $600 but Advanced Control Components was gracious enough to give up 4 hours of their time to help us with our assembly. Wire bonding also makes this project difficult to manufacture at high rates in high quantities. The semi-conductor used in the poly-phase die is made of Indium gallium phosphide (InGaP) which is very soft and takes a very experienced technician to wire bond to the bonding pads.

In addition, the technology of wireless communications is always adapting and progressing so our project could potentially be improved as more advanced technology presents itself. The current infrastructure is geared towards the current 3G wireless networks. Our project could potentially force the manufacturing of new networks to support ultra wide band technology. The biggest constraint politically is the regulation of the communications bandwidth by the Federal communications Committee. These regulations made it difficult for our team to find commercially available parts at 3.158 GHz to 3.658 GHz.

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Budget

Table 9. Industrial Budget.

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Table 10. To Date Out of Pocket Budget *LO, LNA, PA, BA, 1 by 2 PD, 1 by 4 PD, Balun, Single Layer Capacitor, High Frequency Laminate

**Credited by ECE Department ***After ECE Department Rebate

Table 11. Original Out of Pocket Budget in Proposal

Throughout our project we have been successful in gaining free samples from the many different companies we contacted. Mini-Circuits supplied us with the necessary power dividers, Anadigics provided us with the power amplifier, and RFMD provided us with the low noise amplifier for our design. Synergy Microwave gave us the Local Oscillators we needed for our LO and Polyphase board, and Texas Instruments has provided us the Buffer Amplifier. During the duration of our project, Advanced Control Components offered us their assembly services through wire-bonding and engineering advice so we had to make the trip 4 times to get the assembly done. Although we have had some success in receiving samples, we still had to spend some money out of pocket in order to realize our design. The car rides to Advanced Control Components cost us $461.10. We also spent money on purchasing leadless chip carriers in order for us to surface mount a die to our Rogers board. The local oscillator in our design also needed an interface with a PC for programming purposes so we had to purchase two 25 pin DSub connectors. The final total for all of these parts and shipping cost our group $561.00. This total is much higher than our proposed budget because we did not account for multiple trips to Advanced Control Components, which is further away than Hybrid Tech, for us mis-handling our circuits. We also did not have a solution to our broken poly-phase board with the leadless chip carriers.

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Gantt Chart and Teamwork

Table 12. Gantt Chart showing respective responsibilities

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Throughout the course of our senior design project we had to meet certain deadlines set by the senior design committee. In order to have our deliverables on time, we created a Gantt Chart to help us visualize the entire timeline of our project. This organizational tool contained the due dates for each written report and oral presentation given by the senior design committee. Once we had our critical dates laid out, we created a detailed plan to allow for mistakes shipping and manufacturing parts, and also allotted time for unforeseen problems. Once we had a plan we made a separate section on the Gantt chart to put our suspense dates for each of our deliverables. All of our circuit prototype modules have been on schedule and are fully operational within datasheet specifications.

Concerning teamwork; our team worked very well together. Our team did not have the same team leader every term because each person’s unique skills were used at different phases of the project in order to maximize our efforts. The contribution of each team member went beyond RF circuitry throughout the duration of this senior design project. Each team member’s responsibilities can be seen in the columns below their name on the Gantt Chart (see Table 12).

Summary & Conclusions

We have finished the prototype layouts for the LO and PP board, LNA, Buffer Amplifier.

Our LO and PP board is fully assembled and has been initially tested. We have successfully made prototype modules for all the circuit components which closely met the data sheet and necessary system specifications.

References

[1] http://www.3gamericas.org/documents/UMTS_Forum_MBB_LTE_White_Paper_February_2009%5B1%5D.pdf [2] http://www.3gamericas.org/documents/applications_nov2004.pdf [3] http://www.synergymwave.com/Products/synthesizer/datasheets/FSW200400-100.pdf [4] http://www.wenzel.com/pdffiles1/Standard%20Parts/501s/50104608a.pdf [5] http://www.johansontechnology.com/images/stories/ip/baluns/Balun_3600BL14M100.pdf [6] http://www.mini-circuits.com/pdfs/SCN-2-35.pdf [7] http://products.rfmd.com/docdownload.jsp?docID=NN30-DSN-V27VVG23CM&tabname=TechLib [8] http://focus.ti.com/lit/ds/symlink/ths4513.pdf [9] D. M. Pozar, “Microwave Engineering”, John Wiley & Sons Inc., 2005 [10] Pranav Iyengar and A. S. Daryoush, "Circularly Polarized Array Ring Antenna for Ultra Wide Band Wireless Communications", Drexel University, ECE Department, Philadelphia, PA, 19104. [11] Tiwari, Swarup, Lu, Koanantakool and Amadou, “Sub-System Development for RFIC Based Ultra-Wide Band Base Station- Final Report is submitted to Dr. Daryoush and the ECE Senior Design Project Committee at Drexel University”, May 2007. [12] C.A Balanis, “Antenna Theory: Analysis and Design”, John Wiley & Sons Inc., March 2005. [13] Radmanesh, Matthew M., “Radio frequency and microwave electronics”, Prentice Hall PTR, c2001

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Appendix A

Figure A1. General block diagram for a Transmitter Board.

Figure A2. General block diagram for a Receiver Board.

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Figure A3. General block diagram for the Local Oscillator Polyphase Board.

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Appendix B

Figure B1. LO Prototype Module on RO3006

Figure B2. LO Evaluation Board provided by Synergy Microwaves

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Figure B3. Wide view of Prototype LO’s signal on Spectrum Analyzer

Figure B4. Layout of Prototype LO in ADS

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Appendix C

Figure C1. Poly-phase Prototype Module designed for RO3006 in ADS

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Figure C2. Polyphase wire bonding Diagram using 1 inch in diameter gold wire

Figure C3. Broken Poly-phase board from previous senior design teams

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Figure C4. Polyphase RFIC developed by previous Senior Design teams under Dr. Daryoush at 2.45 GHz

Figure C5. Purchased LCC to solve broken Poly-phase problem NOTE: top side view is on the left while bottom side is on the right

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Figure C6. Top of LCC with Polyphase IC epoxied and wire bonds

Figure C7. Poly-phase Prototype Module implemented

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Figure C8. Poly-phase Prototype Module Test Setup

Figure C9. Poly-phase Prototype Module Test Results NOTE: V0 – yellow, V90 – blue, V180 – red, V270 - black

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Appendix D

Figure D1. Mechanical Layout of LOPP Board

Figure D2. Layout of LOPP Board on ADS

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Figure D3. Actual circuit of LOPP Board before assembly

Figure D4. Actual circuit of LOPP Board after majority of assembly

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Figure D5. Balun Module Layout in ADS

Figure D6. Balun Module implemented on RO3006

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Table D1. Balun Data Sheet Specifications

Table D2. Balun Prototype Module Testing

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Figure D7. Amplitude Difference between the two output ports of Balun Module Prototype

Figure D8. Phase Difference between the two output ports of Balun Module Prototype

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Figure D9. 1 by 2 Power Divider Module Layout in ADS

Figure D10. 1 by 2 Power Divider Prototype Module implemented on RO3006

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Table D3. 1 by 2 Power Divider Data Sheet Specifications

Table D4. 1 by 2 Power Divider Prototype Module Testing Results

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Figure D11. Insertion Loss comparison for both output ports of 1 by 2 Power Divider Prototype Module

Figure D12. Insertion Loss Phase Difference between the two output ports of 1 by 2 Power Divider Module

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Figure D13. LOPP Testing Setup

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Appendix E

Figure E1: RF3866 Evaluation Board Schematic

Figure E2: RF3866 Layout

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Figure E3: RF3866 Evaluation Board

Figure E4: RF3866 Prototype Board Top View

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-25

-20

-15

-10

-5

0

5

10

15

1 3 5 7 9 111315171921232527293133

Out

put P

ower

(dB

m)

Input Power (dBm)

P1dB with 20 dBm Attenuator at Output of Eval Board

Linear …meas…

Figure E5: S-Parameters

Figure E6: P1dB with 20 dBm Attenuator at Output of Eval Board

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Figure E7: S21 (Gain) of Prototype Board with -35 dBm of Reference Signal

Figure 8: Intermodulation Distortion of Evaluation Board

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Figure 9: Intermodulation Distortion of Prototype Board

Figure 10: S11 for RF3866 Prototype Board

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Figure 11: S22 for RF3866 Prototype Board

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Appendix F

Figure F1: THS4513 Evaluation Board Schematic

Figure F2: THS4513 Evaluation Board Layout

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Figure F3: THS4513 Prototype Board

Figure F4. Buffer Amplifier Simulation Results for Gain and Group Delay

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Figure F5. Buffer Amp. Voltage Gain vs. Frequency

Figure F6: Output Waveform of Buffer Amplifier

-3

-2.5

-2

-1.5

-1

-0.5

0

0.5

1

Vol

tage

Gai

n, d

B

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Appendix G

Figure G1: Layout of AWT6283R Prototype Board

Figure G2: AWT6283R Prototype Board

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Figure G3: Heatsink of AWT6283R Prototype Board

Figure G4: AWT6283R Evaluation Board

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Figure G5: S21 of AWT6283R Prototype Board with 20 dB attenuator at the output and a reference signal of -15dBm

Figure G6: S21 of AWT6283R Evaluation Board

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Figure G7: S11 of AWT6283R Prototype Board

Figure G8: S11 of AWT6283R Evaluation Board

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Figure G9: S22 of AWT6283R Prototype Board

Figure G10: S22 of AWT6283R Evaluation Board

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Figure G11: P1dB of Evaluation board and Prototype Board

Figure G12: Intermodulation Distortion of Prototype Board

P1 dB Compression Point

0

5

10

15

20

25

30

35

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

Input Power (dBm)

Out

put P

ower

(dB

m)

Prototype boardEvaluation board

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c

Figure G13: Intermodulation Distortion of Evaluation Board

Figure G14: Evaluation Board Schematic

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Paul Miranda 16 Glenwood Ave

Jersey City, NJ 07306 201-978-5842

paul.d.miranda@us.army.mil

Education Drexel University, Philadelphia, PA Bachelor's Degree in Electrical Engineering, September 2009 Radio Frequency and Advanced Electronics Concentrations Security Clearance: Secret Internship Experience Advanced Control Component, Eatontown, NJ, March 2006 to September 2008

• Junior Design and Test Intern, • Assisted in the design, test, tune, and characterization of Phase Shifters, RF Switches, Amplifiers, High and

Low Pass Filter, and Attenuators (10 MHZ to 40 GHz) • Tuned a variety of devices using 10-30 mil gold ribbon stubs (ribbon bonding) and copper stubs (epoxy) • Worked extensively with Microwave Office and Ansoft Designer for simulating designs

Design Project School Year 2008-2009

• Designed components of a 4x4 MIMO ultra wide band base station • Selected Appropriate Local Oscillator according to specifications • Designed Layout in ADS to integrate with poly phase shifter • Conducted testing of local oscillator using spectrum analyzer

Radio Frequency Test Skills Tests (not limited too): Scattering Parameters, Noise Figure, Third Order Intercept Point, 1dB Compression, and Dynamic Range Software: Microwave Office, Ansoft Design, Advanced Design System, PSpice, Multi-Sim, Autolab Hardware: Vector Network Analyzers, Spectrum Analyzers, Oscilloscopes, Power Meters, Scalar Network Analyzers, and Noise Figure Meters Honors and Awards • Army ROTC 4 Year Scholarship: 2004-Present • ROTC Scholar Award: 2006 • Most Improve Cadet: 2005and 2008 • ROTC “Award for Excellence” Nominee: 2009 • World War II Society Cadet Leadership Award: 2005

Activities Army ROTC 2004-Present

• Cadet Command Sergeant Major (2009) in charge of Task Force Dragon Battalion • In charge of over 100 cadets • Developed time management, flexibility, and leadership skills.

Army ROTC Color Guard Captain 2008-2009 • Organized Color Guard Detail for events • Ensured cadets know the proper marching techniques

ARMY ROTC Ranger Challenge-2006 • Developed leadership skills in more technical areas through difficult physical tasks such as 10K forced road

march and the construction of rope bridges. Drexel University Cycling Team 2006-Present

• 2008 National Off Road Bicycle Association National Championship Qualifier

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