Upload File

risc-v soc fpga brings real-time to linux presenter ... · fpga bu – embedded strategy to be the...

  • Home
  • Documents
  • RISC-V SoC FPGA Brings Real-Time to Linux Presenter ... · FPGA BU – Embedded Strategy To be the leading provider of programmable RISC-V solutions Highly differentiated, open ISA
24
RISC-V SoC FPGA Brings Real-Time to Linux Presenter: Vishakh Rayapeta Date: 18 June 2019

Upload: others

Post on 05-Jun-2020

7 views

Category:

Documents


0 download

Report

TRANSCRIPT

Page 1: RISC-V SoC FPGA Brings Real-Time to Linux Presenter ... · FPGA BU – Embedded Strategy To be the leading provider of programmable RISC-V solutions Highly differentiated, open ISA

RISC-V SoC FPGA Brings Real-Time to LinuxPresenter: Vishakh Rayapeta

Date: 18 June 2019

Page 2: RISC-V SoC FPGA Brings Real-Time to Linux Presenter ... · FPGA BU – Embedded Strategy To be the leading provider of programmable RISC-V solutions Highly differentiated, open ISA

2

FPGA BU – Embedded StrategyTo be the leading provider of programmable RISC-V solutions

Highly differentiated, open ISA alternative to ARM AMP Mode: Simultaneous Linux + Real Time

Flexibility Enhances our low power position Enhances our security position Provenance enables full transparency for trusted

design A lower cost ASIC migration path than ARM

MCHP Foundation Board Member: Ted Speers MCHP Working Committee Member: Stuart Hoad,

Richard Newell Strategic Partnership with Soft 32-bit uCs, Hard Quad-core 64-bit uPs + uC Common MSS architecture, boards, ecosystem

A Comprehensive Ecosystem to Support RISC-V Development

Open. Lowest Power. Programmable RISC-V Solutions

Key RISC-V Foundation and Industry Partnerships

Page 3: RISC-V SoC FPGA Brings Real-Time to Linux Presenter ... · FPGA BU – Embedded Strategy To be the leading provider of programmable RISC-V solutions Highly differentiated, open ISA

3

Mi-V Soft CPUs (Available Now)

Core LE’s CoreMark Cache Mul/Div Floating Point Availability

CORE_RISCV_AXI4 10K 2.01 8K I and D Yes N/A Now

Mi_V_RV32IMAF_L1_AHB 26K 2.01 8K I and D Yes Single Precision Now

Mi_V_RV32IMA_L1_AHB 10K 2.01 8K I and D N/A N/A Now

Mi_V_RV32IMA_L1_AXI 10K 2.01 8K I and D Yes N/A Now

CORE_RISCV_AXI4 Based on Coreplex E31 (32bit) Separate AXI4 for memory access

Mi_V_RV32IMA_L1_AHB with SECDED available

Mi_V_RV32IMAFC_L1_AHB

Mi-V = Mi-V RISC-V Ecosystem RV32I = 32 bit integer machineM = Multiply and DivideA = Atomic InstructionsF = Single Precision Floating PointD = Double Precision Floating PointC = Compressed InstructionsL1 = Instruction and Data CacheAHB = AHB Bus InterfaceAXI = AXI Bus Interface

Page 4: RISC-V SoC FPGA Brings Real-Time to Linux Presenter ... · FPGA BU – Embedded Strategy To be the leading provider of programmable RISC-V solutions Highly differentiated, open ISA

4

SoftConsole Eclipse IDE

A single tool chain for RISC-V and ARM MCUs Easy migration from ARM to RISC-V

Running on Linux or Windows Hosts Bundled with example projects and RTOSs

Eclipse IDE Design Flow

Compiler

Debugger Demo/Eval Boards

Firmware Catalog

Sample Projects

Arduino ShieldPMOD

MikroBusUSB

Page 5: RISC-V SoC FPGA Brings Real-Time to Linux Presenter ... · FPGA BU – Embedded Strategy To be the leading provider of programmable RISC-V solutions Highly differentiated, open ISA

Introduction to PolarFire FPGA

Open, Lowest Power, Cost Optimized, Programmable SoC

Page 6: RISC-V SoC FPGA Brings Real-Time to Linux Presenter ... · FPGA BU – Embedded Strategy To be the leading provider of programmable RISC-V solutions Highly differentiated, open ISA

6

Data Route Zones Policy

Lowest Power Mid-Range FPGAs

Control Plane (PCIe, GigE, 10GE)

RF and Baseband Signal Processing

Video & Image Processing

Hardware Acceleration

Packet Processing & Traffic Management

10G Bridging & Aggregation

PortableCommunications

Low PowerOptics

Page 7: RISC-V SoC FPGA Brings Real-Time to Linux Presenter ... · FPGA BU – Embedded Strategy To be the leading provider of programmable RISC-V solutions Highly differentiated, open ISA

7

Mid-Range FPGA Landscape

PolarFire FPGAs deliver up to 50% lower power to mid-range

Transceiver Rate

Relative

Power & Cost

5G

10G

28G+

PERFORMANCE OPTIMZEDCOST / POWER OPTIMIZED

Only cost and power optimized FPGA with 12.7G SERDES• Power/cost

decrease from mid range FPGAs

• Performance upgrade from cost/power optimized FPGAs

Page 8: RISC-V SoC FPGA Brings Real-Time to Linux Presenter ... · FPGA BU – Embedded Strategy To be the leading provider of programmable RISC-V solutions Highly differentiated, open ISA

8

Lowest Power –Save Up to 50%

Enabling Application Performance at Significantly Lower Power

Static power 10x Reduction

Transceiver 2x Reduction

Total power up to 50% lower than best case competitor number

PolarFire Customer: $1.5/W in BOM cost saving due to power savings

Page 9: RISC-V SoC FPGA Brings Real-Time to Linux Presenter ... · FPGA BU – Embedded Strategy To be the leading provider of programmable RISC-V solutions Highly differentiated, open ISA

9

Security is All About LayersTo protect your information you need

Secure Hardware, Design Security and Data Security

Microsemi FPGAs provide a solid foundation for your security needsThe DPA logo is a trademark of Cryptography Research, Inc. used under license

Trust: Licensed Patent Protected DPA Resistance, NIST Certified Crypto Accelerators, Secure Supply Chain

Anti-Tamper: Secure Bitstream, Tamper Detection, Active Mesh, No Copying. Cloning, or Reverse Engineering

Information Assurance: Key storage using Physically Unclonable Function (PUF)Advanced Crypto AcceleratorsLicensed Patent Protected DPA Resistance Pass through License

“The number of IoT sensors is expected to approach 30 billion in 5 years – and each unit is a potential entry point for cyber-criminals” –The Economist Intelligence Unit, 4/11/2016

“Some call cybercrime the greatest transfer of wealth in human history” – The Center of Strategic and International Studies, July 2013, The Economic Impact of Cybercrime

Page 10: RISC-V SoC FPGA Brings Real-Time to Linux Presenter ... · FPGA BU – Embedded Strategy To be the leading provider of programmable RISC-V solutions Highly differentiated, open ISA

10

Exceptional Reliability

Error Free SEU immune Fabric Configuration No need to detect configuration errors

No scrubbing required No triple mode redundancy needed Lowers cost

Memories are also protected Built-in SECDED on 33 bit word

System Controller Suspend Mode for Safety Critical Applications

SEU a growing concern for equipment demanding 99.999% uptime

Flash FPGANo Error

SRAM FPGAFunctional Failure

Alpha / Neutronparticles strike routing matrix

SRAM Configuration Failures

Page 11: RISC-V SoC FPGA Brings Real-Time to Linux Presenter ... · FPGA BU – Embedded Strategy To be the leading provider of programmable RISC-V solutions Highly differentiated, open ISA

11

PolarFire Product Family

Extended Commercial (0⁰C-100⁰C) and Industrial (-40⁰C-100⁰C) Temperature Support for all Die Package Combinations - RoHS only

FeaturesPolarFire FPGA

MPF100 MPF200 MPF300 MPF500

FPGA Fabric

Logic Elements (4LUT + DFF) 109K 192K 300K 481KMath Blocks (18x18 MACC) 336 588 924 1480LSRAM Blocks (20 kbit) 352 616 952 1520uSRAM Blocks (64x12) 1008 1764 2772 4440Total RAM (Mbits) 7.6 Mbits 13.3 Mbits 20.6 Mbits 33 MbitsuPROM (kbits 297 Kbits 297 Kbits 459 Kbits 513 KbitsUser DLL's/PLL's 8 each 8 each 8 each 8 each

High Speed I/O

250 Mbps -12.7 Gbps Transceiver Lanes 8 16 16 24PCIe Gen2 Endpoints/Root Ports 2 2 2 2

Total I/O Total User I/O 284 364 512 584

Packaging

Type / Size / Pitch Total User I/O (HSIO / GPIO) GPIO CDRs / XCVRsFCSG325 (11x11, 11x14.5*, 0.5 mm) 170(84/86) 8/4 170(84/86) 8/4*FCSG536 (16x16, 0.5 mm) 300(120/180) 15/4 300(120/180) 15/4FCVG484 (19x19, 0.8 mm) 284(120/164) 14/4 284(120/164)14/4 284(120/164) 14/4FCG484 (23x23, 1.0 mm) 244(96/148) 13/8 244(96/148) 13/8 244(96/148) 13/8

FCG784 (29x29, 1.0 mm) 364(132/232)20/16

388(156/232) 20/16

388(156/232)20/16

FCG1152 (35x35, 1.0 mm) 512(276/236) 24/16

584(324/260) 24/24

Devices in the same package and family type are pin compatible

Additional Temp Grade: Military (-55⁰C-125⁰C) - Leaded packages only Note: FC484M package is a lidded package whereas the FCG484I package is not.

Page 12: RISC-V SoC FPGA Brings Real-Time to Linux Presenter ... · FPGA BU – Embedded Strategy To be the leading provider of programmable RISC-V solutions Highly differentiated, open ISA

PolarFire SoC Architecture

Open, Lowest Power, Cost Optimized, Programmable SoC

Page 13: RISC-V SoC FPGA Brings Real-Time to Linux Presenter ... · FPGA BU – Embedded Strategy To be the leading provider of programmable RISC-V solutions Highly differentiated, open ISA

13

Secure Communications and Portable Embedded Systems

Enabling Purpose-built, Real-time, Low Power systems

Smart Weapons, Drones and UAVsIndustrial IoT

Collaborative RobotsImaging and Machine LearningSafety Critical Systems

Page 14: RISC-V SoC FPGA Brings Real-Time to Linux Presenter ... · FPGA BU – Embedded Strategy To be the leading provider of programmable RISC-V solutions Highly differentiated, open ISA

14

Real-time Linux?

Wide spread Linux adoption Rich OS with thousands of applications to choose from

Requirements still exist for real-time while running Linux Safety critical The ability to deterministically monitor the execution environment.

Real-time system control Completing tasks deterministically, on time every time.

Securing the IoT Execute a trusted execution environment deterministically for consistent

results.

Working with our partner We have been able to architect a complex SoC FPGA that provides Determinism and a rich OS within the same multi-core CPU cluster

Page 15: RISC-V SoC FPGA Brings Real-Time to Linux Presenter ... · FPGA BU – Embedded Strategy To be the leading provider of programmable RISC-V solutions Highly differentiated, open ISA

15

Variable Execution Time in Typical Application Processors

SMP 1

L2

DDR4

CPU

SMP 2

CPU

SMP 3

CPU

SMP 4

CPU

5332800

5333000

5333200

5333400

5333600

5333800

5334000

5334200

ISR Execution Time Variability

Branch predictors, cache misses and lack of coherency affect determinism negatively

Page 16: RISC-V SoC FPGA Brings Real-Time to Linux Presenter ... · FPGA BU – Embedded Strategy To be the leading provider of programmable RISC-V solutions Highly differentiated, open ISA

16

Turn off the CPU branch predictors Convert L1 to Tightly Integrated Memory Make sure all cores coherent to the memory subsystem Make the memory system deterministic Share coherent memory for message passing

Real-Time and Linux

SMP 1

L2

DDR4

RTBP Off

E51 U54

SMP 2

U54

SMP 3

U54

SMP 4

U54

Direct Access

Coherent Buffers

5722600

5723100

5723600

No Execution Time VariabilityRESULT

Page 17: RISC-V SoC FPGA Brings Real-Time to Linux Presenter ... · FPGA BU – Embedded Strategy To be the leading provider of programmable RISC-V solutions Highly differentiated, open ISA

17

PolarFire SoC - RISC-V Enabled Innovation Platform

Freedom to Innovate in• Linux and Real-Time

• Securely Connected IoT systems• High-Rel Safety Critical Systems

• Thermal and Power Constrained Systems

Page 18: RISC-V SoC FPGA Brings Real-Time to Linux Presenter ... · FPGA BU – Embedded Strategy To be the leading provider of programmable RISC-V solutions Highly differentiated, open ISA

18

Low Power MSS Low power RISC-V micro-architecture 2MB L2 cache: increases cache hit/miss ratio 0.5-0.9W lower power

Power: RISC-V vs Alternatives

0.0

200.0

400.0

600.0

800.0

1000.0

1200.0

1400.0

1600.0

PolarFireSoC Zynq Zynq+

Processor Power4000 DMIPS load, DDR@32b x 1600Mb/s

DDR

ProcessorDynamic

ProcessorStatic

Comp A 22nm

Comp A 16nm

PolarFire SOC28nm

0

2

4

6

8

10

12

14

16

PolarFireSoC Zynq Zynq+

4x4x60MHz DFE Power

Static

XCVR

lProcessor

Dynamic

4x4x60MHz RRH

368MHz732DSP126k LE

10xCPRI7 1x12.5G JESD

4000 DMIPS

4GB/s DDR

Comp A 22nm

Comp A 16nm

PolarFire SOC28nm

LTE Digital Front End Application 3-7W lower power for 60MHz 4x4 MIMO

implementation

Page 19: RISC-V SoC FPGA Brings Real-Time to Linux Presenter ... · FPGA BU – Embedded Strategy To be the leading provider of programmable RISC-V solutions Highly differentiated, open ISA

19

PolarFire SoC inherits best in class PolarFire FPGA Security DPA resistant bitstream programming Anti-tamper Cryptographical bound supply chain assurance Physically Unclonable Function (PUF) True random number generator Side channel resistant crypto coprocessor

PolarFire SoC has:+ Secure Boot+ Spectre and Meltdown immunity+ Physical memory protection+ SECDED on all memories

Security for Defense, Ready for IoT

Page 20: RISC-V SoC FPGA Brings Real-Time to Linux Presenter ... · FPGA BU – Embedded Strategy To be the leading provider of programmable RISC-V solutions Highly differentiated, open ISA

Pre-silicon PolarFire SoC Development Options

Page 21: RISC-V SoC FPGA Brings Real-Time to Linux Presenter ... · FPGA BU – Embedded Strategy To be the leading provider of programmable RISC-V solutions Highly differentiated, open ISA

21

Freedom to Start Software Development

Eclipse IDE Design Flow

Compiler

Debugger

Firmware Catalog

Sample Projects

GDB

Free Rapid Software Development and Debug Capabilities Without Hardware

Complete PolarFire SoC Processor Subsystem Model

Available now

Page 22: RISC-V SoC FPGA Brings Real-Time to Linux Presenter ... · FPGA BU – Embedded Strategy To be the leading provider of programmable RISC-V solutions Highly differentiated, open ISA

22

HiFive Unleashed Development BoardHiFive Unleashed Expansion Board

PolarFire SoC Embedded Experts Development Kit

Freedom to Begin Hardware Development

+

Page 23: RISC-V SoC FPGA Brings Real-Time to Linux Presenter ... · FPGA BU – Embedded Strategy To be the leading provider of programmable RISC-V solutions Highly differentiated, open ISA

23

PolarFire SoC Summary

PolarFire FPGA Award Winning Features 30-50% Lower power Defense grade security Exceptional reliability Smallest, lowest power, secure form factors – 11x11, 16x16, 19x19

PolarFire Microprocessor Subsystem Linux and real time in a deterministic, coherent CPU cluster 30-50% Lower power Defense grade secure boot Spectre/Meltdown immune SECDED on all memories

Click here to learn more

https://www.microsemi.com/product-directory/soc-fpgas/5498-polarfire-soc-fpga
Page 24: RISC-V SoC FPGA Brings Real-Time to Linux Presenter ... · FPGA BU – Embedded Strategy To be the leading provider of programmable RISC-V solutions Highly differentiated, open ISA

Thank You


Design of FPGA based 8-bit RISC Controller IP core using VHDL

The Updated Status of RISC-V SW · The Updated Status of RISC-V SW Kito Cheng and Greentime Hu 2019 RISC-V Workshop Taiwan

RISC-V SoC FPGA Brings Real-Time to Linux · 2 Microchip’s FPGA Strategy To be the leading provider of programmable RISC-V solutions § Highly differentiated, open ISA alternative

CHIPS Alliance Overview - RISC-V

RISC-V Privileged Architecture

RISC-V: Enabling a New Era of Open Data-Centric …innovation.wdc.com/downloads/RISC-V-Presentation-Brief-forWeb.pdf · PRESENTATION BRIEF 3 Presentation Brief | RISC-V: Enabling

RISC-V BitManip Task Group

Porting HelenOS to RISC-V

"A FPGA Implementation of a MIPS RISC Processor for ...jecook/thesis/Victor_thesis.pdf · ABSTRACT A FPGA Implementation of a MIPS RISC Processor for Computer Architecture Education

Celerity: An Open Source RISC-V Tiered Accelerator Fabriccseweb.ucsd.edu/~mbtaylor/papers/HC29.21.430-Celerity-RISC-V-Davidson-UCSD.pdfGeneral-Purpose Tier: RISC-V Rocket Cores •

Introduction to RISC-V · Introduction to RISC-V Jielun Tan, James Connolly Last updated 09/2019 1. Overview What is RISC-V Why RISC-V ISA overview Software environment Project 3

Software-Programmable FPGA IoT Platform - RISC-V 3 Agenda •Introduction •Who we are •IoT Platform in FPGA •Lattice’s IoT Vision •IoT Platform Overview •Architecture Overview

Extending RISC-V for Application-Specific Requirements · Extending RISC-V for Application-Specific Requirements 5th RISC-V Workshop ... –Performance critical code is highlighted

Porting Android onto RISC-V

RISC-V: Berkeley Hardware for Your Berkeley Software ... · RISC-V ISA • Fifth RISC ISA from Berkeley, so RISC-V • Modular ISA: Simple base instruction set plus extensions •

How to go from a RISC-V Core RVfpga-SoC to a RISC-V SoC?

Embedded Software Development for RISC-V Based SoC RISC …Embedded Software Development for RISC-V Based SoCs Embedded Software Development for RISC-V Based SoC. Page §2 MINRES Technologies

Embedded Software Development for RISC-V Based SoC RISC-V … · 2019-10-15 · Embedded Software Development for RISC-V Based SoC. Page §2 ... Agile embedded software development

RISC-V INTERNATIONAL ASSOCIATION ASSOCIATION …

Andes RISC-V CPU IP Provides · 2019-08-15 · Taking RISC-V® Mainstream. 5. Why Andes - 1: Best RISC-V Extensions Bring Andes strength to RISC-V Core family Architecture beyond

RISC-V Introduction

The RISC-V Instruction Set Manual · The RISC-V Instruction Set Manual ... 7.1 PLIC Overview ... This document describes the RISC-V privileged architecture,

Tue0830 Workshop Intro & RISC-V Foundation Overview … · § RISC-V Foundation Overview ... and open RISC-V instruction set architecture together ... Tue0830 Workshop Intro & RISC-V

FreeBSD/RISC-V and Device Drivers - FreeBSD.org …br/freebsd_riscv.pdf ·  · 2017-11-24FreeBSD/RISC-V and Device Drivers ... (ARM, MIPS, RISC-V, x86) •Device Drivers (Sound,

RISC-V Perf Tool Status...2019/03/10  · Andes Technology 2019 RISC-V Workshop Taiwan Taking RISC-V ® Mainstream 2 Outline Big picture: perf record RISC-V perf Current status, and

Mi-V RISC-V Ecosystemww1.microchip.com/downloads/en/DeviceDoc/00002911A.pdf · 2019-01-28 · FPGAs & SoCs Mi-V RISC-V Ecosystem Open. Lowest Power. Programmable RISC-V Solutions

Risc V 4-way Superscalar

RISC-V Instruction Formatsinst.eecs.berkeley.edu/~cs61c/resources/su18_lec/Lecture7.pdf · RISC-V Feature, n×16-bit instructions • Extensions to RISC-V base ISA support 16-bit

Evaluation of RISC-V RTL with FPGA-Accelerated Simulation · MIDAS Custom Compiler Passes 10 §FIRRTL: IR for RTL transforms ... -RTL state snapshots for energy modeling r FPGA-Accelerated

Industrial-Strength High-Performance RISC-V … be the highest single thread performance 64-bit RISC-V processor • Allow RISC-V to be positioned alongside highest performance processors

State of the Union - RISC-V · 2019-06-12 · o RISC-V RISC-V Timeline 3 RISC-V ISA project begins 1st Rocket tapeout, EOS14, 45nm User ISA v2.0 IMAFD Hot Chips 2014 First Linux Port

MicroSemi PolarFire FPGA the Avalanche Board with Open ...Running a Linux-Capable Open Source Soft SoC on the Avalanche Board with MicroSemi PolarFire FPGA RISC-V Summit, Dec 3 2018

The future of operating systems on RISC-VThe future of operating systems on RISC-V ... Introduction to RISC-V RISC-V status Selected RISC-V topics RISC-V and open hardware: the future

with RISC-V Igniting the Open Hardware Ecosystem · your favorite software project to RISC-V ... – Initial presentation at RISC-V workshop in December 2017 ... – Low-speed Peripherals:

The RISC-V Instruction Set Manual Volume II: Privileged ...€¦ · 1.1 RISC-V Hardware Platform Terminology A RISC-V hardware platform can contain one or more RISC-V-compatible processing