Dec 2015 P.Gargini RC4

Paolo Gargini

Chairman ITRS2.0

Fellow IEEE, Fellow I-JSAP Intel Fellow (1995-2012)

Roadmap Benefits Past, Present and

Future

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Dec 2015 P.Gargini RC4

International Electron Device Meeting, December 1975

Second Update of Moore’s Law

2

4

7

9

13

1

3

5 6

8

10 11 12

14 15 16

0

19 18 17

20

1961

1959

19

60

1962

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63

1964

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1966

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67

1968

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69

1970

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1972

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1974

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75

1976

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1978

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79

1980

1965

1975

Log 2

of t

he n

umbe

r of

com

pone

nts p

er in

tegr

ated

func

tion

Year

2X/Year

2X/2Year

2

Dec 2015 P.Gargini RC4 3

Moore’s Law and Dennard’s Scaling Laws Convergence

50% AREA READUCION GENERATION TO GENERATION

50%

=> 30% LINEAR FEATURE REDUCTION

S=0.7

Dec 2015 P.Gargini RC4

First Age of Scaling (Self-aligned Silicon Gate)

Phase 1

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Dec 2015 P.Gargini RC4

IC Industry at a Glance (1975-2003)

Driver Cost/transistor -> 50% Reduction

How 2x Density/2 years (Moore)

Method Geometrical Scaling (Dennard)

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Dec 2015 P.Gargini RC4

Gate Dielectric Scaling

1

2

3 To

x eq

uiva

lent

(nm

)

4 8 12

Monolayers

4

0

1999

2001

2003

2005

1997 NTRS

You Are Here!

Silicon substrate

1.2nm SiO2

Gate

6

From My Files

Dec 2015 P.Gargini RC4 7

Dec 2015 P.Gargini RC4

Tutorial for SEMI P.Gargini

1998 ITRS Update

• Participation extended to: EECA, EIAJ, KSIA, TSIA at WSC on April 23,1998

• 1st Meeting held on July 10/11,1998 in San Francisco

• 2nd meeting held on December 10/11,1998 at SFO• 50% of tables in 1997 NTRS required some changes• 1998 ITRS Update posted on web in April 1999

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Dec 2015 P.Gargini RC4

ITRS 1.0

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Dec 2015 P.Gargini RC4

Second Age of Scaling (Equivalent Scaling)

Phase 2

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Dec 2015 P.Gargini RC4

The Ideal MOS Transistor

From My Files

Fully Surrounding Metal Electrode

High-K Gate Insulator

Fully Enclosed, Depleted Semiconductor

Low Resistance Source/Drain

Drain Source Metal Gate Insulator

Band Engineered Semiconductor

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Dec 2015 P.Gargini RC4

IC Industry at a Glance (2003->2021)

Driver Cost/transistor-> 50% Reduction

How 2x Density/2 years (Moore)

Method Equivalent Scaling ( ITRS1.0)

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Dec 2015 P.Gargini RC4 13

Dec 2015 P.Gargini RC4

Dec 2015 P.Gargini RC4

Incubation Time n  Strained Silicon

• 1992->2003 n  HKMG

• 1996->2007 n  Raised S/D

• 1993->2009 n  MultiGates

• 1997->2011 ~ 12-15 years

Drain Source Metal Gate Insulator

1998

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Dec 2015 P.Gargini RC4

NRI Funded Universities Finding the Next Switch

UC Los Angeles C Berkeley UC Irvine UC Sana Barbara Stanford U Denver Portland State U Iowa

Notre Dame Purdue Illinois-UC Penn State Michigan UT-Dallas Cornell GIT

UT-Austin Rice Texas A&M UT-Dallas ASU Notre Dame U. Maryland NCSU Illinois UC

Columbia Harvard Purdue UVA Yale UC Santa Barbara Stanford Notre Dame U. Nebraska/Lincoln U. Maryland Cornell Illinois UC Caltech UC Berkeley MIT Northwestern Brown U Alabama

SUNY-Albany GIT Harvard Purdue RPI Columbia Caltech MIT NCSU Yale UVA

Over 30 Universities in 20 States

SPIN

TUNNEL FET

GRAPHENE SPIN LOGIC

GRAPHENE

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Dec 2015 P.Gargini RC4

Dec 2010

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Dec 2015 P.Gargini RC4

5

7

10 Te

chno

logy

Nod

e (n

m)

2017 2015 2013

14

2019

2013 ITRS 19

2021

3

1

Technology Node Scaling Today’s Challenge

Dec 2015 P.Gargini RC4 20

Dec 2015 P.Gargini RC4

Vertical Logic Architecture

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Dec 2015 P.Gargini RC4

Third Age of Scaling (3D Power Scaling)

Phase 3

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Dec 2015 P.Gargini RC4

IC Industry at a Glance (2021->203X)

Driver Cost/transistor & power reduction

How 2x Density/2 years (Moore)

Method 3D Power Scaling (ITRS2.0)

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Dec 2015 P.Gargini RC4

The Different Ages of Scaling (Different methods for different times)

①  Geometrical Scaling (1975-2003) ①  Reduction of horizontal and vertical physical dimensions in

conjunction with improved performance of planar transistors

②  Equivalent Scaling (2003~2021) ①  Reduction of only horizontal dimensions in conjunction with

introduction of new materials and new physical effects. New vertical structures replace the planar transistor

③  3D Power Scaling (2021~203X) ①  Transition to complete vertical device structures.

Heterogeneous integration in conjunction with reduced power consumption become the technology drivers

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Dec 2015 P.Gargini RC4

More Moore Beyond Moore

More than Moore

Heterogeneous Integration

System Integration

Customized Functionality O P S Y S T E M

A P P L E T S

Outside System Connectivity

Beyond 2020

ITRS 2012

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Dec 2015 P.Gargini RC4

1991 Micro Tech 2000 Workshop Report

1994NTRS 1992NTRS 1997NTRS

21th Anniversary of TRS

Japan Korea Europe Taiwan USA

http://www.itrs2.net

2001 ITRS 1999 ITRS 1998 ITRS Update

2000 ITRS Update

2002 ITRS Update

2004 ITRS Update

2006 ITRS Update 2003 ITRS 2005 ITRS 2007 ITRS

2008 ITRS Update

2010 ITRS Update 2009 ITRS 2012 ITRS

Update 2011 ITRS

2013 ITRS

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Dec 2015 P.Gargini RC4

ITRS 2.0 (2014-15)

http://www.itrs2.net

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Dec 2015 P.Gargini RC4

Q: How do we get back to exponential performance scaling?

IEEE Rebooting Computing Initiative

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Dec 2015 P.Gargini RC4 30

Dec 2015 P.Gargini RC4

NTRS

End of Traditional Scaling in Sight

ITRS 1.0

Equivalent Scaling Research

3D Power Scaling

NNI

International

US Initiatives

Launch of USG Nanotechnology

Launch of Eu/Japan Nanotechnology

Agreement on US research coordination

NRI

INC

Yearly Conference on Nano Eu/Japan/US

Equivalent Scaling Goes into

Production

Global Semiconductor Industry

High-k/Metal Gate. FinFET

ITRS 2.0

1997 1998 2003 2007 2011 ~2021 2000 2005 2015

Moore’s Law Continues

Continuous Scaling

International Nanotechnology Investments

FCRP

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Dec 2015 P.Gargini RC4

Rebooting Computing

2003 2012 2020 2030 2035 2015 2025

Moore’s Law Continues

Global Computer Industry

Computer industry Close to frequency and power limits

US Initiatives

NSCI

ITRS 2.0

IEEE RC International Rebooting Computing Investments

3D Power Scaling

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