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Robu st Low Powe r VLSI Robust Low Power VLSI Deliberate Practice Variation-Resilient Building Blocks for Ultra-Low-Energy Sub-Threshold Design Alicia, Kyle, Yanqing Dept. of Electrical Engineering, University of Virginia April 03, 2013

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Robust Low Power VLSI What is Variation?  Devices performing differently from how they were designed to operate  Effects  Robustness  Performance  Causes  Process  Voltage  Temperature 3

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Page 1: Robust Low Power VLSI R obust L ow P ower VLSI Deliberate Practice Variation-Resilient Building Blocks for Ultra-Low-Energy Sub-Threshold Design Alicia,

RobustLowPow

erVLSI

RobustLowPowerVLSI

Deliberate Practice

Variation-Resilient Building Blocks forUltra-Low-Energy Sub-Threshold Design

Alicia, Kyle, YanqingDept. of Electrical Engineering, University of VirginiaApril 03, 2013

Page 2: Robust Low Power VLSI R obust L ow P ower VLSI Deliberate Practice Variation-Resilient Building Blocks for Ultra-Low-Energy Sub-Threshold Design Alicia,

RobustLowPow

erVLSI 2

Motivation Energy minimization for BSNs Operate circuits in sub-threshold Tradeoffs

Sensitivity to variation Performance

Page 3: Robust Low Power VLSI R obust L ow P ower VLSI Deliberate Practice Variation-Resilient Building Blocks for Ultra-Low-Energy Sub-Threshold Design Alicia,

RobustLowPow

erVLSI 3

What is Variation? Devices performing differently from

how they were designed to operate Effects

Robustness Performance

Causes Process Voltage Temperature

Page 4: Robust Low Power VLSI R obust L ow P ower VLSI Deliberate Practice Variation-Resilient Building Blocks for Ultra-Low-Energy Sub-Threshold Design Alicia,

RobustLowPow

erVLSI 4

Variation in Sub-Threshold Types of Variation

Random Dopant Fluctuation

Carrier Mobility W/L

Lithography Threshold Voltage

Oxide Thickness Analysis Tools

Monte Carlo Corner Analysis

𝐼=𝐼 0𝑒(𝑉 𝑔𝑠−𝑉 h𝑡 )𝑛𝑽 𝑻

[1]

Page 5: Robust Low Power VLSI R obust L ow P ower VLSI Deliberate Practice Variation-Resilient Building Blocks for Ultra-Low-Energy Sub-Threshold Design Alicia,

RobustLowPow

erVLSI 5

Metrics for Evaluation

1. Energy Consumption2. Gate Delay3. Delay Variation 4. Robustness

1. Noise Margins (output swing)5. Area overhead

Page 6: Robust Low Power VLSI R obust L ow P ower VLSI Deliberate Practice Variation-Resilient Building Blocks for Ultra-Low-Energy Sub-Threshold Design Alicia,

RobustLowPow

erVLSI 6

Attacking the ProblemBlock/Logic Level• ???

Standard Cells• ???

Device Level• ???

Page 7: Robust Low Power VLSI R obust L ow P ower VLSI Deliberate Practice Variation-Resilient Building Blocks for Ultra-Low-Energy Sub-Threshold Design Alicia,

RobustLowPow

erVLSI 7

Research Questions1. How do you design sub-threshold

standard cells capable of MHz operation that are variation-resilient?

Page 8: Robust Low Power VLSI R obust L ow P ower VLSI Deliberate Practice Variation-Resilient Building Blocks for Ultra-Low-Energy Sub-Threshold Design Alicia,

RobustLowPow

erVLSI 8

Research Questions1. For an inverter, what design choices

can we do to make it variation resilient?

Area overhead Delay Variation Robustness

Noise Margins (output swing)

Page 9: Robust Low Power VLSI R obust L ow P ower VLSI Deliberate Practice Variation-Resilient Building Blocks for Ultra-Low-Energy Sub-Threshold Design Alicia,

RobustLowPow

erVLSI 9

Research Questions1. After considering the inverter, what

other techniques can we apply to other standard cells?

1. Combinational2. Sequential

Page 10: Robust Low Power VLSI R obust L ow P ower VLSI Deliberate Practice Variation-Resilient Building Blocks for Ultra-Low-Energy Sub-Threshold Design Alicia,

RobustLowPow

erVLSI 10

References1. Process Variations, University of Maryland, Advanced

VLSI Design:http://www.csee.umbc.edu/~cpatel2/links/640/lectures/lect10_process_var.pdf

2. Reynders, N.; Dehaene, W., "Variation-Resilient Building Blocks for Ultra-Low-Energy Sub-Threshold Design," Circuits and Systems II: Express Briefs, IEEE Transactions on , vol.59, no.12, pp.898,902, Dec. 2012.


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