robust low power vlsi r obust l ow p ower vlsi synthesis based design techniques for ultra low...
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Rob
ust
Low
Power
VLSI
Robust
LowPower
VLSI
Synthesis Based Design Techniques for Ultra Low Voltage Energy Efficient SoCs
Yanqing ZhangFebruary 27th, 2012
Rob
ust
Low
Power
VLSI 2
Motivation for Ultra Low Voltage DesignP
ow
er
Performance
Wireless Sensor Nodes
Portable Electronics
Desktop Applications
Servers and Data Centers
Rob
ust
Low
Power
VLSI 3
Motivation for Ultra Low Voltage Design
Application Characteristics: 1. Device lifetime
2. Robust functionality 3. Relatively small form factor4. Speed not a major concern
[1]
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Low
Power
VLSI 4
Motivation for Ultra Low Voltage DesignTrend has been to use voltage scaling…BUT IT’S NOT THAT SIMPLE!
[2]
Almost 2 orders-of-magnitude increase in energy efficiency
[1]
Rob
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Low
Power
VLSI 5
0.2 0.4 0.6 0.8 1 1.20VDD
0
10
20
30
40
50
60
% Minimum energy point occurs here
% Leakage energy/Total energy
Vth
Key Challenges: Increased Significance of Leakage
% Leakage Energy/Total Energy for a Critical Path
Rob
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Low
Power
VLSI 6
0 20 40 60 80 100Delay (ns)
120 1400
50
150
Coun
t
100
Key Challenges: Sensitivity to VariabilityLocal Variation of Delay for 4 Stage Inverter Chain
Exponential dependence on Vth increases uncertainty in timing closure metrics. This decreases chip yield.
Rob
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Low
Power
VLSI 7
Key Challenges: Efficient Hardware Selection
COTS Based WSN
Fully functional TX and DSP,But 20mW power consumption
Short lifetime
Custom IC Based IC
No DSP. 3 day lifetime.Lacks functionalityLifetime still short
[3]
High Speed SoCs
Very powerful. Low power so it is not power hog.Not for ULV domain
Conventionally, we consider SPEED as main factor for system. Our requirements are: system LONGEVITY and ROBUST FUNCIONTALITY. We can really improve SoCs in ULV domain if we change our strategy.
Rob
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Low
Power
VLSI 8
Summary of Dissertation GoalsPROJECT 1 (completed)
• Design architecture for a Body Area Sensor Node (BASN) SoC capable of battery-less operation.
PROJECT 2• Local variation robust standard cell library for sub-Vt• Synthesis flow reducing leakage energy
PROJECT 3• Hold time robust design methodology
PROJECT 4• Alternative approach to DVFS
Rob
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Low
Power
VLSI 9
Outline• Motivation• Hardware Selection for Energy Efficient SoC (BASN chip)
• Motivation• Hypothesis• Approach• Results
• Library Design and Characterization at ULVs for Robust Timing Closure
• Hold Time Analysis and Timing Closure Method for Sub-threshold
• Latch Based Design for Single-VDD Alternative Approach to DVFS
Rob
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Low
Power
VLSI 10
Project 1: Hardware Selection for Energy Efficient SoC (BASN chip)
Rob
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Low
Power
VLSI 11
Wireless body area sensor nodes (BASN) enable inexpensive continuous monitoring of patients
Battery replacement/charging for body-worn devices may not be feasible or desirable
Information
Assessment, Treatment
Motivation
Rob
ust
Low
Power
VLSI 12
MCU
MotivationCOTS Based WSN
Fully functional TX and DSP,But 20mW power consumption Short lifetime
Custom IC Based IC
No DSP. 3 day lifetime.Lacks functionalityLifetime still short
[3]
• BASNs exemplify design space requiring energy efficiency to the extreme
• State-of-the-art low power modules help…but not full solution• On-chip processing a MUST (TX duty cycle, node size), but
‘throwing on an MCU’ entails high power ~100µW• Judicial hardware selection needed
Rob
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Low
Power
VLSI 13
Hypothesis
ADC RFAFE
Boost Converter
VoltageRegulation
µController
Memory
DSP
Power Mgmt.
RF Kick-StartTEG
Signal Path
Power Path
VBOOST
ECG
EMG
EEG
~60µW
We can achieve a battery-less (energy harvesting) BASN SoC capable of various bio-signal acquisition and flexible data processing with state-of-the-art low power circuit design and judicial hardware selection
Rob
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Low
Power
VLSI 14
MCURR+AFib Accel.30-Tap FIR Accel.
0 50 100 150 200Delay (µs)
Mea
sure
d E
nerg
y/O
p (p
J)
Accelerators:• Programmable FIR• Heart rate (R-R) extraction• Atrial Fibrillation (AFib) detection• Band energy envelope detection• Direct memory access (DMA)• Packetizer
Energy Efficiency / Sample
110x
6800x
4000x
0
1
2
3
4
30 Tap FIR MCU 6.3 nJAccel 57.6 pJ
Env. Detect MCU 3.6 nJAccel 530 fJ
R-R Extract MCU 12 pJAccel 3 fJ
Approach
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Low
Power
VLSI 15
This Work [18] [19] [20] [21] [22]
Sensors ECG, EMG, EEG ECG Neural, ECG, EMG, EEG EEG ECG, TIV Temp,
PressureSupply 30mV, -10dBm 1.2V 1V 1V 1.2V 0.4V/0.5VE Harvesting Thermal, RF X X X X Solar
Power Mgmt. DPM, Clock/Power gate
Clock gate X X X Power gate
Gen. Purp. MCU
1.5 pJ/Instr @ 200kHz X X X X 28.9pJ/Instr
@ 73kHz
Accelerators Many ASIC X ASIC Few X
Memory 5.5kB (0.3V-0.7V) 42kB (1.2V) X x 20kB
(1.2V) 5kB (0.4V)
Digital Power 2.1µW ~12µW N/A 2.1µW 500µW 2.1µWTotal Power 19µW 31.1µW 500µW 77.1µW 2.4mW 7.7µW
Significance
• Has lower power, lower minimum input supply voltage, and more complete system integration than all other reported wireless BASN SoCs
• first wireless biosignal acquisition chip powered solely from thermoelectric harvested power
Rob
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Low
Power
VLSI 16
Outline• Motivation• Hardware Selection for Energy Efficient SoC (BASN chip)
• Motivation• Hypothesis• Approach• Results
• Library Design and Characterization at ULVs for Robust Timing Closure
• Hold Time Analysis and Timing Closure Method for Sub-threshold
• Latch Based Design for Single-VDD Alternative Approach to DVFS
Rob
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Low
Power
VLSI 17
Project 2: Library Design and Characterization at ULVs for Robust Timing Closure
Rob
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Low
Power
VLSI 18
0 0.05 0.1 0.15 0.2 0.250
0.05
0.1
0.15
0.2
0.25
VNAND2-IN-NOR2-OUT
VN
OR
2-I
N-N
AN
D2
-OU
T
Motivation
Static CMOS NOR2
Static CMOS NOR2 FAILS SNM @ TT corner with local variation
Rob
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Low
Power
VLSI 19
Standard cell library essential to synthesis, but scaling industry standard cells aren’t sufficient for sub-Vt—fail SNM with variation
Motivation
Problem:Weak devices (PMOS) +Stacked transistor variation
Rob
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Low
Power
VLSI 20
Motivation
Logic Gate
Logic Gate
Logic Gate
Logic Gate
Logic Gate
Logic Gate
LEAKING WITHOUT PURPOSE!
[4]
Rob
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Low
Power
VLSI 21
-18log(delay)
0
Prob
abili
ty (%
)
2-stage4-stage8-stage
.014
16-stage
σ/µ= .019 .022 .024
-16 -14 -12
4
8
12
16
Conventional method of ‘process corner based timing closure’ un-suitable for sub-Vt
Doesn’t capture sensitivity to local variation
Motivation
Rob
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Low
Power
VLSI 22
Hypothesis
1. Using TX-gate style logic, we can achieve lower energy consumption for a given yield when compared to static CMOS gates.
2. We can achieve decreased total energy with a flow that optimizes leakage on non-critical paths, but still ensures path yield with variation aware cell characterization.
Rob
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Low
Power
VLSI 23
1. TX-Gate Based Gate Design
A
AB
2. Long Length Low Leakage Gate Design
3. Setup/Hold Optimized Register
4. Synthesis Gate Replacement
6. Clock Network Extraction
5. Place and Route Retiming
7. Post Clock Extraction Retiming
8. Circuit Simulation and Evaluationlang = spectreparameters …INVX1 A B VDD VSS ….sim opt …
New Cell Library
Proposed Approach
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Low
Power
VLSI 24
Anticipated Contributions
• Minimizing leakage in TX-based cells• Matching speed with static CMOS counterparts• Layout compactness issues
Anticipated Bottlenecks
• Variation immune TX-Gate standard cell library (publication)• Variation aware path leakage optimization technique
(publication)
Rob
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Low
Power
VLSI 25
Outline• Motivation• Hardware Selection for Energy Efficient SoC (BASN chip)
• Motivation• Hypothesis• Approach• Results
• Library Design and Characterization at ULVs for Robust Timing Closure
• Hold Time Analysis and Timing Closure Method for Sub-threshold
• Latch Based Design for Single-VDD Alternative Approach to DVFS
Rob
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Low
Power
VLSI 26
Project 3: Hold Time Analysis and Timing Closure Method for Sub-threshold
Rob
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Low
Power
VLSI 27
Motivation
tSKEW
Clock
Clock+skew
Data 1
Data 2
Clock Clock +skew
Data 1 Data 2Skew is increased in sub-Vt because of increased PVT variation sensitivity
Rob
ust
Low
Power
VLSI 28
Motivation
Clock w/ BAD slew
Data 1
Data 2
Clock w/ BAD slew
Data 1 Data 2Slew is decreased in sub-Vt because of increased PVT variation sensitivity
Rob
ust
Low
Power
VLSI 29
Motivation
Clock
Clock
Data 1 Data 2Hold time, clock-q uncertainty in sub-Vt because of increased PVT variation sensitivity
Data 1
Data 2
Rob
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Low
Power
VLSI 30
Motivation
tSKEW
• Conventional method to solve hold time:• Use clock tree synthesis to design a tree with many levels
(control skew) and large buffers(control slew)• Use buffer insertion to take care of hold time, clock-q
THIS WON’T WORK IN Sub-Vt!
Rob
ust
Low
Power
VLSI 31
Yiel
d (%
)
1 2 3 435
45
55
65
75
85
Level of clock tree
Motivation
• More levels=more skew! Contrary to conventional widsom…
Rob
ust
Low
Power
VLSI 32
Motivation
• Buffer insertion energy costly!• And still doesn’t solve our problem (subject to variation too…)
PCLKPREGPHOLD
Level of clock tree
Yield (%)40 50 60 70 80 90 100
% P
ower
Ove
rhea
d of
Buff
ers o
f
0
10
20
30
40
50
60
70
1
2
3
Tota
l Circ
uit P
ower
(Nor
mal
ized)
96 97
Rob
ust
Low
Power
VLSI 33
Hypothesis
1. We can achieve a similar parameter controlling method suitable for sub-Vt by re-analyzing the effects of each parameter.
2. We can achieve a more energy efficient method for a given yield constraint using a novel two-phase clock based timing scheme
Rob
ust
Low
Power
VLSI 34
tSKEW
tSKEW
tSKEW
EDA Tools MethodFind the lowest energy
approach to accomplish:
1. Limited Skew
2. Judicial Hold Buffer Insertion
4. Tolerable Clock Slew
3. Tolerable Data Slew
5. Robust Register Less tSKEW
Less tSKEWMaster Clock Slav
e Cl
ock
Less tSKEW
Less tSKEWMaster Clock Slav
e Cl
ock
Less tSKEW
Less tSKEWMaster Clock Slav
e Cl
ock
DLL
VS
No More Buffers!
Two-phase Clock Method
Approach
Rob
ust
Low
Power
VLSI 35
tSKEW
Master Clock
tSKEW
Slave Clock
Master Clock Slav
e Cl
ock
Split register into 2 positive transparent latches
Tune DLL to fix timing
Master Clock+skew
1
Data 1
Data 2
Data 1 Data 2
2
3
4
Approach
Rob
ust
Low
Power
VLSI 36
Anticipated Contributions
• Simulation time for coming up with design methodology• DLL design for two-phase clocking• Incorporating timing scheme into synthesis flow
Anticipated Bottlenecks
• Design methodology using EDA tools suitable for sub-Vt (publication)
• A novel hold time fixing scheme using two-phase clocking (publication)
Rob
ust
Low
Power
VLSI 37
Outline• Motivation• Hardware Selection for Energy Efficient SoC (BASN chip)
• Motivation• Hypothesis• Approach• Results
• Library Design and Characterization at ULVs for Robust Timing Closure
• Hold Time Analysis and Timing Closure Method for Sub-threshold
• Latch Based Design for Single-VDD Alternative Approach to DVFS
Rob
ust
Low
Power
VLSI 38
Project 4: Latch Based Design for Single-VDD Alternative Approach to DVFS
Rob
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Low
Power
VLSI 39
85
SNM
Yie
ld (%
)
90
95
100
Register Type
99.5698.96
88.57
Motivation
• Recent research has demonstrated near ideal energy savings using this concept by using three voltage islands.
[5]
Rob
ust
Low
Power
VLSI 40
0
Workload
0
Ener
gy
0.2 0.4 0.6 0.8
0.2
0.4
0.6
0.8
1
1Single-VDDMVDDPDVS
Motivation
• Potential drawback: when considering total energy through DC-DC converter, may compromise energy savings
Rob
ust
Low
Power
VLSI 41
Hypothesis
1. We can achieve better energy efficiency in DVFS by dynamically switching level of pipelining in a latch based design running off of single VDD for a certain frequency range.
Rob
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Low
Power
VLSI 42
Logic BlockLevel 0:
Logic Block/2Level 1: Logic Block/2
/4Level 2: /4 /4 /4
Approach
Rob
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Low
Power
VLSI 43
Approach
DCDC
DCDC
DCDC
Blk1 Blk2 Blkn
Energy,Power
Delay
Latch-based Design
DCDCEnergy,Power
Delay
Rob
ust
Low
Power
VLSI 44
Anticipated Contributions
• Minimizing the overhead for switching the amount of pipelining
• Latch-based timing issues
Anticipated Bottlenecks
• Analysis of optimal latch pipelining for ULVs (publication)• Dynamic pipelining alternative approach to DVFS (publication)
Rob
ust
Low
Power
VLSI 45
Publications1. Fan Zhang, Yanqing Zhang et al., “A Batteryless 19µW MICS/ISM-Band Energy Harvesting Body Area Sensor Node SoC”, to appear in 2012 International Solid-State Circuits Conference, 02/2012.2. Benton H. Calhoun et al., “Body Sensor Networks: A Holistic Approach from Silicon to Users”, IEEE Proceedings3. Yanqing Zhang and Benton H. Calhoun, “The Cost of Fixing Hold Time Violations in Sub-threshold Circuits”, 2011 Subthreshold Microelectronics Conference, 09/20114. Yanqing Zhang et. al., “Energy Efficient Design for Body Sensor Nodes”, Journal of Low Power Electronics and Applications, 04/2011.5. Benton H. Calhoun, Sudhanshu Khanna, Yanqing Zhang, Joseph Ryan, and Brian Otis, “System Design Principles Combining Sub-threshold Circuits and Architectures with Energy Scavenging Mechanisms”, International Symposium on Circuits and Systems (ISCAS), Paris, France, pp. 269-272, 05/2010.
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Low
Power
VLSI 46
References[1] A. Barth, “TEMPO 3.1: A Body Area Sensor Network Platform for Continuous Movement Assessment”, BSN 2009.[2] B. Calhoun and A. Chandrakasan, “Characterizing and Modeling Minimum Energy Operation for Subthreshold Circuits”, ISLPED 2004[3] S. Rai, et. al., “A 500uW Neural Tag with 2uVrms AFE and Frequency-Multiplying MICS/ISM FSK Transmitter”, ISSCC 2009[4] H. L. Yeager, et. al. “Microprocessor Power Optimization through Multi-Performance Device Insertion”, VLSI 2004[5]Y. Shakhsheer et. al. “A 90nm Data Flow Processor Demonstrating Fine Grained DVS for Energy Efficient Operation from 0.25V to 1.2V”, CICC 2011
Rob
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Low
Power
VLSI 47
Schedule: Key Anticipated MilestonesProject Milestone (Publication for…) Expected DateBASN chip Hardware platform
comparisonCompleted
BASN chip Batteryless SoC chip CompletedLibrary Design TX-gate based standard cells 09/2012Library Design Variation aware leakage
optimization12/2012
Hold Closure Sub-Vt hold time method using EDA tools
12/2012
Latch DVFS Latch pipelining analysis in sub-Vt
01/2013
Latch DVFS Alternative DVFS approach 09/2013Hold Closure Two-phase clock method 10/2013
Rob
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Low
Power
VLSI 48
THANK YOU!
“PhD Degrees:You have to be Lin it to Lin it”
-Yanqing Zhang
Rob
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Low
Power
VLSI 49
How Does Synthesis Relate?
2. HDL DescriptionModule SoC_components (in, out, clk)…
1. Determine ArchitectureMCU?Memories?Accelerators?Bus protocol?
3. Standard Cell Design
4. CharacterizationINV:delay=…POWER=…Leakage=…
5. Gate Translation
6. Timing Closure
Clock
Data
7. Place and Route
8. Chip Verification
DUT
Rob
ust
Low
Power
VLSI 50
Key Challenges: Weakened Drive Strength
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8VDD
102
103
104
105
106
107
108
109
Freq
uenc
y (H
z)
[2]
We would like a slower drop-off in frequency, because this leads to drastic increase in leakage
Ring Oscillator Frequency
Rob
ust
Low
Power
VLSI 51
0.2 0.4 0.6 0.8 1 1.2VDD
0
5
10
15
20
25
Ratio
of D
rain
Cur
rent
2.6
140nm/90nm140nm/180nm140nm/270nm280nm/90nm420nm/90nm
Increasing area
Key Challenges: Unbalanced FET Strengths
Standard cells are designed at nominal VDD . We can’t just scale VDD and expect balance. This constrains speed and increases leakage
Relative Strength of NMOS/PMOS
Rob
ust
Low
Power
VLSI 52
Approach
Energy per Instruction
Energy per Sample Delay per Sample
Max achievable data rate
GOPS / W
GPP 2.62 pJ 210 pJ 8 us (80 cycles) 125 kHz 4.76 FPGA N/A 2.22 pJ 94.5 ns (1 cycle) 10 MHz 450 ASIC N/A 0.23pJ 6.18 ns (1 cycle) 150 MHz 4348
• Implemented same R-R extraction algorithm• Same technology, manual optimization of codes• 100X energy efficiency for ASICs vs. GPPs• Use GPPs sparingly, steer processing to ASICs
Rob
ust
Low
Power
VLSI 53
ADC
DMA/SRAM
Bio-signal Accelerators
Packetizer
Power and Channel control
Sa
mp
ling
rate
con
tro
l
Power/clock gate, clock rate, and bus control
Du
ty c
ycle
, da
ta r
ate
con
tro
l
Dig
itize
d V
BO
OS
T
DPMChip
program
LNA
VBOOST
VGA
IMEM
Approach
MCU
Rob
ust
Low
Power
VLSI 54
Example of Mixed Path
ENV Detect
FIR
Example Custom Path
RR+AFib
FIR
Generic Path
MCU
Flexible Architecture for Data Processing
MCU
Event-Based Burst
Store and Burst
Stream
If event
ProcessedData
Flexible Architecture for Data Transmission
Data for TX
4kB DMem
4kB DMem
ECG
EMG
EEG
AFE
Data processing Data transmission
• Data processing: max flexibility (generic path) or max efficiency (biosignal accelerators)
• Data transmission: supports modes from streaming (100% DC) to rare event detection (~0% DC)
MCU: microcontroller
Approach
Rob
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Low
Power
VLSI 55
Time (s)0 1 93 95 97 99 101 103 105 107
1
…
…
…
AFib beginsChip detects AFib
0.8
0.6
0.4
0.2
0
0.5
0
• When a rare AFib occurs, TX is enabled to transmit the last 8 beats of ECG (in the data memory).
• 19 µW total chip
Inpu
t E
CG
Sig
nal
(V)
AF
ib D
etec
t (V
)Results
Rob
ust
Low
Power
VLSI 56
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
0.4
0.6
0.8
1
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.80
0.5
1
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.80
0.5
1
1.798 1.7981 1.7982 1.7983 1.7984 1.7985 1.79860
0.5
1
1.7979 1.798 1.7981 1.7982 1.7983 1.7984 1.7985 1.7986 1.79870
0.5
1
655 ms
650 µs
Header Data CRC
VBoost sample
ADC IN(V)
TX EN
TX DATA
Time (s)
• Every 5s, VBOOST is sampled to check for sufficient energy
• DPM enables RF crystal oscillator (20ms) and TX (650µs)
• 19 µW total chip
Results
Rob
ust
Low
Power
VLSI 57
Cell Type
99.0
Yiel
d (%
)
99.2
99.4
99.6
99.8
100
Standard cell library essential to synthesis, but scaling industry standard cells aren’t sufficient for sub-Vt—fail SNM with variation
Motivation
Rob
ust
Low
Power
VLSI 58
0 20 40 60 80 100Delay (ns)
L=90nm
0
Occ
urre
nce
(%)
L=180nmL=270nmL=360nm
2
4
6
Make the cells bigger? Won’t work, greater active energy, not an insurance to
robustness Even if it did work, area at least quadruples
Motivation
Rob
ust
Low
Power
VLSI 59
0 0.05 0.1 0.15 0.2 0.250
0.05
0.1
0.15
0.2
0.25
VNAND2-IN-NOR2-OUT
VN
OR
2-I
N-N
AN
D2
-OU
TPreliminary Results
Increased SNM @ FS corner
Static CMOS NOR2
TX-Gate NOR2
Rob
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Low
Power
VLSI 60
0 0.05 0.1 0.15 0.2 0.250
0.05
0.1
0.15
0.2
0.25
VNAND2-IN-NOR2-OUT
VN
OR
2-I
N-N
AN
D2
-OU
TPreliminary Results
Increased SNM @ SS corner
Static CMOS NOR2
TX-Gate NOR2
Rob
ust
Low
Power
VLSI 61
0 0.05 0.1 0.15 0.2 0.250
0.05
0.1
0.15
0.2
0.25
VNAND2-IN-NOR2-OUT
VN
OR
2-IN
-NA
ND
2-O
UT
Preliminary Results
TX-Gate NOR2
TX-Gate NOR2 PASSES SNM @ TT corner with local variation
Rob
ust
Low
Power
VLSI 62
-800Delay (ns)
1
Occ
urre
nce
(%)
tholdtc-q, slew=329nstc-q, slew=419nstc-q, slew=750nstc-q, slew=1200ns
-400 0 400 800
2
3
4
5
6
7
8
9
0
Preliminary Results
• Hold time is quite immune to slew variation• Slew affects clock-q—there is a limit to slew before clock-q
becomes detrimental
Rob
ust
Low
Power
VLSI 63
Preliminary Results
• Low power DLL makes novel two-phase timing scheme possibly worthy
P2p jitter
Frequency Power % Jitter/Freq Main Contribution
DLL 373 ps 100 MHz 15 uW 3.73% Low Power
Header/Footer Array
CLK_INCurrent Starved Inverters
Weak Latches
Level Restorers
Out_b
Out
Rob
ust
Low
Power
VLSI 64
85
SNM
Yie
ld (%
)
90
95
100
Register Type
99.5698.96
88.57
Motivation
• DVFS provides the ability to trade-off energy and delay to cater to variable workloads
[4]
Rob
ust
Low
Power
VLSI 65
Approach
Logic BlockLevel 0:
tc-q, ElatchPleak,latch
tsetup, ElatchPleak,latch
tlogic, ElogicPleak,logic
Delay: tc-q+ tsetup + tlogic = PER Energy: 2Elatch + Elogic + PER(Pleak,logic + 2Pleak,latch)
Logic BlockLevel 1:
Delay: tc-q+ tsetup + tlogic/2 = PER Energy: 3Elatch + Elogic + PER(Pleak,logic + 4Pleak,latch)
Logic Block
Level 2:
Delay: tc-q+ tsetup + tlogic/4 = PER Energy: 5Elatch + Elogic + PER(Pleak,logic + 8Pleak,latch)
Delay: tc-q+ tsetup + tlogic/2n = PER Energy: (2n +1)Elatch + Elogic + PER(Pleak,logic + 2n+1Pleak,latch)
Is this energy efficient? (2n +1)Elatch + αElogic + (tc-q+ tsetup + tlogic/2n)(Pleak,logic + 2n+1Pleak,latch)
Rob
ust
Low
Power
VLSI 66
28
Average (tc-q+tsetup)/2 (ns)
0
Intr
insi
c En
ergy
/lat
ch (f
J)
30 32 34 36
1
2
38
3
40
Preliminary Results
• Efficiency of latches have the potential to mitigate the pipelining overhead of this scheme
Rob
ust
Low
Power
VLSI 67
0.2 0.4 1 1.20.6 0.8
Delay (ms)
10
Ener
gy (f
J)
30
50
0
70
1.4
90
110 RegLatch
Preliminary Results
• Efficiency of latches have the potential to mitigate the pipelining overhead of this scheme