rofiling fpga floor planning effects on timing closure · profiling fpga floor-planning effects on...
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PROFILING FPGA FLOOR-PLANNING EFFECTS ON TIMING CLOSURE
FPL 2012
Jaren Lamprecht, Brad Hutchings
Brigham Young University
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FPGA Floor-planning
• Ever-larger FPGA devices increase placement problem difficulty
• Vendors suggest floor-planning to guide placement
• A floor-plan is a map of design submodules to physical FPGA regions
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How to Floor-plan?
• What aspect ratios are best for submodules that comprise the floor-plan?
• How much area should be allocated for a submodule?
• What impact do area constraints have on the maximum clock rate for a submodule?
• What guidelines should be followed when assigning submodules to physical locations on the FPGA?
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Xilinx Device Tiles
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DSP
BRAM
CLB
Interconnect
10 T
iles
13 Tiles
VIEWED WITH
RAPID SMITH
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Independent Submodule Implementation
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Submodule Resource Requirements
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Submodule Logic LUTs Memory LUTs Registers BRAMs DSPs FFT 2574 571 4001 5 12 FIR 3106 36 7376 0 100 FP 13270 450 21584 12 40 Microblaze 1395 84 1443 0 3 Mult 362 23 466 0 0 Picoblaze 113 34 135 0 0
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Submodule Baseline Clock Constraints
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FIR Submodule without Area Constraints
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Area Constraint Variation
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100,000’s of Implementations
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Area Constraint Generator
BUILT ON
RAPID SMITH
For each submodule: • Aspect Ratio: all ratios from ints 1 to 5. • Area Overhead: 0-150%, 10% step • Seeds: all MAP seeds (-t [1…100]) • Scripted constraint generation
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Submodule Implementation Results
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Submodule Implementation Results
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Submodule Implementation Results
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Submodule Implementation Results
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Submodule Implementation Results
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Submodule Implementation Results
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General Results
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• Any combination of aspect ratio and area overhead can meet timing constraints
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General Results
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• Any combination of aspect ratio and area overhead can meet timing constraints
• Above 20% area overhead, most combinations meet timing at least as often as implementations without area constraints
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General Results
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• Any combination of aspect ratio and area overhead can meet timing constraints
• Above 20% area overhead, most combinations meet timing at least as often as implementations without area constraints
• At or below 20% area overhead, aspect ratio noticeably impacts results. Moderate aspect ratios preferred.
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Exceptional Results
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• FIR submodule cannot meet timing at all combinations
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Exceptional Results
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• FIR submodule cannot meet timing at all combinations
• Prefers 2.0 aspect ratio
One Vertical Tile Hop
Two Horizontal Tile Hops
Equivalent Wire Delays
Aspect Ratio = (W/H) = (2/1) For Minimizing Maximum Wire Delay
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Exceptional Results
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• FIR submodule cannot meet timing at all combinations
• Prefers 2.0 aspect ratio
• Area Constraints crossing the central clock column are troublesome
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Submodule Floor-planning Guidelines
• Area constraints do not prevent a submodule from meeting Fmax.
• Resource area overhead should be greater than 20%.
• Tile aspect ratio is less important, but 2.0 minimizes maximum wire delay.
• Area constraints should not cross the central clock column.
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Future Work
• System Designs – Can we draw the same conclusions when we
use hard macros in larger systems? – What is the impact of routing spill-over in
system designs?
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