rope.memory

8/13/2019 Rope.memory

1/14

THE ROPE M MORY A PERM NENT STOR GE DEVICEP uttnerElectronic Instruments DivisionBurroughs CorporationPhiladelphia 7, Pennsylvania

INTRODUCTIONA powerful way of increasing the capabilityand flexibility of digital computing systems is

through the use of permanent storage memories. Such memories are also known as readonly memories or NDRO electrically unalterable memories. As an example of the application of a permanent memory, consider a computer used for control purposes. Generally,such systems are physically small, relativelyinexpensive, and are not required to performa variety but rather a restricted category ofcomputations. The problem of program andconstant input and storage in such systems isconsiderable. Permanent memory can satisfythe input and storage function required in sucha system in an inexpensive manner. t can,furthermore be packaged in such a manner asto minimize volume requirements; in any event,the volume occupied by the store for such anapplication is less than that required for tapeor other inputs. In both large and small scalecomputers, permanent memory can be used forthe storage of supervisory routines, input/out-put function routines, and, in the case of therope memory, performing logic.The rope memory is a true permanent storagedevice in that the information content of thememory is fixed by construction; any changesin the information content require that thedevice be rebuilt or exchanged. Memories inwhich data can be altered by replacing a changeable data element are classed as semi-permanent memories . While this distinction may be

5

logically tenable, it will not be considered inthis paper: the changeability being consideredhere as simply a special case of rebuilding.Rope memories have been used in a number ofcomputing systems; the use of a rope memoryin a computer being designed by the M.l. T.Instrumentation Laboratory for the Apollospace craft was announced recently.I5

The emphasis of this paper is on rope memories. The relation of a rope memory to a conventional read/write memory can only be basedon the question of whether or not a permanentstorage device can be used in a particular application. In order to place the properties of ropememories in their proper place in the class ofpermanent storage devices, some other techniques of this type will be discussed. ( No comparison will be attempted with permanentmemories based on optical or photographicprinciples.) These other techniques have received more attention up to now; the discussionto follow is based on the belief that ropes meritsimilar attention, all the more so since theygive the opportunity for a greater range ofapplications.REVIEW OF SOME PERMANENTMEMORY SCHEMES

Before entering on a discussion of rope memories, we shall briefly describe various otherpermanent memory schemes, the description ofwhich will help in placing the information concerning rope memories into proper perspective.The permanent memory schemes to be described

From t e co ect on o t e Computer H story Museum (www.computer story.org)


2/14

46 PROCEEDINGS-FALL JOINT COMPUTER CONFERENCE, 1963below are 1 capacitative type, 2) electromag-netic coupling type, and 3 permanent magnettwistor type. These memories have in commonthe following features:

1 They are organized in a linear select mode.2 Each storage element stores one bit of in-formation.3 Output signals are of the order of a fewmillivolts.4) The information state of the memories

can be changed by a relatively uncompli-cated procedure, i.e., by changing cardswhich form the basis of informationstorage.

5) Access is random6 Some batch fabrication techniques arepossible.At the conClusion of the discussion concern-

ing rope memories, we shall return to thesepcints and examine them in the light of thebehavior of rope memories.Capacitative Type 4 11. 14. 20

Schematically, this memory can be represented as shown in Figure 1 A voltage pulsedirected along anyone of the horizontal wordlines will be detected on a sense line if that lineis coupled to the word line by a capacitor; other-wise, no pulse will appear on the sense line. Aninterrogation pulse applied to a word line causesall bits of that word to be read out in parallel.

The word and sense lines are etched on sep-arate printed circuit boards. These boards arethen oriented in such a manner that the wordand sense lines are orthogonal. A metallizedcard insulated on both sides by a layer of mylaris sandwiched in between these boards. If ahole is punched in the card at the position wherea word and sense line intersect, a small (about

pf) capacitor is created, thus coupling thesense to the word line corresponding to a 1bit. The absence of a hole makes capacitativecoupling between the lines impossible. Writingis thus accomplished by punching holes in themetallized card in a pattern in accordance withthe information to be stored. The metallizedcard itself is grounded. Memories of this typehave been reported to operate at 5 me rates,with outputs of about mv for storage capacity

WORD LINES RE HORIZONT LSENSE LINES RE VERTIC L

Figure 1. Schematic representation of the capacitativepermanent memory.

of 105 bits. Worst case analysis of noise con-ditions shows that a SIN ratio of 10:1 is attainable.

The techniques for fabricating memories ofthis type are evidently suited to batch processesthat should yield relatively inexpensive stores.Mechanical alignment is a problem that mustbe considered in the design of this type memory.The information state of the memory can bechanged by changing the punched metalHzcdcards.lectromagnetic Coupling TypeThis particular technique is based on the factthat the mutual inductance between two con-

ductors having a fixed geometrical relationshipis a function of the medium separating them.f an alternating current, I, is caused to flow

in one of a pair of one-turn coils, an output willbe generated across the terminals of the secondcoil which is proportional to :M ) dI/dt. The



3/14

THE ROPE MEMORY A PERMANENT STORAGE DEVICE 47induced emf in the second coil can be reducedfor a constant geometry by inserting a shielding material between the coils. Thus, forexample the insertion of a copper plate of0.04 mm thickness between two coils of 6.5 mmdiameter separated by a distance of 0.75 mmcauses a 23 db reduction in the induced emf.Binary information can thus be stored as theabsence or presence of shield between the coilsand can be detected as the absence or presenceof an induced emf.

The primary coil is the excitation coil; thesecondary coil is the sensing coil. Since exci tation coils and sensing coils can be connectedin series as shown in Figure 2 it is possibleto manufacture arrays of coils by printed circuittechniques. The excitation coils are etched onone board the sensing coils are etched on asecond board. The orientation of these twoboards relative to one another is such that thelong axes are orthogonal. Each row of excitation coils represents one word the sensing coilsrepresent bits. The system is word organized.

Storage of information is effected by sand-wiching a prepunched insulated metal card between a pair of boards containing excitationand sensing coils. Holes are punched at the intersection of sensing and excitation coils atpositions which are to store I bits. At positions which are to store 0 bits no holes arepunched. The relative outputs have alreadybeen discussed above. Mechanical alignment is

INFORM TIONPL NE

Figure 2. Electromagnetic coupling type permanentmemory construction.

extremely critical here since the holes musthave a very definite geometrical relationshipto the sense and excitation coils in order not toaffect the mutual inductance. Again storedinformation can be changed by exchangingcards. A memory of this type is reported asoperating at 1.5 mc. Excitation currents usedwere 200 m o Outputs are not explicitly re-ported but can be computed to be about 50 mvwithout taking attenuation into account. Worstcase SiN ratios at the amplifier output are reported to be 30 db.Permanent Magnet Twistor Type 2 5. 7. 10

The twistor is employed in a novel mannerin this type of memory. Information is notstored in the twistor, but rather as the absenceor presence of permanent magnets. Associatedwith each twistor element there is a permanentmagnet whose function is to generate an external field which will inhibit the twistor fromswitching if that element is to store a 0 bit.Alternately if the twistor element is to storea I bit it is not to be inhibited from switching hence no permanent magnet is associatedwith it. Those twistors inhibited from switching will not change state on being interrogated;those twistors not inhibited will switch fromone remanent state to the other upon being interrogated. It is thus necessary to follow upeach interrogation pulse with a reset pulse.

In constructing a permanent magnet twistortype memory the first step is to enclose twistorwires and their returns within mylar tape. Thisassembly is then bonded to solenoid mountingboards. The solenoids themselves are preparedby photoetching. The permanent magnets area nickel-cobalt alloy and are formed on a cardeither by photoetching or electrodeposition.Some 2 816 permanent magnets (bits) can bedeposited on a card having an area of 55 in 2giving a density of about 52 bits/in2. Thetwistor wires and tape are continuous; theassembly of wire tape, and solenoid boards isfolded concertina fashion into a stack. Provi-sion is made to guide the magnet card intoproper registration with the solenoid board.

I t is easy to imagine that alignment problemsare critica l here especially in view of the factthat twistor elements may interact if spaced tooclosely together.) Memories with capacities of



4/14

48 PROCEEDINGS-FALL JOINT COMPUTER CONFERENCE, 19631.44 X 106 bits have been reported, with anoperational cycle of 5 p.sec. Drives requiredare 2.0 amperes for the solenoids. Outputsshown for a 4,096 word module are 4 mv forones and 0.8 mv for zeroes , with a switch

ing time of about 2 p.sec.THE ROPE lVIEMORYl, 6, 8, Hi, 21Principle o peration

To illustrate the principle of operation ofrope memories, suppose that a rope is to beconstructed using 2n cores. t must be possibleto select each core uniquely. For purposes ofselection, each core is threaded by a selected setof n out of 2n inhibit lines. All cores are alsothreaded by a common set and reset line. Initially all cores are in the same remanent state.Two inhibit registers are used for the purposeof selecting a given core. One of the registersstores the address of the core to be selected,the other register stores the complementedaddress of the core. These are the D and Cregisters respectively. Associated with each ofthe 2n bits in the registers is a driver which isenabled if the bit is a 1 ; one driver is con-nected to one inhibit line. The set line is enabledsimultaneously with the inhibit lines; the setand inhibit pulses are of equal amplitude butopposite polarity. The amplitude of each pulseis greater than the switching threshold of thecore. The polarity of the set pulse is such thatin the absence of any inhibit pulses it willswitch a core fully. The polarity of the inhibitpulses is such as to prevent a core from switching-the inhibit p'ulses will drive the corefurther into saturation.

The selected core is not threaded by any ofthe enabled inhibit lines and is thus switchedby the set pulse. During this phase of the operation (called the selection phase), the cores actas null decoders21. Referring to Figure 3, wesee that the core will be set if, and only if, noneof the threaded Dn or Cn line drivers is en-abled. Hence,

Do C) C2 Do C1 C2 1Do .... DIl C1 C2 ....Do Dn . C1 C2 1

Figure 3.

The reset pulse is of the same amplitude asthe set and inhibit pulses. Its polarity is suchthat it will reset the core that was set duringthe selection phase of the rope memory operatingcycle. During the read phase the core outputobtained as a consequence of the application ofthe reset pulse is used to generate the information pattern. At the end of the reset pulse, allcores are again in the same remanent state.This selection scheme is also known as theRajhman switch16

Each core may store m bits; this requires theuse of m sense lines. Information patterns aregenerated by threading a sense line through acore if the bit to be stored is a 1 ; otherwise,the core is bypassed by the particular senseline-these lines correspond to 0 bits as nooutput will appear across them when the coreis reset. The sense lines are common to allcores; a given sense line will thread those coreswherein a I is to be stored in the bit positionrepresented by that sense line and will bypassthose cores wherein a 0 is to be stored in thebit position represented by that sense line.

Figure 4 illustrates the wiring scheme for arope memory of eight words (n==3). In theillustration each core stores a three-bit word.The information stored is the address of theword storing it. For a rope consisting of eightcores, there are six inhibit lines; three of theseare associated with the direct register, the otherthree lines are associated with the comple-mented register. Assume that the data storedin word 010 is to be read out. The operation isas follows:



5/14

THE ROPE MEMORY A PERMANENT STORAGE DEVICE 9

INHIBIT REGISTERSC 0

Fig-ure 4a. Rope Memory Wiring Scheme.

Do _____ --'0 1 .J L ____ _____02 ____CO J L ___ ____CI t ____C .J L____LJ L L

SETJI__ .jRESET - - - - t

OUTPUT I 1 \1SELECTWANDREAD010

~W SELECTANDREAD100DASHED LINES SHOW UNDAMPEDMODE OF OPERATION

Figure 4b. Timing Diagram for Rope MemoryOperatkn.

1) 010 is stored in the direct inhibit register.101 is stored in the complemented inhibitregister.

2) During the selection phase, the set lineand the drivers corresponding to I inthe registers are enabled.

3) Core 010 will be set since none of the enabled inhibit lines thread it.

4) During the read phase, the reset line isenabled and the information stored in theword is transferred to the output registervia the sense lines.

The wiring pattern of the inhibit lines canbe generalized as shown in Table 1 (The LSBof the address is taken as k==O.

TABLE Ikth bit of Dk Ckaddress

0 threads does not thread1 does not thread threads

Rope rganizationRope memories may be organized in two dif

ferent ways. The m bits stored by a given coremay be considered as the m bits of one word.Alternately, each of the m bits stored by a givenrope will be referred to as the one-core-perferent words. These two ways of organizing acore will be referred to as the one-core-perword and one-core-per-output bit modes ofstorage respectively. Regardless of the organization, the bits stored by anyone core are readout in parallel.

A rope organized on a one-core-per-wordbasis is a random access memory. It is possibleto subdivide the m bits stored per core into nequal parts of n bits each so that a core maybe considered as storing m n words of n bitseach. This requires that one of m n sets ofsense lines be selected to read out the properinformation; for example, if 256 cores are tostore four words each for a total of 1024 words,the address must be 10 bits long, eight to selectthe proper core and two to select the properone of four words.

A one-core-per-output bit organization requires that the rope be read out sequentially inorder that the bits of a word appear in properorder. While this mode of operation is possible,it is not extremely desirable. For one thing, thetime elapsed to fully read out a word becomessomewhat prohibitive: given a cycle time of8fLsec and a k-bit word, 8k fLsec would elapsebefore one word is fully read out. For anotherthing, the number of bits that a core can storeis necessarily related to its inner diameter sincethis is the factor limiting the number of linesthat may be threaded through it. Typically , acore having an I.D. of 0.140 can have 128 senselines threaded through it. This number of senselineR is certainly adequate for a rope organizedon a one-core-per-word basis; it is not necessar-

From the collection of the Computer History Museum (www.computerhistory.org)


6/14

50 PROCEEDINGS-FALL JOINT COMPUTER CONFERENCE, 1963ily adequate for a rope organized on a one-coreper-output bit basis.Rope Memory haracteristics

A prototype rope can be seen in Figure Sa.Figure 5b shows a packaged unit. This ropeconsists of 256 cores, each of which stores four16-bit words. The storage elements used in.thisrope are 26 maxwell bobbin cores made of 1 8mil 4-79 Molybdenum Permalloy. The innerdiameter of the bobbins is 0.140 . If driven byramps having a slope of 400 malp sec, the output of the rope is of the order of 200 mv, withan absolute SIN of about 9:1. (See FigureDamped Operation.) The switching times ofthe cores are somewhat less than 2 p'sec; but

Figure 5a. Prototype Rope Memory Storing 256 Words,64 Bits per Word.

F .igure 5b. Rope Memor y Package Capacity:256 Words, 64 Bits per Word.

UNDAMPED OUTPUT

DAMPED OUTPUTTHE OUTPUTS SHOWN ARE FOR A 256CORE ROPE OF 64 BITS PER WORDBOBBIN CORE: E I D 231-002.SCALES: VERTICAL 100 MV/CM

HORIZONTAL 0.5 USEC CMFigure 6. Undamped and damped mode of operation.

since peaking occurs at 2 p sec after the startof the ramp, the cycle time is 8 p.sec. The valuesof resistance and inductance of various lines aretabulated in Table II.

TABLE IILine I Resistance InductanceSet 2 ohms 11 p.hInhibit 2 ohms 7 p.hSense 10 ohms 12 p.h

These data are suggestive of the performanceof a rope memory. Various factors pertainingto rope memory operation are discussed below.

Drive Currents It is possible to drive ropeswith either square pulses or ramps as mentioned above. Owing to the large inductanceof the selection and sense lines, a fast rise timepulse makes the L di/dt term large, which introduces 1) considerable back voltage, 2) aircoupling noise. While a ramp increases thecycie time of the memory, it 1 introduces rela-



7/14

THE ROPE MEMORY-A PERMANENT STORAGE DEVICE 51tively little back voltage, 2) decreases air cou-pling noise, 3 gives greater uniformity of coreoutputs.

The constraints placed on the various drivecurrents are relatively minor:

1 Each of the set, reset and inhibit pulsesmust exceed the switching threshold ofthe core.

2 The amplitude of the inhibit pulses mustbe greater than or equal to the amplitudeof the set pulse.

3 The set pulse may not start before or endafter the inhibit pulses, and must terminate before the reset line is enabled.

There is no requirement that the set and in-hibit pulses have the same shape: in fact, it ispossible and desirable to apply essentially DCon the inhibit lines; the set pulse may be eithera square wave or a ramp, as long as the otherconstraints are met. The desirability of DC onthe inhibit lines will be discussed below in thesection on noise cancellation. The reset pulseought to be a ramp for the reasons advancedabove. The relation of the core output to theramp pulse is shown in Figure 7

Since the selection scheme associated withrope memories is such that one and only onecore is not inhibited from switching during theselection phase and only that core is reset during the read phase, the core may be overdrivenin order to increase operating cycles. This willalso increase the core output. Clearly, powerconsumption is increased too.

No general statement can be made regardingthe amplitude requirements of the various

R S T PULS

v maxORE OUTPUT

10 OF Vmax

Figure 7 Relation between the core output and th3ramp used to generate it.

pulses. As is true in regular coincident currentor linear select memories, not all rope memoriesare made with the same type of core and themagnitude of the threshold switching field isclearly a function of the core used. One vitaltradeoff appears in choosing a core for a ropememory: the storage capacity, the requireddrive currents, and the output voltage are afunction of core size. The storage capacity andthe required drive currents are directly pro-portional to the inner diameter of the core;hence, the drive currents increase as the num-ber of bits to be stored increases. t thus be-comes axiomatic that for a given requiredcapacity the smallest core making the memorymanufacturable is to be selected as the storageelement.

Outputs and oise Cancellation The outputof a particular rope for given drive conditionswas given above. This magnitude output istypical for the given slope and memory capac-ity. The me mory capacity governs the outputinsofar as the length of the sense lines, andhence their attenuation, varies in direct pro-portion to the number of cores common to aset of sense lines.

Noise problems in rope memories can berather severe. Fortunately, there are two verysimple methods by which noise can be mini-mized to give SIN ratios of about 10:1. Be-fore discussing these schemes, the causes ofthe noise in the rope will be discussed.

In the first instance, noise is introduced inthe sense lines due to the air coupling betweenthe sense lines and the drive lines. This com-ponent is proportional to di/dt. Secondly,during reset time the 211-1) unselected coresare driven into saturation. This contributes anamount of noise which is proportional to211-1) d pk where Pk is the flux excursion

dtbetween the remanent and saturation points ofthe core. This noise can be many times theoutput of the selected core.

The air flux coupling can be reduced bydoubling back the sense line causing it to re-turn at its starting point. This doubling backminimizes the area in which coupling can occur.The noise flux can be cancelled by providingsense line cancellation and/or by leaving the



8/14


9/14

THE ROPE MEMORY-A PERMANENT STORAGE DEVICE 53role of the sense and inhibit lines. The senselines corresponding to bits used as the associative criteria are driven during the selection,phase of the cycle. The particular combinationof sense lines will cause all those cores storinginformation in accord with the search bits tobe switched. During read time the addressesof all cores so switched can be determined bylinking each core to a detector.ROPE MEMORY MANUFACTURE

Rope memory manufacture is unique in that1) no batch fabrication techniques are possibleat the moment, 2) with the exception of theset, reset, and inhibit lines, there is no regularwiring pattern, 3) the test of the final assemblymust establish that all cores are within specification at the end of the manufacturing processand that the information wired into the ropeis correct.

Up to the moment, we have used only discrete cores as storage elements in rope memories.In the near future. we hope to be able to produce storage elements on a batch basis, usingferrites in conjunction with thick magneticfilms

The main labor involved in the manufactureof a rope memory is in the wiring. This processhas been automated to the fullest extent possiblein order to reduce unit costs and to minimizethe chances for human error. Rope memoriesare manufactured in modules of 256 or 512cores. Initially, the set, reset, and inhibit linesare wired in. At this stage, the rope is testedto see that these lines were wired in correctly.This is done by driving each core in turn witha single turn winding and monitoring the output on the inhibit lines to determine whetheror not a given inhibit line threads the core.After the rope passes this test, it is obviousthat each core can be selected properly. Thenext step consists of wiring in the sense lines.For each sense line, there are as many thread,no-thread decisi'ons as there are cores in therope. All the thread, no-thread decisions for asense line for 256 cores are encoded on a 90-column card. This card is used not only to govern the wiring phase of the manufacturingprocess, but also to test the correctness of thewiring. After each sense line is inserted, eachcore is addressed in turn and its output moni-

Figure 8. Sense line tester.

tored across that sense line. The output iscompared to the information stored on the 90-column card. The sense line tester is shown inFigure 8. (The details of the manufacturingequipment and processes are the subject of apaper presently being prepared by the personnelresponsible for its design.)

At the completion of the memory assembly,the rope is tested again. This final test consistsof again testing each sense line as' describedabove and/or reading out each word (core) inturn and comparing the wired word outputagainst the desired word output, which is alsostored on a 90-column card. Each rope is alsotested to insure that the outputs of the wholeassembly of cores are consistent with one another; i.e., that the cores meet their specification. This latter test is the third test that thecores are subjected to: they are first tested ina raw state to determine if they meet specifications, and they are again tested after mounting on the assembly matrix prior to being wired.

Packaging techniques are primarily dependent on the connector type used. Generally, ropesshould be pluggable, which demands that a rugged connector be used. The choice of the connector is dependent on the size of the rope (256or 512 cores) and the maximum number ofsense lines. Our experience with packagingcores suggests that there are no difficulties inencapsulating a complete rope to protect itagainst environmental stresses.ROPE MEMORY SYSTEM

As mentioned above, a number of rope memory systems ha ve been built and placed intooperation. A rope presently being designed andconstructed is outlined in block diagram formin Figure 9. The purpose of this section is to



10/14

54 PROCEEDINGS-FALL JOINT COMPUTER CONFERENCE, 1963briefly outline the approach used in the designof this system. The description

of the rope memory systemunder construction is as follows:

STORAGE CAPACITY

ADDRESS INPUT

INFORMATION OUTPUTST ANDARD LEVELSCYCLE TIMEPOWER REQUIREMENTSMECHANICALVERIFIER

DDRESSINPUT

DDRESSREGISTER

256 words, expandable in modules of 256 words.Maximum number of bits per core: 64.Provision will be made for storing up to four words per core.Either serial or parallel. Only true address needs to be furnished.An eight-bit address input is required if one core stores one word.f cores store four words, a ten-bit address is required.

Either serial or parallel.oand -6 volts.8 p sec115 v AC 60 cycles. Actual power will depend on memory configuration.19 rack mount. Minimum height including power supply: 21 .Rope memory will be interchangeable.A built-in verifier will allow each word to be addressed manuallyso that word content can be verified. Provision will be made fortesting the memory under worst case drive conditions.

M MORY

nally. If four 16-bit words are to be stored percore, giving a total storage capacity of 1024words, the address must consist of ten bits: theeight low-order bits select the core, the remaining two bits are used to identify which ofthe four words stored by that core are to beread out.

Inspection of Figure 9 shows that no decoding circuits are necessary to select a core. Allthe information required for selection is contained in the address and its internally generated complement.

SENSE MPLIFIERS

Selection may be accomplished in one of threedifferent ways: 1) by having one driver associated with each of the direct and complementedaddress register bits and enabling those driverswhose corresponding bit position in the registeris a 1 ; 2) by using eight drivers and steering the current through the appropriate inhibitlines by means of switches controlled by theaddress register; 3) by using sixteen switchesand activating eight of these to switch theproper inhibit lines from a zero level to a DClevel able to generate the proper inhibit signal.The system under construction uses the lastmentioned scheme. In addition, a set and resetdriver are provided. The only restriction on theinhibit currents is that their amplitude begreater than that of the set pulse during thetime the set pulse is turned on; no restrictions

OUTPUTFigure 9. Rope memory system.

The eight-bit address of the core to be selectedis the input to the rope memory system, Thecomplement of the address is generated inter-



11/14

THE ROPE MEMORY-A PERMANENT STORAGE DEVICE 55

are placed on the inhibit current waveforms.A damped mode of operation is used.The output is fed into a flip-flop shift register.

If four words are stored per core, the selectedword will be gated to the output register byusing the information contained in the additional two bits of the address.

The block diagram of a memory system utilizing an electromagnetic coupling type permanent memory3 is shown in Figure 10. Theblock diagram has been simplified for comparison purposes. A system of this type is inherently faster than a rope memory system sinceit depends on a coupling response proportionalto di/dt and not on the switching time of amagnetic core. Since the output is dependenton di/dt, the rise time of the current pulsemust be carefully controlled; in the rope systemsuch careful control is not required as explainedabove. The input to that system is a nine-bitcode. Six bits are used to select one of 64 channels. The remaining three bits are used toselect one of eight words stored per channelthis corresponds to selecting one of four wordsstored per core in the rope memory system.There are 41 bits per word. The selection saccomplished by fragmenting the input asshown, and decoding each of the three segments

SENSELINESELE TOR

MEMORY

OUTPUT

Fi gure 10. Electromagnetic coupling type permanentmemory system.

in order to select the proper word. The addressmust be decoded as in any linear select scheme,a step not necessary in the rope memory system.

Due to the unique selection scheme employedby the rope memory and the fact that the tolerances on the inhibit drivers are very loose, together with the relative simplicity of the senseamplifiers due to the high output levels of thecore3, the component count in such a systemcan be reduced by from 3 < /


12/14

56 PROCEEDINGS-FALL JOINT COMPUTER CONFERENCE, 1963TABLE III

SUMMARY OF CHARACTERISTICSPermanent Changing Automatic Bits Per

Memory Data Mechanical Cycle Mag- Reset Storage AddressingType Feasible? Alignment Time Output netic Required Access ElementROPE NO Not 6-10 100- Yes Yes Random 64+ Nullapplicable p sec 200mv depending decoder

on coreCAPACI- YES Critical 200 1mv No No Random 1 Linear

TATIVE p sec SelectEM COU- YES Critical 1 50mv* No No Random 1 Linear

PLING SelectPM YES Critical 5 p sec 4mv Yes Yes Random 1 Linear

TWISTOR SelectThis valu3 is computed and d >es not take attenuation into account.

to replace information deleted in this manner.While the other schemes allow wholesale alteration of information, the ease with which thiscan be done must be somewhat tempered by themechanical alignment which is critical.ACKNOWLEDGEMENTS

The work done with rope memories whichforms much of the basis of this paper has depended on the cooperation of a number ofpeople. t is with pleasure that I acknowledgethe efforts of Messrs. W. Hennessey, A. Dorn,D. Pilsetnieks, and D. Clemson, all of the Electronic Instruments Division of the BurroughsCorporation. Messrs. Hennessey, Dorn andPilsetnieks are responsible for the design of therope memory manufacturing equipment andpackaging techniques. Mr. Clemson is largelyresponsible for the realization of the testsystem, the coordination of the manufacturingprocedure, and the work on the rope memorysystem described in the paper.BIBLIOGRAPHY

1. ALONSO, R., and LANING, J. H., DesignPrinciples for a General Control Computer , (R276 Instrumentation Laboratory, M.LT., April, 1960).

2. BARRET, et al., A Card-Changeable Permanent-Magnet Twistor Memory of Large

Capacity , IRE Trans. on EC EC-I0 451(1961).

3. ENDO, I., and YAMATO, J., The MetalCard Memory, A New SemipermanentStore , Large-Capacity Memory Techniques for Computing Systems . ACM Monograph Series, Yovits, Ed., The MacmillanCo., New York, 1962.

4. FOGLIA, et al., Card Capacitor-A Semipermanent, Read Only Memory. IBMJournal of Research and Development .567 (1961).

5. GIANOLA, et al., Large-Capacity CardChangeable Permanent Magnet TwistorMemory . Large-Capacity Memory Techniques for Computing Systems . ACM Monograph Series, Yovits, Ed., The MacmillanCo., New York, 1962.

6. GETLER, W., Space Role Seen for NewComputer , Missiles a.nd Rockets 12, 31(1963) .

7. KRYLOW, et aI., Semipermanent Memory:Latest Use for Twistors , Electronics 3680 (1963).

8 KUTTNER, P., Magnetic Permanent Storage: The Rope Memory . Presented tothe 1963 ACM National Conference.

9. KUTTNER, P., Thick Film Memory , Internal Burroughs Report, Al-267, October,1960.



13/14

THE ROPE MEMORY-A PERMANENT STORAGE DEVICE 5710. LOONEY D. H., A Twistor Matrix Memory

for Semipermanent Information , Proceedings, Western Joint Computer Conference, 1959.11. MACPHERSON D. H., and YORK R. K.,Semipermanent Storage by CapacitativeCoupling , IRE Trans. o EC EC-10 6(1961) .

12. MEYERHOFF ed., Digital Applications ofMagnetic Devices p. 417, if. John Wileyand Sons, New York, 1960.

13. MORGENSON E. 0. JR., Wired-CoreMatrix Memories , Instruments and Control Systems 3.5 75 (1962).

14. No Author Given, Miniaturized DataStorage System , Design News 17, 212(1962).

15. No Author Given, Core-Rope Memory ,Cornputer Design 2, 16 (1963).16. RAJCHMAN J., Static Magnetic MatrixMemory and Switching Circuits , RC Review 14, 183 (1952).17. RENARD A. M., and NEUMANN W. J.,

Unifluxor-A Permanent Memory Ele-

ment , Procedings, Western Joint Computer Conference, 1960.

18. RYAN R. D., A Permanent High SpeedStore for Use with Digital Computers ,IRE Trans. on EC EC-3 2 (1954).

19. SCHNEIDER et al., l\1ADDAM-The FirstCompletely Miniaturized Operating Computer , Proceedings, XII International Astronautical Congress, 1961.

20. TAKASHI and WATANABE CapacitanceType Fixed Memory , Large-CapacityM emory Techniques for Computing Systems ACM Monograph Series, Yovits, Ed.,The Macmillan Co., New York, 1962.

21. WALENDZIEWICZ E. T., The D210 Magnetic Computer , Paper presented to theSpaceborne Computer Engineering Conference, October, 1962.

22. WIER J. M., A High Speed PermanentStorage Device , IRE Trans. on EC EC-416 (1955).

23. Private discussion with R. Yn, ElectronicInstruments Division, Burroughs Corporation.



14/14

rope.memory

Documents