router architecture overview
TRANSCRIPT
-
8/2/2019 Router Architecture Overview
1/46
Shashank AgarwalInnovation and Incubation labs
NEC-HCL
-
8/2/2019 Router Architecture Overview
2/46
Introduction Routers functionality and generic architecture
Abstract Components of a RouterSwitch FabricsLine Cards
CPU Host IP Routers Architecture
Design Issues on different level of internet
Advances and Trends in Router Design
Open problems for Routers Design Conclusion
5/8/2012NEC-HCL 2
-
8/2/2019 Router Architecture Overview
3/46
Router is layer 3 Packet forwarder Links global internet
Transfer packets from input to output links
Router classification Backbone Router
Enterprise Router
Access Router
5/8/2012NEC-HCL 3
-
8/2/2019 Router Architecture Overview
4/46
5/8/2012NEC-HCL 4
-
8/2/2019 Router Architecture Overview
5/46
5/8/2012NEC-HCL 5
SwitchingFabric
Input Port
Input Port
Output Port
Output Port
RoutingProcessor
-
8/2/2019 Router Architecture Overview
6/46
Route processingpath computation
routing table maintenance
reach ability propagation achieved by control path)
packet forwarding IP packet validation
Destination IP Address Parsing and Table Lookup
Packet Lifetime Control
Checksum Calculation
5/8/2012NEC-HCL 6
-
8/2/2019 Router Architecture Overview
7/465/8/2012NEC-HCL 7
Lookup
IP Address
Update
Header
Header ProcessingData Hdr Data Hdr
1M prefixesOff-chip DRAM
AddressTable
IP Address Next Hop
Queue
Packet
BufferMemory
1M packetsOff-chip DRAM
-
8/2/2019 Router Architecture Overview
8/465/8/2012NEC-HCL 8
LookupIP Address
UpdateHeader
Header Processing
AddressTable
LookupIP Address
UpdateHeader
Header Processing
AddressTable
LookupIP Address
UpdateHeader
Header Processing
AddressTable
Data Hdr
Data Hdr
Data Hdr
BufferManager
BufferMemory
BufferManager
BufferMemory
BufferManager
BufferMemory
Data Hdr
Data Hdr
Data Hdr
InterconnectionFabric
-
8/2/2019 Router Architecture Overview
9/465/8/2012NEC-HCL 9
-
8/2/2019 Router Architecture Overview
10/46
Interfaces (Line Cards) Input/output of packets Buffering / Queuing QoS
Switching fabric Moving packets from input to output
Buses Crossbars Shared memories
CPU Host for running control plane Software(processing module)
Routing Packet processing Scheduling Etc.
5/8/2012NEC-HCL 10
Data Plane
Control Plane
-
8/2/2019 Router Architecture Overview
11/46
Control Path or Slow Path (consist of the CPU). Data Path or Fast Path (consist of the line card).
5/8/2012 11
Interfacecard
forwarding
Controller card
Routingcontrol
RoutingTable
RouterBackplane
a) Basic architecture
PacketForwarding
RoutingTable
Topology
&AddressExchangeNeighbor nodes
Incoming datapackets
outgoing datapackets
Neighbor nodes
b) Routing Components
-
8/2/2019 Router Architecture Overview
12/46
Time critical processing tasks forms the criticalpath.
Time critical tasks mainly consist of header
checking, forwarding(include segmentation), QoScontrol.
Most high-speed routers implement this fast path
in hardware.
5/8/2012NEC-HCL 12
-
8/2/2019 Router Architecture Overview
13/46
Packet by Packet Orientation Background Tasks
-Fragmentation and reassembly -Routing Protocols (RIP, OSPF, BGP,etc)
-Source routing option -Network management(SNMP)
-Route recording Option -Router configuration(BOOTP, DHCP,etc)
-Timestamp option
-ICMP message generation
5/8/2012 NEC-HCL13
Packets destined to a router, such as maintenance,management or error protocol data are usually not timecritical (ICMP,SNMP,TCP,UDP and routing protocol entitiesRIP, OSPF, BGP etc.)
-
8/2/2019 Router Architecture Overview
14/46
5/8/2012NEC-HCL 14
-
8/2/2019 Router Architecture Overview
15/46
(1)Shared Medium Switch Fabric: TDM Bus
In this each module is allocated a time slot in acontinuously repeating transmission.
limited in capacity and by the arbitration overhead forsharing this critical resource.
challenge is that it is almost impossible to build a bus
arbitration scheme fast enough to provide nonblockingperformance at multigigabit speeds.
5/8/2012NEC-HCL 15
-
8/2/2019 Router Architecture Overview
16/46
(2)Shared Memory Switch Fabric
5/8/2012NEC-HCL 16
Bottleneck- speed limited by memory access time and a Egress portShould work at the Total speed of all the ingress ports.
5/8/2012NEC-HCL 16
SharedMemory
Ingress
Port
IngressPort
Input Port
Input Port
Output Port
Output Port
SystemController
EgressPort
Egress
Port
Packets
Packets
Packets
Packets
-
8/2/2019 Router Architecture Overview
17/46
(3)Distributed Output Buffered Switch FabricIndependent paths exist between all N2 possible pairs of
inputs and outputs.
Unlike the shared medium approach, the address filters andbuffers need to operate only at the port speed.
5/8/2012NEC-HCL 17
AF AF AF AF AF AF
Ingress
Egress
Buffers
AddressFilters
Buses12..N
1 N
-
8/2/2019 Router Architecture Overview
18/46
(4) Space Division Switch Fabric : Crossbar switch
Every input port has a connection to every output port During each timeslot, each input connected to zero or one outputs
Advantage: Exploits parallelism Disadvantage: Need scheduling algorithm
5/8/2012 18
-
8/2/2019 Router Architecture Overview
19/46
5/8/2012NEC-HCL 19
Output 1
Output 2
Output 3
Input 1
Input 2
Input 3
Problem: The packet at the front of the queue experiences
contention for the output queue, blocking all packets behind it.
Maximum throughput in such a switch: 2 sqrt(2)
-
8/2/2019 Router Architecture Overview
20/46
Advantages
Easy to build 100% can be achieved with
limited speedup
Disadvantages Harder to design
algorithms Two congestion points
Flow control at destination
5/8/2012NEC-HCL 20
input interfaces output interfaces
Crossbar
-
8/2/2019 Router Architecture Overview
21/46
Maintain N virtual queues at each input one per output
5/8/2012NEC-HCL 21
Output 1
Output 2
Output 3
Input 1
Input 2
Input 3
-
8/2/2019 Router Architecture Overview
22/46
CPU Host for running control plane
5/8/2012NEC-HCL 22
-
8/2/2019 Router Architecture Overview
23/46
Functions Computes forwarding table
Implement Routing Protocol
Run software to configure and manage router
Handles packets whose destination address are notin the forwarding table
5/8/2012NEC-HCL 23
-
8/2/2019 Router Architecture Overview
24/46
GPP tends to be more expensive, but allow extensiveport functionality.
ASICs are not only cheaper, but can also provide
operations that are specific to routing.
It is argued that ASIC can reduce the complexity on eachsystem board by combining a number of functions intoindividual chips that are designed to perform at highspeeds.
5/8/2012NEC-HCL 24
-
8/2/2019 Router Architecture Overview
25/46
5/8/2012NEC-HCL 25
-
8/2/2019 Router Architecture Overview
26/46
5/8/2012 26
Bus-based Router architecture with singleProcessor
Use general purpose CPU multiple interface cards
interconnected through a shared bus.Route
Processor
(CPU)Memory
LineCard
LineCard
LineCard
DMADMADMA
MAC MAC MAC
Bus
-
8/2/2019 Router Architecture Overview
27/46
5/8/2012 27
RouteTable
CPU
LineCard
BufferMemory
LineCard
MAC
BufferMemory
LineCard
MAC
BufferMemory
FwdingCache
FwdingCache FwdingCache
MAC
BufferMemory
Typically
-
8/2/2019 Router Architecture Overview
28/46
5/8/2012 28
Architecture with Multiple Parallel Forwarding EnginesForwarding
Engine
ForwardingEngine
ForwardingEngine
NetworkInterface
ResourceControl
NetworkInterface
NetworkInterface
Control Bus
Data Bus
Forwarding EngineColumn Bus
Forwarding EngineRow Bus
-
8/2/2019 Router Architecture Overview
29/46
5/8/2012 29
IP router architectures(4)Crossbar: Switched Backplane with multiple processors
Typically
-
8/2/2019 Router Architecture Overview
30/46
5/8/2012 30
IP router architectures(5)Crossbar: Switched Backplane with fully distributed processors
Typically >50Gb/s aggregate capacity
Switch Fabric
NetworkInterface
NetworkInterface
NetworkInterface
Switch Fabric Interface
Media-Specific Interface
OutboundProcessing
LocalProcessingSubsystem
InboundProcessing
-
8/2/2019 Router Architecture Overview
31/46
5/8/2012NEC-HCL 31
-
8/2/2019 Router Architecture Overview
32/46
Backbone Router interconnects EnterpriseNetwork High link cost shared among large customer base.
Main challenge Maintaining high speed
Reliability
Techniques of achieving Reliability Dual power supplies
Hot spares
Duplicate data path through routers
5/8/2012NEC-HCL 32
-
8/2/2019 Router Architecture Overview
33/46
Major performance Bottleneck Route lookup in Forwarding Table
Routing Table may contain thousand of entries
Finding the longest matching prefix
Small packet increase cost of lookup
Large number of Destination increases cost
Output Qued Routers
Switch Fabric runs faster than sum speed of incoming links
Problems:
o
Limitation on speed of Routero Rate of accessing output buffers limited by SRAM or DRAM access
time.
5/8/2012NEC-HCL 33
-
8/2/2019 Router Architecture Overview
34/46
Input queued Routers Problems
Contention for switching fabric and output queue.
Difficult to design high speed arbiters that will fairly scheduleswitch fabric and output lines.
Stability and Reliability of Routing Protocol implementation
Routers running different protocols
5/8/2012NEC-HCL 34
-
8/2/2019 Router Architecture Overview
35/46
Enterprise/Campus Routers interconnect Endsystem
Main Objective Provide connectivity to large no. of end points as cheaply as
possible.
Provide different service qualities. Main challenges
Routers have low cost/ports Routers have large no. of ports Easy to configure
Support QoS Carry multicast traffic efficiently Support features like traffic filter, firewall and Vlan
5/8/2012NEC-HCL 35
-
8/2/2019 Router Architecture Overview
36/46
Access Routes link customers at home or in smallbusiness with an ISP
Main Objective Support heterogeneous high speed ports
Support variety of protocol at each port
5/8/2012NEC-HCL 36
-
8/2/2019 Router Architecture Overview
37/46
5/8/2012NEC-HCL 37
-
8/2/2019 Router Architecture Overview
38/46
5/8/2012NEC-HCL 38
High speed route lookup Speed of algorithm determined by
o Number of memory access
o Speed of memory
Techniques to improve performance of root lookupalgorithm
Hardware oriented techniques
o Based on CAMS and caches
Table compaction techniques
o Build compact data structure for the forwarding table andstore in cache
Hash based solution
o Use markers on the hash tables
-
8/2/2019 Router Architecture Overview
39/46
5/8/2012NEC-HCL 39
Advances in switching fabric ATM switch fabric core
o Allows router to support different QoS stream
o Once destination port is determined, IP packet is fragmentedinto ATM cells and switched
o ATM cells are reassembled at output ports beforetransmission
Enterprise level Mgmt and centralization
Single administrator controlling all routers in the
enterprise Centralize some router function
o Central route server computes loop free routes for entireenterprise and loads them on all routers forwarding table.
-
8/2/2019 Router Architecture Overview
40/46
5/8/2012NEC-HCL 40
Avoid Route Lookups Speeding up output queues
o Bottleneck of Output queue is access speed of Buffer
o Solutions
o Build very wide memories that can load entire cell in asingle cycle
Input Queued Switches
Problems
o HOL problem
o
Arbitrating access to switch fabric at high speedo Difficult to implement scheduling algorithm that
simultaneously schedules both fabric and output queues
Solutions
o VOQ
-
8/2/2019 Router Architecture Overview
41/46
5/8/2012NEC-HCL 41
Scheduling Fair Queuing
o Each packet source sharing a link is allocated a weight atbottleneck link
o Protects well-behaved sources from losing packets due to
misbehavior of other sources Reducing Port cost
Cost depend on
o Amount and kind of memory use: SRAMs vs. DRAMs
o Processing power: ASIC vs. General purpose processors
o Complexity of protocol used for communication betweenport and routing processor.
Soft Router
Optics Inside Router
-
8/2/2019 Router Architecture Overview
42/46
5/8/2012NEC-HCL 42
-
8/2/2019 Router Architecture Overview
43/46
Flow identification Need efficient and fast flow classifier
Ease of Configuration Configuring Router is hard Detecting Mistake in configuration file is difficult
Misconfigured routers causes performance problems
Software stability of large systems is difficult toachieve Interaction between bugs from different vendors can
lead to persistent network instability
5/8/2012NEC-HCL 43
-
8/2/2019 Router Architecture Overview
44/46
5/8/2012NEC-HCL 44
-
8/2/2019 Router Architecture Overview
45/46
While advances in router design have solved somedifficult routing problems, some important issuesremain unsolved
Trade off between cost , speed, flexibility, and ease of
configuration will still be challenge for a router design
Routers need enough processing power to forwardseveral million packets per second (Mpps).
The major design parameters are Amount and power of memory Processing Power Complexity of Protocol
45
-
8/2/2019 Router Architecture Overview
46/46