rr410505 jntu vlsi systems design

8/13/2019 Rr410505 jntu Vlsi Systems Design

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Code No: RR410505 Set No. 1

IV B.Tech I Semester Supplimentary Examinations, May/Jun 2009VLSI SYSTEMS DESIGN

( Common to Computer Science & Engineering, Computer Science &Systems Engineering and Electronics & Computer Engineering)

Time: 3 hours Max Marks: 80Answer any FIVE Questions

All Questions carry equal marks

1. Implement the following gates with p-MOS transistors only and explain its working

(a) 2 - Input AND gate.

(b) 4 - Input NOR gate. [8+8]

2. Name different IC fabrication technologies with suitable examples. [16]

3. Design a stick diagram for CMOS EX-NOR gate. [16]

4. Design a layout for CMOS inverter. [16]

5. Explain the delay calculation procedure for CMOS inverter. [16]

6. Draw the circuit diagram of Depletion-load NMOS SRAM cell and explain its

working principle. [16]

7. Explain clearly the global routing phase of the floor planning of the chip with fewexamples by considering all constraints. [16]

8. Write a register-transfer description of one four-digit timer. [16]

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1. Implement the following gates with CMOS Logic and explain its working

(a) 3 - Input NAND gate.

(b) Inverter. [8+8]

2. Explain clearly about each step of typical design abstraction ladder for digitalintegrated circuits. [16]

3. Design a stick diagram for CMOS logic shown below.Y = (AB + CD)1 [16]

4. Design a layout for CMOS 2-input NAND gate. [16]

5. Explain clearly any one of the testing procedure to Test sequential Systems. [16]

6. Draw the circuit diagram of four transistor DRAM cell with storage nodes andexplain its working. [16]

7. Clearly explain about block placement and channel definition with respect to floorplanning of the chip. [16]

8. Clearly explain about the generic integrated circuit design flow. [16]

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(a) 2 - Input NAND gate.


2. (a) Why CMOS technology is most suitable for VLSI ICs?

(b) Compare between CMOS and bipolar technologies. [6+10]

3. Explain details about level-1 modeling of MOS transistor. [16]

4. Design a layout for CMOS 3-input NOR gate. [16]

5. Give tests for struck-open fault for each transistor in a two-input static NOR gate.[16]

6. Draw the basic structure of serial-Parallel multiplier and explain its working prin-ciple. [16]

7. Explain about pad design procedure to design input and output pads. [16]

8. With suitable example explain any one of the partitioning algorithm [16]

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(a) 2 - Input AND gate.


2. Define different current parameters of Digital IC and explain their significance.[16]

3. Explain with neat sketches CMOS fabrication using P - well process. [16]

4. Design a layout for CMOS 3-input NOR gate. [16]

5. Explain how wire delay are calculated using El-more - delay model and RC Trees.[16]

6. Discuss clearly about the following system Design principles.

(a) Pipelining

(b) Data-paths. [8+8]

7. Clearly explain how ASM chart is a useful abstraction for register transfer design.[16]

8. With suitable example explain any one of the scheduling algorithm [16]

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rr410505 jntu vlsi systems design

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