rr410505-vlsi system sesign
TRANSCRIPT
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8/13/2019 Rr410505-Vlsi System Sesign
1/4
RR SET-1Code.No: RR410505
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
IV B.TECH I SEM SUPPLEMENTARY EXAMINATIONS, JUNE 2010
VLSI SYSTEM SESIGN
(COMMON TO CSE, CSS, ECC)Time: 3hours Max.Marks:80
Answer any FIVE questionsAll questions carry equal marks
- - -
1. Implement the following gates with n-MOS transistors only and explain itsworking:
a) 2 Input OR gate b) 4 Input NAND gate. [8+8]
2.a) Define Moores Law.
b) Why ICs are more reliable, accurate & faster than discrete devices? [8+8]
3. Design a stick diagram in CMOS logic for the function given below.
Y = {(A+B+C) D}
[16]
4. Design a layout for NMOS 3-input NOR gate. [16]
5.a) Compute the Zero delay signal probabilities for all signals for the network shown
in figure.
b) Find the combination of input transitions which introduces maximum of glitchingat the primary output 0 assuming that all gates have a delay of one unit time
shown in figure. [8+8]
6. Draw the Architecture of PLA and explain how different logic functions can be
implemented using PLA. [16]
7. Explain how Architecture driven voltage scaling technique reduces the power
consumption of the design. [16]
8. With suitable example explain clearly about Hardware/Software Co-simulation &
Co-synthesis. [16]
-oOo-
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8/13/2019 Rr410505-Vlsi System Sesign
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RR SET-2Code.No: RR410505
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
IV B.TECH I SEM SUPPLEMENTARY EXAMINATIONS, JUNE 2010
VLSI SYSTEM SESIGN
(COMMON TO CSE, CSS, ECC)Time: 3hours Max.Marks:80
Answer any FIVE questionsAll questions carry equal marks
- - -
1. Design a stick diagram in CMOS logic for the function given below.
Y = {(A+B+C) D}
[16]
2. Design a layout for NMOS 3-input NOR gate. [16]
3.a) Compute the Zero delay signal probabilities for all signals for the network shown
in figure.
b) Find the combination of input transitions which introduces maximum of glitching
at the primary output 0 assuming that all gates have a delay of one unit timeshown in figure. [8+8]
4. Draw the Architecture of PLA and explain how different logic functions can be
implemented using PLA. [16]
5. Explain how Architecture driven voltage scaling technique reduces the power
consumption of the design. [16]
6. With suitable example explain clearly about Hardware/Software Co-simulation &
Co-synthesis. [16]
7. Implement the following gates with n-MOS transistors only and explain itsworking:
a) 2 Input OR gate b) 4 Input NAND gate. [8+8]
8.a) Define Moores Law.
b) Why ICs are more reliable, accurate & faster than discrete devices? [8+8]
-oOo-
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8/13/2019 Rr410505-Vlsi System Sesign
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RR SET-3Code.No: RR410505
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
IV B.TECH I SEM SUPPLEMENTARY EXAMINATIONS, JUNE 2010
VLSI SYSTEM SESIGN
(COMMON TO CSE, CSS, ECC)Time: 3hours Max.Marks:80
Answer any FIVE questionsAll questions carry equal marks
- - -
1.a) Compute the Zero delay signal probabilities for all signals for the network shownin figure.
b) Find the combination of input transitions which introduces maximum of glitching
at the primary output 0 assuming that all gates have a delay of one unit time
shown in figure. [8+8]
2. Draw the Architecture of PLA and explain how different logic functions can beimplemented using PLA. [16]
3. Explain how Architecture driven voltage scaling technique reduces the powerconsumption of the design. [16]
4. With suitable example explain clearly about Hardware/Software Co-simulation &Co-synthesis. [16]
5. Implement the following gates with n-MOS transistors only and explain its
working:
a) 2 Input OR gate b) 4 Input NAND gate. [8+8]
6.a) Define Moores Law.
b) Why ICs are more reliable, accurate & faster than discrete devices? [8+8]
7. Design a stick diagram in CMOS logic for the function given below.
Y = {(A+B+C) D}
[16]
8. Design a layout for NMOS 3-input NOR gate. [16]
-oOo-
-
8/13/2019 Rr410505-Vlsi System Sesign
4/4
RR SET-4Code.No: RR410505
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
IV B.TECH I SEM SUPPLEMENTARY EXAMINATIONS, JUNE 2010
VLSI SYSTEM SESIGN
(COMMON TO CSE, CSS, ECC)Time: 3hours Max.Marks:80
Answer any FIVE questionsAll questions carry equal marks
- - -
1. Explain how Architecture driven voltage scaling technique reduces the powerconsumption of the design. [16]
2. With suitable example explain clearly about Hardware/Software Co-simulation &Co-synthesis. [16]
3. Implement the following gates with n-MOS transistors only and explain its
working:
a) 2 Input OR gate b) 4 Input NAND gate. [8+8]
4.a) Define Moores Law.b) Why ICs are more reliable, accurate & faster than discrete devices? [8+8]
5. Design a stick diagram in CMOS logic for the function given below.
Y = {(A+B+C) D}
[16]
6. Design a layout for NMOS 3-input NOR gate. [16]
7.a) Compute the Zero delay signal probabilities for all signals for the network shown
in figure.
b) Find the combination of input transitions which introduces maximum of glitching
at the primary output 0 assuming that all gates have a delay of one unit timeshown in figure. [8+8]
8. Draw the Architecture of PLA and explain how different logic functions can be
implemented using PLA. [16]
-oOo-