SUB -NYQUIST SAMPLING DSP & SUPPORT CHANGE DETECTOR

MIDTERM PRESENTATION

Performed by:Omer Kiselov Daniel Primor

Winter 2010

:Supervised by Moshe Mishali Inna Rivkin

High speed digital systems laboratoryTechnion - Israel institute of technologydepartment of Electrical Engineering

OUTLINE

Algorithms in the systems Testing methods Functional Architecture Entity Definition Full System Architecture Resources Estimation Goals for future Work environment Gantt Chart

THE WHOLE SYSTEM AND MAIN OBJECTIVE

High speed digital systems laboratoryTechnion - Israel institute of technologydepartment of Electrical Engineering

To implement in hardware (on FPGA) a DSP to reconstruct the digital signal of the samples given by the expand

To implement a Support Change Detector which identify the spectral support changes.

The DSP & Support Change Detector Project Goals

High speed digital systems laboratoryTechnion - Israel institute of technologydepartment of Electrical Engineering

The DSP Computation Algorithm

High speed digital systems laboratoryTechnion - Israel institute of technologydepartment of Electrical Engineering

QR Decompositio

nAs matrix R matrix

InverseInv(R)*transpose(

Q)Pseudo Inverse Of As Matrix

Multiply Pinv(A)*Sample

s Y

Y Analog Samples

Digital Samples

MATHEMATICAL ALGORITHM

† 1

m n m m m n

m n T m m

A Q R

A R Q

1 1 1 1 1

1 1 1 1

1 1 1 1

1 1

1

0

0 0

0 0 00 0 0 0 0 0 0

0 0 0 00 0 0 0 0 0 0 0

0 0 0 0 00 0 0 0 0 0 0 0 0

0 0 0 0 00 0 0 0 0 0 0 0 0 0

0 0 0 0 00 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0

0 0 0 0 0

0 0 0 0 0

0 0 0 0 0

r r r r r

r r r r

r r r

r rr r r r r

rr r r r

R I R R r r r

r r

r

0

0 0

0 0 0

0 0 0 0

0 0 0 0 0

0 0 0 0 0

0 0 0 0 0

0 0 0 0 0

0 0 0 0 0

0 0 0 0 0

0 0 0 0 0

r r r r r

r r r r

r r r

r r

r

0

0 0

0 0 0

0 0 0 0

new

r r r r r

r r r r

R r r r

r r

r

0

0 0

0 0 0

0 0 0 0

0 0 0 0 0

0 0 0 0 0

0 0 0 0 0

0 0 0 0 0

0 0 0 0 0

0 0 0 0 0

0 0 0 0 0

r r r r r

r r r r

r r r

r r

r

R

1

1 1 1 1 1

1 1 1 1

1 1 1

1 1

1

0

0 0

0 0 0

0 0 0 0

invnew new

r r r r r

r r r r

R R r r r

r r

r

1 1 1 1 1

1 1 1 1

1 1 1 1

1 1

1

0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0

invnew

r r r r r

r r r r

R R r r r

r r

r

High speed digital systems laboratoryTechnion - Israel institute of technologydepartment of Electrical Engineering

Adding an extra support to the matrix As. After Pseudo inverse the “Control Vector” is

multiplied by 12 samples The results are summed up If the Energy level is high we get a support

change. The support change signal is up to ‘1’ for a single

clock cycle.

The Support Change Detector Algorithm

High speed digital systems laboratoryTechnion - Israel institute of technologydepartment of Electrical Engineering

SIMULATIONS

Floating point simulations The algorithm in basic hardware implementation

possible functions Fixed point simulations

Word length : 18 bit, 12 for fraction The algorithm with sliced R matrix

High speed digital systems laboratoryTechnion - Israel institute of technologydepartment of Electrical Engineering

MAIN ENTITY INTERFACE DSP & SCD

High speed digital systems laboratoryTechnion - Israel institute of technologydepartment of Electrical Engineering

HDL

Memory interface

Expander interface

CTF interface

High speed digital systems laboratoryTechnion - Israel institute of technologydepartment of Electrical Engineering

HDL

INTEFACE BEHAVIOR The Expander Sends The signals serially and valid

while they are TRUE. The CTF sends a Valid bit and one clock cycle

later send the support serially one by one after which the valid drops. It first sends the support amount one clock after valid simultaneously with the first support organ.

The memory in the ordinary memory access. There are 3 clocks with hopefully 12 times the

main clock in speed and 4 times the main clock in speed. Any faster clock will be appreciated.

MAIN BLOCK DIAGRAM

High speed digital systems laboratoryTechnion - Israel institute of technologydepartment of Electrical Engineering

HDL

DSP BLOCK DIAGRAM

High speed digital systems laboratoryTechnion - Israel institute of technologydepartment of Electrical Engineering

Inputs

HDL

DSP BLOCK DIAGRAM

High speed digital systems laboratoryTechnion - Israel institute of technologydepartment of Electrical Engineering

HDL

DSP BLOCK DIAGRAM

High speed digital systems laboratoryTechnion - Israel institute of technologydepartment of Electrical Engineering

HDL

DSP BLOCK DIAGRAM

High speed digital systems laboratoryTechnion - Israel institute of technologydepartment of Electrical Engineering

HDL

DSP BLOCK DIAGRAM

High speed digital systems laboratoryTechnion - Israel institute of technologydepartment of Electrical Engineering

HDL

SUPPORT CHANGE DETECTOR BLOCK DIAGRAM

High speed digital systems laboratoryTechnion - Israel institute of technologydepartment of Electrical Engineering

HDL

RESOURCES ESTIMATION• Multipliers:

• QR Decomposition needs one divide unit and one square root unit• Other units don’t require arithmetic units• Memory Estimation

The calculation matrixes (4) are saved in serial on chip FIFOs, with wordlength of 24X18bit=432bit, depth of 32 words

The Pseudo Inverse matrixes (current and last)are saved in on chip RAM, 2X24X24X18bit=20,736bit

The support is saved serially in on chip FIFO 12X7 bits The support number is saved in the controller. The samples are saved in on chip FIFO, including bit from SCD that shows if

there is a change in the support, 227bit wordlength and depth of 64 words In QR Decomposition: 4X18bit=72bit for Beta (number for calculation),

2X24X18bit=864bit for vectors, 2X24X24X18bit=20,736bit for temporary matrixesIn matrix multiplier: 2X24X24X18bit=20,736bit for temporary matrixes.

In samples multiplier: 2X24X18bit=864bit for samples

Samples Multiplier

Matrix Multiplier Matrix Inverse QR Decomposition

48 ,uses Two Sum of Four mode

24 ,uses Two Sum of Four mode

20 51

PROJECT PART A GOALS Until the end of the first part of the project:

To finish the implementation of the DSP & Support Change Detector in VHDL.

The system must pass a full simulation in ModelSim and perform (in flying colors! )

To reach the minimal acceptable mark of energy for the support change detector via simulation in Matlab. (Tradeoff – false alarm to miss detection)

High speed digital systems laboratoryTechnion - Israel institute of technologydepartment of Electrical Engineering

BOUNDARIES IN IMPLEMENTATION

We are to implement the device for the stratix III FPGA which has limited resources.

High speed digital systems laboratoryTechnion - Israel institute of technologydepartment of Electrical Engineering

Device

Multipliers

9x9 12x12 18x18 36x3618X18

Complex18X18 Sum

of Mults

EP3SE110 896 672 448 224 224 896

Stratix III breakdown

Memory resources 1040X9k 48X144k

6750X0.64k

SIMULATION AND DESIGN TOOLS

High speed digital systems laboratoryTechnion - Israel institute of technologydepartment of Electrical Engineering

Gantt ChartHigh speed digital systems laboratoryTechnion - Israel institute of technology

department of Electrical Engineering

defining the main entity

charactirizing the systems blocks

detailed block diagram for hardware implementation

Detailed design

Learning HDL designer

Entities Definition

Learning devlopment tools

implementing the QR decomposition in VHDL

preparing the midterm presentation

implementing and simulating the matrix inverse unit

implementing and simulating the other system blocks in VHDL

crating a matlab simulation of the support change detector

implementing the support change detector in VHDL

Exam period

debugging

simulation in modelsim

end of part A

01/10/2009 20/11/2009 09/01/2010 28/02/2010

*already done *in process

*not approached yet

High speed digital systems laboratoryTechnion - Israel institute of technologydepartment of Electrical Engineering

Questions?

Thank you very

much!