saa7128h; saa7129h digital video encoder sheets/nxp pdfs/saa7128h,7129h.pdf1. general description...

1. General description

The SAA7128H; SAA7129H encodes digital CR-Y-CB video data to an NTSC, PAL orSECAM CVBS or S-video signal. Simultaneously, RGB or bypassed but interpolatedCR-Y-CB signals are available via three additional DACs. The circuit at a 54 MHzmultiplexed digital D1 input port accepts two ITU-R BT.656 compatible CR-Y-CB datastreams with 720 active pixels per line in 4 : 2 : 2 multiplexed formats, for example MPEGdecoded data with overlay and MPEG decoded data without overlay, where one datastream is latched at the rising clock edge and the other at the falling clock edge.

It includes a sync/clock generator and on-chip DACs.

2. Features

Monolithic CMOS 3.3 V device, 5 V I2C-bus optional

Digital PAL/NTSC/SECAM encoder

System pixel frequency 13.5 MHz

54 MHz double-speed multiplexed D1 interface capable of splitting data into twoseparate channels (encoded and baseband)

Three Digital-to-Analog Converters (DACs) for CVBS (CSYNC), VBS (CVBS) and C(CVBS) two times oversampled with 10-bit resolution (signals in brackets optional)

Three DACs for RED (CR), GREEN (Y) and BLUE (CB) two times oversampled with9-bit resolution (signals in brackets optional)

An advanced composite sync is available on the CVBS output for RGB displaycentering

Real-time control of subcarrier

Cross-color reduction filter

Closed captioning encoding and World Standard Teletext (WST) and North-AmericanBroadcast Text System (NABTS) teletext encoding including sequencer and filter

Copy Generation Management System (CGMS) encoding (CGMS described bystandard CPR-1204 of EIAJ); 20 bits in lines 20/283 (NTSC) can be loaded via I2C-bus

Fast I2C-bus control port (400 kHz)

Line 23 Wide Screen Signalling (WSS) encoding

Video Programming System (VPS) data encoding in line 16 (50/625 lines counting)

Encoder can be master or slave

Programmable horizontal and vertical input synchronization phase

Programmable horizontal sync output phase

Internal Color Bar Generator (CBG)

SAA7128H; SAA7129HDigital video encoderRev. 03 — 9 December 2004 Product data sheet

Philips Semiconductors SAA7128H; SAA7129HDigital video encoder

Macrovision® Pay-per-View copy protection system rev. 7.01 and rev. 6.1 optional; thisapplies to SAA7128H only. The device is protected by US patents 4631603, 4577216and 4819098 and other intellectual property rights; use of the Macrovision anti-copyprocess in the device is licensed for non-commercial home use only. Reverseengineering or disassembly is prohibited; please contact your nearest PhilipsSemiconductors sales office for more information.

Controlled rise/fall times of output syncs and blanking

On-chip crystal oscillator (3rd-harmonic or fundamental crystal)

Down mode (low output voltage) or power-save mode of DACs

QFP44 package

3. Quick reference data

[1] At maximum supply voltage with highly active input signals.

4. Ordering information

Table 1: Quick reference dataVDDD = 3.0 V to 3.6 V; Tamb = 0 °C to 70 °C; unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

VDDA analog supply voltage 3.15 3.3 3.45 V

VDDD digital supply voltage 3.0 3.3 3.6 V

IDDA analog supply current [1] - 130 150 mA

IDDD digital supply current VDDD = 3.3 V [1] - 75 100 mA

Vi input signal voltage levels TTL compatible

Vo(p-p) analog output signal voltages Y,C and CVBS without load(peak-to-peak value)

1.25 1.35 1.50 V

RL load resistance 75 - 300 Ω

LElf(i) low frequency integral linearityerror

- - ±3 LSB

LElf(d) low frequency differential linearityerror

- - ±1 LSB

Tamb ambient temperature 0 - 70 °C

Table 2: Ordering information

Typenumber

Package

Name Description Version

SAA7128H QFP44 plastic quad flat package; 44 leads (lead length 1.3 mm);body 10 × 10 × 1.75 mm

SOT307-2

SAA7129H

9397 750 14325 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.

Product data sheet Rev. 03 — 9 December 2004 2 of 55

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9397 750 14325

Product data shee

Philips S

emiconduc

5.B

lock diagram41

SCL VDDA4

42

SDA

40 36

VDDA3

31

VDDA2

28

VDDA1

2535

XTALI

34

XTALO

7

RCV1

8

RCV2

43

TTXRQ

37

XCLK

4

LLC1RESET_N

t

I2C-BUSINTERFACE

SYNC/CLOCK21SA

20VDD(I2C)

SAA7128H

torsS

AA

7128H; S

AA

7129HD

igital video encoder

mhb572

A

CVBS(CSYNC)

30

VBS(CVBS)

27

C(CVBS)

24

VSSA122

VSSA232

VSSA333

A

RED23

GREEN26

BLUE29

© K

oninklijke Philips E

lectronics N.V. 2004. A

ll rights reserved.

Rev. 03 —

9 Decem

ber 20043 of 55

Fig 1. Block diagram

I2C-bus control

9 to 16MP7 to MP0

44TTX

DY

C

clock and timing I2C-bus control

19

RTCI

OUTPUTINTERFACEENCODER

Y

FADER

I2C-buscontrol

3

AP

2

SP

39

VDDD3

17

VDDD2

6

VDDD1

38

VSSD3

18

VSSD2

5

VSSD1

MPA

MPB

MPpos

MPneg

MP

VP

SWITCH

I2C-bus control

I2C-bus controlI2C-bus control

DY

CB-CR

CB-CR

RGBPROCESSOR

I2C-bus control

SAA7129H


6. Pinning information

6.1 Pinning

6.2 Pin description

Fig 2. Pin configuration

SAA7128HSAA7129H

RES VSSA3

SP VSSA2

AP VDDA3

LLC1 CVBS

VSSD1 BLUE

VDDD1 VDDA2

RCV1 VBS

RCV2 GREEN

MP7 VDDA1

MP6 C

MP5 RED

MP

4T

TX

MP

3T

TX

RQ

MP

2S

DA

MP

1S

CL

MP

0R

ES

ET

_N

VD

DD

2V

DD

D3

VS

SD

2V

SS

D3

RT

CI

XC

LK

VD

D(I

2C)

VD

DA

4

SA

XT

ALI

VS

SA

1X

TA

LO

001aac194

1

2

3

4

5

6

7

8

9

10

11

33

32

31

30

29

28

27

26

25

24

23

12 13 14 15 16 17 18 19 20 21 22

44 43 42 41 40 39 38 37 36 35 34

Table 3: Pinning

Symbol Pin Type Description

RES 1 - reserved pin; do not connect

SP 2 I test pin; connected to digital ground for normal operation

AP 3 I test pin; connected to digital ground for normal operation

LLC1 4 I line-locked clock input; this is the 27 MHz master clock

VSSD1 5 supply digital ground 1

VDDD1 6 supply digital supply voltage 1

RCV1 7 I/O raster control 1 for video port; this pin receives/provides a VS/FS/FSEQ signal

RCV2 8 I/O raster control 2 for video port; this pin provides an HS pulse of programmable length orreceives an HS pulse




MP7 9 I double-speed 54 MHz MPEG port; it is an input for ITU-R BT.656 style multiplexedCR-Y-CB data; data is sampled on the rising and falling clock edge; data sampled on therising edge is then sent to the encoding part of the device; data sampled on the fallingedge is sent to the RGB part of the device (or vice versa, depending on programming)

MP6 10 I

MP5 11 I

MP4 12 I

MP3 13 I

MP2 14 I

MP1 15 I

MP0 16 I



RTCI 19 I real-time control input; if the LLC1 clock is provided by an SAA7113 or SAA7118, RTCIshould be connected to the RTCO pin of the respective decoder to improve the signalquality

VDD(I2C) 20 supply sense input for I2C-bus voltage; connect to I2C-bus supply

SA 21 I select I2C-bus address; LOW selects slave address 88h, HIGH selects slave address8Ch

VSSA1 22 supply analog ground 1 for RED (CR), C (CVBS) and GREEN (Y) outputs

RED 23 O analog output of RED (CR) signal

C 24 O analog output of chrominance (CVBS) signal

VDDA1 25 supply analog supply voltage 1 for RED (CR) and C (CVBS) outputs

GREEN 26 O analog output of GREEN (Y) signal

VBS 27 O analog output of VBS (CVBS) signal

VDDA2 28 supply analog supply voltage 2 for VBS (CVBS) and GREEN (Y) outputs

BLUE 29 O analog output of BLUE (CB) signal

CVBS 30 O analog output of CVBS (CSYNC) signal

VDDA3 31 supply analog supply voltage 3 for BLUE (CB) and CVBS (CSYNC) outputs

VSSA2 32 supply analog ground 2 for VBS (CVBS), BLUE (CB) and CVBS (CSYNC) outputs

VSSA3 33 supply analog ground 3 for the DAC reference ladder and the oscillator

XTALO 34 O crystal oscillator output

XTALI 35 I crystal oscillator input; if the oscillator is not used, this pin should be connected toground

VDDA4 36 supply analog supply voltage 4 for the DAC reference ladder and the oscillator

XCLK 37 O clock output of the crystal oscillator



RESET_N 40 I Reset input, active LOW. After reset is applied, all digital I/Os are in input mode; PALblack burst on CVBS, VBS and C; RGB outputs set to lowest voltage. The I2C-busreceiver waits for the START condition.

SCL 41 I/(O) serial clock input (I2C-bus) with inactive output path

SDA 42 I/O serial data input/output (I2C-bus)

TTXRQ 43 O teletext request output, indicating when text bits are requested

TTX 44 I teletext bit stream input

Table 3: Pinning …continued

Symbol Pin Type Description




7. Functional description

The digital video encoder encodes digital luminance and color difference signals intoanalog CVBS, S-video and simultaneously RGB or CR-Y-CB signals. NTSC-M, PAL-B/G,SECAM and sub-standards are supported.

Both interlaced and non-interlaced operation is possible for all standards.

The basic encoder function consists of subcarrier generation and color modulation andinsertion of synchronization signals. Luminance and chrominance signals are filtered inaccordance with the standard requirements of RS170A and ITU-R BT.470-3.

For ease of post analog filtering the signals are twice oversampled with respect to thepixel clock before digital-to-analog conversion.

The total filter transfer characteristics are illustrated in Figure 8 to Figure 13. The DACs forY, C and CVBS are realized with full 10-bit resolution; 9-bit resolution for RGB output. TheCR-Y-CB to RGB dematrix can be bypassed optionally in order to provide the upsampledCR-Y-CB input signals.

The 8-bit multiplexed CR-Y-CB formats are ITU-R BT.656 (D1 format) compatible, but theSAV and EAV codes can be decoded optionally when the device is operated in slavemode. Two independent data streams can be processed, one latched by the rising edge ofLLC1, the other latched by the falling edge of LLC1. The purpose of that is e.g. to forwardone of the data streams containing both video and On-Screen Display (OSD) informationto the RGB outputs, and the other stream containing video only to the encoded outputsCVBS and S-video.

For optimum display of RGB signals through a euro-connector TV set, an early compositesync pulse (up to 31 LLC1 clock periods) can be provided at the CVBS output.

As a further alternative, the VBS and C outputs may provide a second and third CVBSsignal.

It is also possible to connect a Philips digital video decoder (SAA7111A, SAA7113 orSAA7118) to the SAA7128H; SAA7129H. Via the RTCI pin, connected to RTCO of adecoder, information concerning actual subcarrier, PAL-ID and definite subcarrier phasecan be inserted.

The device synthesizes all necessary internal signals, color subcarrier frequency andsynchronization signals from that clock.

Wide screen signalling data can be loaded via the I2C-bus and is inserted into line 23 forstandards using 50 Hz field rate.

VPS data for program dependent automatic start and stop of such featured VCRs isloadable via I2C-bus.

The IC also contains closed caption and extended data services encoding (line 21), andsupports anti-taping signal generation in accordance with Macrovision. It is also possibleto load data for copy generation management system into line 20 of every field (525/60line counting).

A number of possibilities are provided for setting different video parameters, such as:




• Black and blanking level control

• Color subcarrier frequency

• Variable burst amplitude, etc.

During reset (RESET_N = LOW) and after reset is released, all digital I/O stages are setto input mode and the encoder is set to PAL mode and outputs a ‘black burst’ signal onCVBS and S-video outputs, while RGB outputs are set to their lowest output voltages.A reset forces the I2C-bus interface to abort any running bus transfer.

7.1 Versatile faderImportant note: whenever the fader is activated with the SYMP bit set to a logic 1(enabling the detection of embedded Start of Active Video (SAV) and End of Active Video(EAV)), codes 00h and FFh are not allowed within the actual video data (as prescribed byITU-R BT.656). If SAV (00h) has been detected, the fader automatically passes 100% ofthe respective signal until SAV is detected.

Within the digital video encoder, two data streams can be faded against each other; thesedata streams can be input to the double speed MPEG port, which is able to separate twoindependent 27 MHz data streams MPA and MPB via a cross switch controlled by EDGE1and EDGE2.

7.1.1 Configuration examples

Figure 4 to Figure 7 show examples on how to configure the fader between the input portsand the outputs, separated into the composite (and S-video) encoder and the RGBencoder.

7.1.1.1 Configuration 1

Input MPA can be faded into MPB. The resulting output of the fader is then encodedsimultaneously to composite (and S-video) and RGB output (RGBIN = ENCIN = 1). In thisexample, either MPA or MPB could be an overlay (menu) signal to be faded smoothly inand out.

Fig 3. Cross switch

mhb574

MPA

MPB

MPpos

MPneg

EDGE1 = 0

EDGE1 = 1

EDGE2 = 1

EDGE2 = 0





Input MPA can be faded into MPB. The resulting output of the fader is then encoded toRGB output, while the signal coming from MPB is fed directly to composite (and S-video)output (RGBIN = 1, ENCIN = 0). Also in this example, either MPA or MPB could be anoverlay (menu) signal to be faded smoothly in and out, whereas the overlay appears onlyin the RGB output connected to the TV set.


Input MPB is passed directly to the RGB output, assuming e.g. it contains video includingoverlay. MPA is equivalently passed through the inactive fader to the composite (andS-video) output, assuming e.g. it contains video excluding overlay (RGBIN = 0,ENCIN = 1).

Fig 4. Configuration 1

mhb575

ENCODERPATH

RGB PATH

FADER

OUTPUT

MPA

MPB

MP

e.g.videorecorder

e.g. TVVP


mhb576

ENCODERPATH

RGB PATH

FADER

OUTPUT

MPA

MPB

MP

e.g. TVVP

e.g.videorecorder


mhb577

ENCODERPATH

RGB PATH

FADER BYPASSMPA

MPB e.g. TV

e.g.videorecorder





Only MPB input is in use; its signal is both composite (and S-video) and RGB encoded(RGBIN = ENCIN = 0).

7.1.2 Parameters of the fader

Basically, there are three independent fade factors available, allowing for the equation:

Output = (FADEx × In1) + [(1 − FADEx) × In2]

Where x = 1, 2 or 3.

Factor FADE1 is effective, when a color in the data stream fed to the MPEG port faderinput is recognized as being between KEY1L and KEY1U. That means, the color is notidentified by a single numeric value, but an upper and lower threshold in a 24-bit YUVcolor space can be defined. FADE1 = 00h results in 100 % signal at the MPEG port faderinput and 0 % signal at the fader video port input. Variation of 63 steps is possible up toFADE1 = 3Fh, resulting in 0 % signal at the MPEG port fader input and 100 % signal atthe fader video port input.

Factor FADE2 is effective, when a color in the data stream fed to the MPEG port faderinput is recognized as being between KEY2L and KEY2U. FADE2 is to be seen inconjunction with a color that is defined by a 24-bit internal Color Look-Up Table (CLUT).FADE2 = 00h results in 100 % of the internally defined LUT color and 0 % signal at thefader video port input. Variation of 63 steps is possible up to FADE2 = 3Fh, resulting in0 % of the internally defined LUT color and 100 % signal at the fader video port input.

Finally, factor FADE3 is effective, when a color in the data stream fed to the MPEG portfader input is recognized as neither being between KEY1L and KEY1U nor being betweenKEY2L and KEY2H. FADE3 = 00h results in 100 % signal at the MPEG port fader inputand 0 % signal at the fader video port input. Variation of 63 steps is possible up toFADE3 = 3Fh, resulting in 0 % signal at the MPEG port fader input and 100 % signal atthe fader video port input.

Optionally, all upper and lower thresholds can be ignored, enabling to fade signals onlyagainst the LUT color.

If bit CFADM is set HIGH, all data at the MPEG port fader are faded against the LUT color,if bit CFADV is set HIGH, all data at the video port fader are faded against the LUT color.


mhb578

ENCODERPATH

RGB PATH

MPA

MPB

e.g. video recorder

e.g. TV




7.2 Data managerIn the data manager, a pre-defined color look-up table located in this block can be readout in a pre-defined sequence (8 steps per active video line) as an alternative to theexternal video data, achieving a color bar test pattern generator without the need for anexternal data source.

7.3 Encoder

7.3.1 Video path

The encoder generates out of Y, U and V baseband signals luminance and colorsubcarrier output signals, suitable for use as CVBS or separate Yand C signals.

Luminance is modified in gain and in offset (latter programmable in a certain range toenable different black level set-ups). A blanking level can be set after insertion of a fixedsynchronization pulse tip level in accordance with standard composite synchronizationschemes. Other manipulations used for the Macrovision anti-taping process such asadditional insertion of AGC super-white pulses (programmable in height) are supported bythe SAA7128H only.

In order to enable easy post analog filtering, luminance is interpolated from a 13.5 MHzdata rate to a 27 MHz data rate, providing luminance in 10-bit resolution. The transfercharacteristics of the luminance interpolation filter are illustrated inFigure 10 and Figure 11. Appropriate transients at start/end of active video and forsynchronization pulses are ensured.

Chrominance is modified in gain (programmable separately for U and V), standarddependent burst is inserted, before baseband color signals are interpolated from a6.75 MHz data rate to a 27 MHz data rate. One of the interpolation stages can bebypassed, thus providing a higher color bandwidth, which can be made use of for Yand Coutput. The transfer characteristics of the chrominance interpolation filter are illustrated inFigure 8 and Figure 9.

The amplitude, beginning and ending of the inserted burst, is programmable in a certainrange that is suitable for standard signals and for special effects. Behind the succeedingquadrature modulator, color in a 10-bit resolution is provided on the subcarrier.

The numeric ratio between Yand C outputs is in accordance with the respectivestandards.

7.3.2 Teletext insertion and encoding

Pin TTX receives a WST or NABTS teletext bitstream sampled at the LLC clock. Twoprotocols are provided:

• At each rising edge of output signal (TTXRQ) a single teletext bit has to be providedafter a programmable delay at input pin TTX

• The signal TTXRQ performs only a single LOW-to-HIGH transition and remains atHIGH-level for 360, 296 or 288 teletext bits, depending on the chosen standard.

Phase variant interpolation is achieved on this bitstream in the internal teletext encoder,providing sufficient small phase jitter on the output text lines.




TTXRQ provides a fully programmable request signal to the teletext source, indicating theinsertion period of bitstream at lines which are selectable independently for both fields.The internal insertion window for text is set to 360 (PAL-WST), 296 (NTSC-WST) or 288(NABTS) teletext bits including clock run-in bits. The protocol and timing are illustrated inFigure 23.

7.3.3 Video Programming System (VPS) encoding

Five bytes of VPS information can be loaded via the I2C-bus and will be encoded in theappropriate format into line 16.

7.3.4 Closed caption encoder

Using this circuit, data in accordance with the specification of closed caption or extendeddata service, delivered by the control interface, can be encoded (line 21). Two dedicatedpairs of bytes (two bytes per field), each pair preceded by run-in clocks and framing code,are possible.

The actual line number where data is to be encoded in, can be modified in a certain range.

The data clock frequency is in accordance with the definition for NTSC-M standard32 times horizontal line frequency.

Data LOW at the output of the DACs corresponds to 0 IRE, data HIGH at the output of theDACs corresponds to approximately 50 IRE.

It is also possible to encode closed caption data for 50 Hz field frequencies at 32 timeshorizontal line frequency.

7.3.5 Anti-taping (SAA7128H only)

For more information contact your nearest Philips Semiconductors sales office.

7.4 RGB processorThis block contains a dematrix in order to produce red, green and blue signals to be fed toa SCART plug.

Before Y, CB and CR signals are de-matrixed, individual gain adjustment for Y and colordifference signals and 2 times oversampling for luminance and 4 times oversampling forcolor difference signals is performed. The transfer curves of luminance and colordifference components of RGB are illustrated in Figure 12 and Figure 13 respectively.

7.5 SECAM processorSECAM specific pre-processing is achieved by a pre-emphasis of color difference signals(for gain and phase see Figure 14 and Figure 15 respectively).

A baseband frequency modulator with a reference frequency shifted from 4.286 MHz toDC carries out SECAM modulation in accordance with appropriate standard or optionalwide clipping limits.

After HF pre-emphasis, line-by-line sequential carriers with black reference of 4.25 MHz(Db) and 4.40625 MHz (Dr) are generated on a DC reference carrier (anti-Cloche filter;see Figure 16 and Figure 17) using specified values for FSC programming bytes.




Alternating phase reset in accordance with SECAM standard is carried out automatically.During vertical blanking, the so-called ‘bottle pulses’ are not provided.

7.6 Output interface/DACsIn the output interface, encoded Yand C signals are converted from digital-to-analog in a10-bit resolution. Yand C signals are also combined in a 10-bit CVBS signal.

The CVBS output occurs with the same processing delay (equal to 82 LLC clock periods,measured from MP input to the analog outputs) as the Y, C and RGB outputs. Absoluteamplitude at the input of the DAC for CVBS is reduced by 15⁄16 with respect to Yand CDACs to make maximum use of conversion ranges.

Red, green and blue signals are also converted from digital-to-analog, each providing a9-bit resolution.

Outputs of the DACs can be set together via software control to minimum output voltage(approximately 0.2 V DC) for either purpose. Alternatively, the buffers can be switched into3-state output condition; this allows for a ‘wired AND’ configuration with other 3-stateoutputs and can also be used as a power-save mode.

7.7 SynchronizationThe synchronization of the SAA7128H; SAA7129H is able to operate in two modes; slavemode and master mode.

In master mode, see Figure 19, the circuit generates all necessary timings in the videosignal itself, and it can provide timing signals at the RCV1 and RCV2 ports. In slave mode,it accepts timing information either from the RCV pins or from the embedded timing dataof the ITU-R BT.656 data stream.

For the SAA7128H; SAA7129H, the only difference between master and slave mode isthat it ignores the timing information at its inputs in master mode. Thus, if in slave mode,any timing information is missing, the IC will continue running free without a visible effect.But there must not be any additional pulses (with wrong phase) because the circuit will notignore them.

In slave mode, see Figure 18, an interface circuit decides which signal is expected at theRCV1 port and which information is taken from its active slope. The polarity can bechosen. If PRCV1 is logic 0, the rising slope will be active.

The signal can be:

• A Vertical Sync (VS) pulse; the active slope sets the vertical phase

• An odd/even signal; the active slope sets the vertical phase, the internal field flag toodd and optionally sets the horizontal phase

• A Field Sequence (FSEQ) signal; it marks the first field of the 4 (NTSC) or 8 (PAL) or12 (SECAM) field sequences; in addition to the odd/even signal, it also sets the PALphase and optionally defines the subcarrier phase.

On the RCV2 port, the IC can provide a horizontal pulse with programmable start and stopphase; this pulse can be inhibited in the vertical blanking period to build up, for example, acomposite blanking signal.




The horizontal phase can be set via a separate input RCV2. In the event of VS pulses atRCV1, this is mandatory. It is also possible to set the signal path to blank via this input.

From the ITU-R BT.656 data stream, the SAA7128H; SAA7129H decodes only the start ofthe first line in the odd field. All other information is ignored and may miss. If this kind ofslave mode is active, the RCV pins may be switched to output mode.

In slave mode, the horizontal trigger phase can be programmed to any point in the line,the vertical phase from line 0 to line 15 counted from the first serration pulse in half linesteps.

Whenever synchronization information cannot be derived directly from the inputs, theSAA7128H; SAA7129H will calculate it from the internal horizontal, vertical and PALphase. This gives good flexibility with respect to external synchronization, but the circuitdoes not suppress illegal settings. In such an event, the odd/even information may vanishas it does in the non-interlaced modes.

In master mode, the line lengths are fixed to 1728 clocks at 50 Hz and 1716 clocks at60 Hz. To allow non-interlaced frames, the field lengths can be varied by ±0.5 lines. In theevent of non-interlace, the SAA7128H; SAA7129H does not provide odd/even informationand the output signal does not contain the PAL ‘Bruch sequence’.

At the RCV1 pin the IC can provide:

• A Vertical Sync (VS) signal with 2.5 (50 Hz) or 3 (60 Hz) lines duration

• An odd/even signal which is LOW in odd fields

• A Field Sequence (FSEQ) signal which is HIGH in the first field of the 4 or 8 or 12 fieldsequences.

At the RCV2 pin, there is a horizontal pulse of programmable phase and durationavailable. This pulse can be suppressed in the programmable inactive part of a field,giving a composite blank signal.

The directions and polarities of the RCV ports can be chosen independently. Timingreferences can be found in Table 55 and Table 63.

7.8 ClockThe input to LLC1 can either be an external clock source or the buffered on-chip clockXCLK. The internal crystal oscillator can be run with either a 3rd-harmonic or afundamental crystal frequency.

7.9 I2C-bus interfaceThe I2C-bus interface is a standard slave transceiver, supporting 7-bit slave addressesand 400 kbit/s guaranteed transfer rate. It uses 8-bit subaddressing with anauto-increment function. All registers are write and readable, except one read only statusbyte.

The I2C-bus slave address is defined as 88h with pin 21 (SA) tied LOW and as 8Ch withpin 21 (SA) tied HIGH.




7.10 Input levels and formatsThe SAA7128H; SAA7129H expects digital Y, CB and CR data with levels (digital codes) inaccordance with ITU-R BT.601.

For C and CVBS outputs, deviating amplitudes of the color difference signals can becompensated by an independent gain control setting, while gain for luminance is set topredefined values, distinguishable for 7.5 IRE set-up or without set-up.

The RGB, respectively CR-Y-CB path features a gain setting individually for luminance(GY) and color difference signals (GCD).

Reference levels are measured with a color bar, 100 % white, 100 % amplitude and100 % saturation.

[1] Transformation:

R = Y + 1.3707 × (CR − 128)

G = Y − 0.3365 × (CB − 128) − 0.6982 × (CR − 128)

B = Y + 1.7324 × (CB − 128).

[2] Representation of R, G and B (or CR, Yand CB) at the output is 9 bits at 27 MHz.

Table 4: ITU-R BT.601 signal component levels

Color Signals [1]

Y CB CR R [2] G [2] B [2]

White 235 128 128 235 235 235

Yellow 210 16 146 235 235 16

Cyan 170 166 16 16 235 235

Green 145 54 34 16 235 16

Magenta 106 202 222 235 16 235

Red 81 90 240 235 16 16

Blue 41 240 110 16 16 235

Black 16 128 128 16 16 16

Table 5: 8-bit multiplexed format (similar to ITU-R BT.601 )

Time Bits

0 1 2 3 4 5 6 7

Sample CB0 Y0 CR0 Y1 CB2 Y2 CR2 Y3

Luminance pixel number 0 1 2 3

Color pixel number 0 2



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9397 750 14325

Product data shee

Philips S

emiconductors

SA

A7128H

; SA

A7129H

Digital video encoder

7.11 Bit allocation map

Table 6: Slave receiver (slave address 88h)

Register function Subaddress Data byte [1]

D7 D6 D5 D4 D3 D2 D1 D0

0 FSEQ O_E

0 0 0

WSS2 WSS1 WSS0

WSS10 WSS9 WSS8

BS2 BS1 BS0

BE2 BE1 BE0

CG02 CG01 CG00

CG10 CG09 CG08

CG18 CG17 CG16

RTRI GTRI BTRI

0 0 0

GY2 GY1 GY0

GCD2 GCD1 GCD0

CSYNC MP2C VP2C

KEY1LU2 KEY1LU1 KEY1LU0

KEY1LV2 KEY1LV1 KEY1LV0

KEY1LY2 KEY1LY1 KEY1LY0

KEY2LU2 KEY2LU1 KEY2LU0

KEY2LV2 KEY2LV1 KEY2LV0

KEY2LY2 KEY2LY1 KEY2LY0

KEY1UU2 KEY1UU1 KEY1UU0

KEY1UV2 KEY1UV1 KEY1UV0

KEY1UY2 KEY1UY1 KEY1UY0

KEY2UU2 KEY2UU1 KEY2UU0

KEY2UV2 KEY2UV1 KEY2UV0

KEY2UY2 KEY2UY1 KEY2UY0

FADE12 FADE11 FADE10

FADE22 FADE21 FADE20

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Status byte (read only) 00h VER2 VER1 VER0 CCRDO CCRDE

Null 01h to 25h 0 0 0 0 0

Wide screen signal 26h WSS7 WSS6 WSS5 WSS4 WSS3

Wide screen signal 27h WSSON 0 WSS13 WSS12 WSS11

Real-time control, burst start 28h DECCOL DECFIS BS5 BS4 BS3

Burst end 29h 0 0 BE5 BE4 BE3

Copy generation 0 2Ah CG07 CG06 CG05 CG04 CG03

Copy generation 1 2Bh CG15 CG14 CG13 CG12 CG11

CG enable, copy generation 2 2Ch CGEN 0 0 0 CG19

Output port control 2Dh CVBSEN1 CVBSEN0 CVBSTRI YTRI CTRI

Null 2Eh to 37h 0 0 0 0 0

Gain luminance for RGB 38h 0 0 0 GY4 GY3

Gain color difference for RGB 39h 0 0 0 GCD4 GCD3

Input port control 1 3Ah CBENB 0 0 SYMP DEMOFF

Key color 1 lower limit U 42h KEY1LU7 KEY1LU6 KEY1LU5 KEY1LU4 KEY1LU3

Key color 1 lower limit V 43h KEY1LV7 KEY1LV6 KEY1LV5 KEY1LV4 KEY1LV3

Key color 1 lower limit Y 44h KEY1LY7 KEY1LY6 KEY1LY5 KEY1LY4 KEY1LY3

Key color 2 lower limit U 45h KEY2LU7 KEY2LU6 KEY2LU5 KEY2LU4 KEY2LU3

Key color 2 lower limit V 46h KEY2LV7 KEY2LV6 KEY2LV5 KEY2LV4 KEY2LV3

Key color 2 lower limit Y 47h KEY2LY7 KEY2LY6 KEY2LY5 KEY2LY4 KEY2LY3

Key color 1 upper limit U 48h KEY1UU7 KEY1UU6 KEY1UU5 KEY1UU4 KEY1UU3

Key color 1 upper limit V 49h KEY1UV7 KEY1UV6 KEY1UV5 KEY1UV4 KEY1UV3

Key color 1 upper limit Y 4Ah KEY1UY7 KEY1UY6 KEY1UY5 KEY1UY4 KEY1UY3

Key color 2 upper limit U 4Bh KEY2UU7 KEY2UU6 KEY2UU5 KEY2UU4 KEY2UU3

Key color 2 upper limit V 4Ch KEY2UV7 KEY2UV6 KEY2UV5 KEY2UV4 KEY2UV3

Key color 2 upper limit Y 4Dh KEY2UY7 KEY2UY6 KEY2UY5 KEY2UY4 KEY2UY3

Fade factor key color 1 4Eh 0 0 FADE15 FADE14 FADE13

CFade, Fade factor key color 2 4Fh CFADEM CFADEV FADE25 FADE24 FADE23


9397 750 14325

Product data shee

Philips S

emiconductors

SA

A7128H

; SA

A7129H


Fade factor other 50h 0 0 FADE35 FADE34 FADE33 FADE32 FADE31 FADE30

LUTU2 LUTU1 LUTU0

LUTV2 LUTV1 LUTV0

LUTY2 LUTY1 LUTY0

VPSEL EDGE2 EDGE1

VPS52 VPS51 VPS50

VPS112 VPS111 VPS110




CHPS2 CHPS1 CHPS0

GAINU2 GAINU1 GAINU0

GAINV2 GAINV1 GAINV0

BLCKL2 BLCKL1 BLCKL0

BLNNL2 BLNNL1 BLNNL0

BLNVB2 BLNVB1 BLNVB0

0 0 0

SCBW PAL FISE

BSTA2 BSTA1 BSTA0

FSC02 FSC01 FSC00

FSC10 FSC09 FSC08

FSC18 FSC17 FSC16

FSC26 FSC25 FSC24

L21O02 L21O01 L21O00

L21O12 L21O11 L21O10

L21E02 L21E01 L21E00

L21E12 L21E11 L21E10

CBLF ORCV2 PRCV2

Table 6: Slave receiver (slave address 88h) …continued


D7 D6 D5 D4 D3 D2 D1 D0

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Look-up table key color 2 U 51h LUTU7 LUTU6 LUTU5 LUTU4 LUTU3

Look-up table key color 2 V 52h LUTV7 LUTV6 LUTV5 LUTV4 LUTV3

Look-up table key color 2 Y 53h LUTY7 LUTY6 LUTY5 LUTY4 LUTY3

VPS enable, input control 2 54h VPSEN 0 ENCIN RGBIN DELIN

VPS byte 5 55h VPS57 VPS56 VPS55 VPS54 VPS53





Chrominance phase 5Ah CHPS7 CHPS6 CHPS5 CHPS4 CHPS3

Gain U 5Bh GAINU7 GAINU6 GAINU5 GAINU4 GAINU3

Gain V 5Ch GAINV7 GAINV6 GAINV5 GAINV4 GAINV3

Gain U MSB, real-time control,black level

5Dh GAINU8 DECOE BLCKL5 BLCKL4 BLCKL3

Gain V MSB, real-time control,blanking level

5Eh GAINV8 DECPH BLNNL5 BLNNL4 BLNNL3

CCR, blanking level VBI 5Fh CCRS1 CCRS0 BLNVB5 BLNVB4 BLNVB3

Null 60h 0 0 0 0 0

Standard control 61h DOWNB DOWNA INPI YGS SECAM

RTC enable, burst amplitude 62h RTCE BSTA6 BSTA5 BSTA4 BSTA3

Subcarrier 0 63h FSC07 FSC06 FSC05 FSC04 FSC03




Line 21 odd 0 67h L21O07 L21O06 L21O05 L21O04 L21O03

Line 21 odd 1 68h L21O17 L21O16 L21O15 L21O14 L21O13

Line 21 even 0 69h L21E07 L21E06 L21E05 L21E04 L21E03

Line 21 even 1 6Ah L21E17 L21E16 L21E15 L21E14 L21E13

RCV port control 6Bh SRCV11 SRCV10 TRCV2 ORCV1 PRCV1


9397 750 14325

Product data shee

Philips S

emiconductors

SA

A7128H

; SA

A7129H


Trigger control 6Ch HTRIG7 HTRIG6 HTRIG5 HTRIG4 HTRIG3 HTRIG2 HTRIG1 HTRIG0

VTRIG2 VTRIG1 VTRIG0

LDEL0 FLC1 FLC0

SCCLN2 SCCLN1 SCCLN0

RCV2S2 RCV2S1 RCV2S0

RCV2E2 RCV2E1 RCV2E0

RCV2S10 RCV2S9 RCV2S8

TTXHS2 TTXHS1 TTXHS0

TTXHD2 TTXHD1 TTXHD0

VS_S2 VS_S1 VS_S0

TTXOVS2 TTXOVS1 TTXOVS0

TTXOVE2 TTXOVE1 TTXOVE0

TTXEVS2 TTXEVS1 TTXEVS0

TTXEVE2 TTXEVE1 TTXEVE0

FAL2 FAL1 FAL0

LAL2 LAL1 LAL0

TTXOVE8 TTXEVS8 TTXOVS8

0 0 0

LINE7 LINE6 LINE5

LINE15 LINE14 LINE13

Table 6: Slave receiver (slave address 88h) …continued


D7 D6 D5 D4 D3 D2 D1 D0

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[1] All bits labelled ‘0’ are reserved. They must be programmed with logic 0.

Trigger control 6Dh HTRIG10 HTRIG9 HTRIG8 VTRIG4 VTRIG3

Multi control 6Eh SBLBN BLCKON PHRES1 PHRES0 LDEL1

Closed caption, teletext enable 6Fh CCEN1 CCEN0 TTXEN SCCLN4 SCCLN3

RCV2 output start 70h RCV2S7 RCV2S6 RCV2S5 RCV2S4 RCV2S3

RCV2 output end 71h RCV2E7 RCV2E6 RCV2E5 RCV2E4 RCV2E3

MSBs RCV2 output 72h 0 RCV2E10 RCV2E9 RCV2E8 0

TTX request H start 73h TTXHS7 TTXHS6 TTXHS5 TTXHS4 TTXHS3

TTX request H delay 74h TTXHD7 TTXHD6 TTXHD5 TTXHD4 TTXHD3

CSYNC advance, Vsync shift 75h CSYNCA4 CSYNCA3 CSYNCA2 CSYNCA1 CSYNCA0

TTX odd request vertical start 76h TTXOVS7 TTXOVS6 TTXOVS5 TTXOVS4 TTXOVS3

TTX odd request vertical end 77h TTXOVE7 TTXOVE6 TTXOVE5 TTXOVE4 TTXOVE3

TTX even request vertical start 78h TTXEVS7 TTXEVS6 TTXEVS5 TTXEVS4 TTXEVS3

TTX even request vertical end 79h TTXEVE7 TTXEVE6 TTXEVE5 TTXEVE4 TTXEVE3

First active line 7Ah FAL7 FAL6 FAL5 FAL4 FAL3

Last active line 7Bh LAL7 LAL6 LAL5 LAL4 LAL3

TTX mode, MSB vertical 7Ch TTX60 LAL8 TTXO FAL8 TTXEVE8

Null 7Dh 0 0 0 0 0

Disable TTX line 7Eh LINE12 LINE11 LINE10 LINE9 LINE8

Disable TTX line 7Fh LINE20 LINE19 LINE18 LINE17 LINE16


7.12 I2C-bus format

[1] X is the read/write control bit; X = logic 0 is order to write; X = logic 1 is order to read.

[2] If more than 1 byte DATA is transmitted, then auto-increment of the subaddress is performed.

7.13 Slave receiver

Table 7: I 2C-bus address; see Table 8

S SLAVE ADDRESS ACK SUBADDRESS ACK DATA 0 ACK -------- DATA n ACK P

Table 8: Explanation of Table 7

Part Description

S START condition

SLAVE ADDRESS 1000 100X or 1000 110X [1]

ACK acknowledge, generated by the slave

SUBADDRESS [2] subaddress byte

DATA data byte

-------- continued data bytes and ACKs

P STOP condition

Table 9: Subaddress 26h

Bit Symbol Description

7 WSS7 wide screen signalling bits: enhanced services field

6 WSS6

5 WSS5

4 WSS4

3 WSS3 wide screen signalling bits: aspect ratio field

2 WSS2

1 WSS1

0 WSS0



7 WSSON 0 = Wide screen signalling output is disabled; default state after reset,

1 = Wide screen signalling output is enabled.

6 - this bit is reserved and must be set to logic 0

5 WSS13 wide screen signalling bits: reserved field

4 WSS12

3 WSS11

2 WSS10 wide screen signalling bits: subtitles field

1 WSS9

0 WSS8






7 DECCOL 0 = disable color detection bit of RTCI input,

1 = enable color detection bit of RTCI input; bit RTCE must be set tologic 1, see Figure 22

6 DECFIS 0 = field sequence as FISE in subaddress 61,

1 = field sequence as FISE bit in RTCI input; bit RTCE must be set tologic 1, see Figure 22

5 BS5 starting point of burst in clock cycles:

PAL: BS[5:0] = 33 (21h); default value after reset

NTSC: BS[5:0] = 25 (19h).4 BS4

3 BS3

2 BS2

1 BS1

0 BS0



7 - these 2 bits are reserved; each must be set to logic 0

6 -

5 BE5 ending point of burst in clock cycles:

PAL: BE[5:0] = 29 (1Dh); default value after reset

NTSC: BE[5:0] = 29 (1Dh).

4 BE4

3 BE3

2 BE2

1 BE1

0 BE0

Table 13: Subaddress 2Ah


7 to 0 CG[07:00] LSB of the byte is encoded immediately after run-in, the MSB of the bytehas to carry the CRCC bit, in accordance with the definition of copygeneration management system encoding format

Table 14: Subaddress 2Bh


7 to 0 CG[15:08] second byte; the MSB of the byte has to carry the CRCC bit, inaccordance with the definition of copy generation management systemencoding format

Table 15: Subaddress 2Ch


7 CGEN 0 = copy generation data output is disabled; default state after reset,

1 = copy generation data output is enabled.

6 - these 3 bits are reserved; each must be set to logic 0

5 -

4 -




3 CG19 remaining bits of copy generation code

2 CG18

1 CG17

0 CG16

Table 16: Subaddress 2Dh


7 CVBSEN1 0 = luminance output signal is switched to Y DAC; default state afterreset,

1 = CVBS output signal is switched to Y DAC.

6 CVBSEN0 0 = chrominance output signal is switched to C DAC; default state afterreset,

1 = CVBS output signal is switched to C DAC.

5 CVBSTRI 0 = DAC for CVBS output in 3-state mode (high-impedance),

1 = DAC for CVBS output in normal operation mode; default state afterreset.

4 YTRI 0 = DAC for Y output in 3-state mode (high-impedance),

1 = DAC for Y output in normal operation mode; default state after reset.

3 CTRI 0 = DAC for C output in 3-state mode (high-impedance),

1 = DAC for C output in normal operation mode; default state after reset.

2 RTRI 0 = DAC for RED output in 3-state mode (high-impedance),

1 = DAC for RED output in normal operation mode; default state afterreset.

1 GTRI 0 = DAC for GREEN output in 3-state mode (high-impedance),

1 = DAC for GREEN output in normal operation mode; default state afterreset.

0 BTRI 0 = DAC for BLUE output in 3-state mode (high-impedance),

1 = DAC for BLUE output in normal operation mode; default state afterreset.



7 to 5 - these 3 bits are reserved; each must be set to logic 0

4 to 0 GY[4:0] gain luminance of RGB (CR, Y and CB) output, ranging from(1 − 16⁄32) to (1 + 15⁄32); suggested nominal value = −6 (11010b),depending on external application




4 to 0 GCD[4:0] gain color difference of RGB (CR, Y and CB) output, ranging from(1 − 16⁄32) to (1 + 15⁄32); suggested nominal value = −6 (11010b),depending on external application

Table 15: Subaddress 2Ch …continued







7 CBENB 0 = data from input ports is encoded; default state after reset,

1 = color bar with fixed colors is encoded.

6 - these 2 bits are reserved; each must be set to a logic 0

5 -

4 SYMP 0 = horizontal and vertical trigger is taken from RCV2 and RCV1,respectively; default state after reset,

1 = horizontal and vertical trigger is decoded out of ITU-R BT.656compatible data at MPEG port.

3 DEMOFF 0 = YCBCR-to-RGB dematrix is active; default state after reset,

1 = YCBCR-to-RGB dematrix is bypassed.

2 CSYNC 0 = CVBS output signal is switched to CVBS DAC; default state afterreset,

1 = advanced composite sync is switched to CVBS DAC.

1 MP2C 0 = input data is twos complement from MPEG port fader input,

1 = input data is straight binary from MPEG port fader input; default stateafter reset.

0 VP2C 0 = input data is twos complement from video port fader input,

1 = input data is straight binary from video port fader input; default stateafter reset.

Table 20: Subaddresses 42h to 44h and 48h to 4Ah

Address Byte Description

42h, 48h KEY1LU[7:0]KEY1UU[7:0]

Key color 1 lower and upper limits for U, V and Y; if MPEG input signal iswithin the limits of key color 1 the incoming signals at the video port andMPEG port are added together according to the equation:

FADE1 × video signal + (1 − FADE1) × MPEG signal

Default value of all bytes after reset = 80h.

43h, 49h KEY1LV[7:0]KEY1UV[7:0]

44h, 4Ah KEY1LY[7:0]KEY1UY[7:0]

Table 21: Subaddresses 45h to 47h and 4Bh to 4Dh


45h, 4Bh KEY2LU[7:0]KEY2UU[7:0]

Key color 2 lower and upper limits for U, V and Y; if MPEG input signal iswithin the limits of key color 2 the incoming signals at the video port andMPEG port are added together according to the equation:

FADE2 × video signal + (1 − FADE2) × LUT values

Default value of all bytes after reset = 80h.

46h, 4Ch KEY2LV[7:0]KEY2UV[7:0]

47h, 4Dh KEY2LY[7:0]KEY2UY[7:0]




Table 22: Subaddress 4Eh



5 to 0 FADE1[5:0] these 6 bits form factor FADE1 which determines the ratio between theMPEG and video input signal in the resulting video data stream if the keycolor 1 is detected in the MPEG input signal:

FADE1 = 00h: 100 % MPEG, 0 % video

FADE1 = 3Fh: 100 % video, 0 % MPEG; default value after reset.

Table 23: Subaddress 4Fh


7 CFADEM 0 = fader operates in normal mode; default state after reset,

1 = the entire video input stream is faded with the color stored in the LUT(subaddresses 51h to 53h) regardless of the MPEG input signal; thecolor keys are disabled.

6 CFADEV 0 = fader operates in normal mode; default state after reset,

1 = the entire MPEG input stream is faded with the color stored in theLUT (subaddresses 51h to 53h) regardless of the video input signal; thecolor keys are disabled.

5 to 0 FADE2[5:0] these 6 bits form factor FADE2 which determines the ratio between theLUT color values (subaddresses 51h to 53h) and the video input signal inthe resulting video data stream if the key color 2 is detected in the MPEGinput signal:

FADE2 = 00h: 100 % LUT color, 0 % video

FADE2 = 3Fh: 100 % video, 0 % LUT color; default value after reset.



7 to 6 - these 2 bits are reserved; each must be a logic 0

5 to 0 FADE3[5:0] these 6 bits form factor FADE3 which determines the ratio between theMPEG and video input signal in the resulting video data stream if neitherthe key color 1 nor the key color 2 is detected in the MPEG input signal:

FADE3 = 00h: 100 % MPEG, 0 % video

FADE3 = 3Fh: 100 % video, 0 % MPEG; default value after reset.



7 to 0 LUTU[7:0] LUT for the color values inserted in case of key color 2 U detection in theMPEG input data stream; LUTU[7:0] = 80h; default value after reset



7 to 0 LUTV[7:0] LUT for the color values inserted in case of key color 2 V detection in theMPEG input data stream; LUTV[7:0] = 80h; default value after reset






7 to 0 LUTY[7:0] LUT for the color values inserted in case of key color 2 Y detection in theMPEG input data stream; LUTY[7:0] = 80h; default value after reset



7 VPSEN 0 = video programming system data insertion is disabled; default stateafter reset,

1 = video programming system data insertion in line 16 is enabled.

6 - this bit is not used and should be set to logic 0

5 ENCIN 0 = encoder path is fed with MPB input data; fader is bypassed; defaultstate after reset,

1 = encoder path is fed with output signal of fader; see Section 7.1.

4 RGBIN 0 = RGB path is fed with MPB input data; fader is bypassed; default stateafter reset,

1 = RGB path is fed with output signal of fader; see Section 7.1.

3 DELIN 0 = not supported in current version; do not use,

1 = recommended value; default state after reset.

2 VPSEL 0 = not supported in current version; do not use,

1 = recommended value; default state after reset.

1 EDGE2 0 = MPB data is sampled on the rising clock edge; default state afterreset,

1 = MPB data is sampled on the falling clock edge.

0 EDGE1 0 = MPA data is sampled on the rising clock edge; default state afterreset,

1 = MPA data is sampled on the falling clock edge.



7 to 0 VPS5[7:0] fifth byte of video programming system data in line 16; LSB first



7 to 0 VPS11[7:0] eleventh byte of video programming system data in line 16; LSB first



7 to 0 VPS12[7:0] twelfth byte of video programming system data in line 16; LSB first



7 to 0 VPS13[7:0] thirteenth byte of video programming system data in line 16; LSB first




[1] All IRE values are rounded up.



7 to 0 VPS14[7:0] fourteenth byte of video programming system data in line 16; LSB first



7 to 0 CHPS[7:0] phase of encoded color subcarrier (including burst) relative to horizontalsync; can be adjusted in steps of 360/256 degrees:

0Fh = PAL-B/G and data from input ports

3Ah = PAL-B/G and data from look-up table

35h = NTSC-M and data from input ports

57h = NTSC-M and data from look-up table.



7 to 0 GAINU[7:0] these are the 8 LSBs of the 9-bit code that selects the variable gain forthe CB signal; input representation in accordance with ITU-R BT.601;see Table 36; the MSB is held in subaddress 5Dh; see Table 39

Table 36: GAINU values

Conditions [1] Encoding

White-to-black = 92.5 IRE GAINU = −2.17 × nominal to +2.16 × nominal

GAINU[8:0] = 0 output subcarrier of U contribution = 0

GAINU[8:0] = 118 (76h) output subcarrier of U contribution = nominal

White-to-black = 100 IRE GAINU = −2.05 × nominal to +2.04 × nominal

GAINU[8:0] = 0 output subcarrier of U contribution = 0

GAINU[8:0] = 125 (7Dh) output subcarrier of U contribution = nominal

GAINU[8:0] = 106 (6Ah) nominal GAINU for SECAM encoding



7 to 0 GAINV[7:0] these are the 8 LSBs of the 9-bit code that selects the variable gain forthe CR signal; input representation in accordance with ITU-R BT.601;see Table 38; the MSB is held in subaddress 5Eh; see Table 41

Table 38: GAINV values


White-to-black = 92.5 IRE GAINV = −1.55 × nominal to +1.55 × nominal

GAINV[8:0] = 0 output subcarrier of V contribution = 0

GAINV[8:0] = 165 (A5h) output subcarrier of V contribution = nominal

White-to-black = 100 IRE GAINV = −1.46 × nominal to +1.46 × nominal

GAINV[8:0] = 0 output subcarrier of V contribution = 0

GAINV[8:0] = 175 (AFh) output subcarrier of V contribution = nominal






[2] Output black level/IRE = BLCKL × 2/6.29 + 28.9.

[3] Output black level/IRE = BLCKL × 2/6.18 + 26.5.

GAINV[8:0] = 129 (81h) nominal GAINV for SECAM encoding



7 GAINU8 MSB of the 9-bit code that sets the variable gain for the CB signal;see Table 35.

6 DECOE real-time control:

0 = disable odd/even field control bit from RTCI

1 = enable odd/even field control bit from RTCI; see Figure 22.

5 to 0 BLCKL[5:0] variable black level; input representation in accordance withITU-R BT.601; see Table 40

Table 40: BLCKL values

Conditions [1] Encoding [1]

White-to-sync = 140 IRE [2] recommended value: BLCKL = 58 (3Ah)

BLCKL = 0 [2] output black level = 29 IRE

BLCKL = 63 (3Fh) [2] output black level = 49 IRE

White-to-sync = 143 IRE [3] recommended value: BLCKL = 51 (33h)

BLCKL = 0 [3] output black level = 27 IRE

BLCKL = 63 (3Fh) [3] output black level = 47 IRE



7 GAINV8 MSB of the 9-bit code that sets the variable gain for the CR signal;see Table 37.

6 DECPH real-time control:

0 = disable subcarrier phase reset bit from RTCI

1 = enable subcarrier phase reset bit from RTCI; see Figure 22.

5 to 0 BLNNL[5:0] variable blanking level; see Table 42

Table 42: BLNNL values


White-to-sync = 140 IRE [2] recommended value: BLNNL = 46 (2Eh)

BLNNL = 0 [2] output blanking level = 25 IRE

BLNNL = 63 (3Fh) [2] output blanking level = 45 IRE

White-to-sync = 143 IRE [3] recommended value: BLNNL = 53 (35h)

BLNNL = 0 [3] output blanking level = 26 IRE

Table 38: GAINV values …continued






[2] Output black level/IRE = BLNNL × 2/6.29 + 25.4.

[3] Output black level/IRE = BLNNL × 2/6.18 + 25.9; default after reset: 35h.

BLNNL = 63 (3Fh) [3] output blanking level = 46 IRE



7 CCRS1 these 2 bits select the cross-color reduction filter in luminance;see Table 44 and Figure 106 CCRS0

5 BLNVB5 these 6 bits select the variable blanking level during vertical blanking;interval is typically identical to value of BLNNL4 BLNVB4

3 BLNVB3

2 BLNVB2

1 BLNVB1

0 BLNVB0

Table 44: Selection of cross-color reduction filter

CCRS1 CCRS0 Description

0 0 no cross-color reduction

0 1 cross-color reduction #1 active





7 DOWNB 0 = DACs for R, G and B in normal operational mode,

1 = DACs for R, G and B forced to lowest output voltage; default stateafter reset.

6 DOWNA 0 = DACs for CVBS, Y and C in normal operational mode; default stateafter reset,

1 = DACs for CVBS, Y and C forced to lowest output voltage.

5 INPI 0 = PAL switch phase is nominal; default state after reset,

1 = PAL switch phase is inverted compared to nominal if RTC is enabled;see Table 46.

4 YGS 0 = luminance gain for white − black 100 IRE; default state after reset,

1 = luminance gain for white − black 92.5 IRE including 7.5 IRE set-up ofblack.

3 SECAM 0 = no SECAM encoding; default state after reset,

1 = SECAM encoding activated; bit PAL has to be set to logic 0.

Table 42: BLNNL values …continued






2 SCBW 0 = enlarged bandwidth for chrominance encoding (for overall transfercharacteristic of chrominance in baseband representationsee Figure 8 and 9),

1 = standard bandwidth for chrominance encoding (for overall transfercharacteristic of chrominance in baseband representationsee Figure 8 and 9); default state after reset.

1 PAL 0 = NTSC encoding (non-alternating V component),

1 = PAL encoding (alternating V component); default state after reset.

0 FISE 0 = 864 total pixel clocks per line; default state after reset,

1 = 858 total pixel clocks per line.



7 RTCE 0 = no real-time control of generated subcarrier frequency; default stateafter reset,

1 = real-time control of generated subcarrier frequency through SAA7113or SAA7118; for timing, see Figure 22.

6 to 0 BSTA[6:0] amplitude of color burst; input representation in accordance withITU-R BT.601; see Table 47

Table 47: BSTA values


White-to-black = 92.5 IRE;burst = 40 IRE; NTSC encoding

recommended value: BSTA = 63 (3Fh)

BSTA = 0 to 2.02 × nominal

White-to-black = 92.5 IRE;burst = 40 IRE; PAL encoding

recommended value: BSTA = 45 (2Dh)


White-to-black = 100 IRE;burst = 43 IRE; NTSC encoding

recommended value: BSTA = 67 (43h)


White-to-black = 100 IRE;burst = 43 IRE; PAL encoding

recommended value: BSTA = 47 (2Fh); default value afterreset


Fixed burst amplitude with SECAM encoding

Table 48: Subaddresses 63h to 66h


63h FSC[07:00] these 4 bytes are used to program the subcarrier frequency;FSC[31:24] is the most significant byte, FSC[07:00] is the leastsignificant byte:

Table 45: Subaddress 61h …continued





[1] Examples:

a) NTSC-M: fsc = 227.5, fllc = 1716 → FSC = 569408543 (21F07C1Fh).

b) PAL-B/G: fsc = 283.7516, fllc = 1728 → FSC = 705268427 (2A098ACBh).

c) SECAM: fsc = 274.304, fllc = 1728 → FSC = 681786290 (28A33BB2h).

64h FSC[15:08] fsc = subcarrier frequency (in multiples of line frequency)

fllc = clock frequency (in multiples of line frequency).

65h FSC[23:16]FSC = round [1]

66h FSC[31:24]



7 to 0 L21O[07:00] first byte of captioning data, odd field; LSB of the byte is encodedimmediately after run-in and framing code, the MSB of the byte has tocarry the parity bit, in accordance with the definition of line 21encoding format



7 to 0 L21O[17:10] second byte of captioning data, odd field; the MSB of the byte has tocarry the parity bit, in accordance with the definition of line 21encoding format



7 to 0 L21E[07:00] first byte of extended data, even field; LSB of the byte is encodedimmediately after run-in and framing code, the MSB of the byte has tocarry the parity bit, in accordance with the definition of line 21encoding format



7 to 0 L21E[17:10] second byte of extended data, even field; the MSB of the byte has tocarry the parity bit, in accordance with the definition of line 21encoding format



7 SRCV11 these 2 bits define signal type on pin RCV1; see Table 54

6 SRCV10

5 TRCV2 0 = horizontal synchronization is taken from RCV1 port (at bitSYMP = LOW) or from decoded frame sync of ITU-R BT.656 input (atbit SYMP = HIGH); default state after reset,

1 = horizontal synchronization is taken from RCV2 port (at bitSYMP = LOW).

Table 48: Subaddresses 63h to 66h …continued


f sc

f llc--------- 2

32×




4 ORCV1 0 = pin RCV1 is switched to input; default state after reset,

1 = pin RCV1 is switched to output.

3 PRCV1 0 = polarity of RCV1 as output is active HIGH, rising edge is takenwhen input; default state after reset,

1 = polarity of RCV1 as output is active LOW, falling edge is takenwhen input.

2 CBLF when CBLF = 0:

If ORCV2 = 1, pin RCV2 provides an HREF signal (horizontalreference pulse that is defined by RCV2S and RCV2E, also duringvertical blanking interval); default state after reset

If ORCV2 = 0 and bit SYMP = 0, signal input to RCV2 is used forhorizontal synchronization only (if TRCV2 = 1); default state afterreset.

when CBLF = 1:

If ORCV2 = 1, pin RCV2 provides a ‘composite-blanking-not’ signal,for example a reference pulse that is defined by RCV2S andRCV2E, excluding vertical blanking interval, which is defined by FALand LAL

If ORCV2 = 0 and bit SYMP = 0, signal input to RCV2 is used forhorizontal synchronization (if TRCV2 = 1) and as an internalblanking signal.

1 ORCV2 0 = pin RCV2 is switched to input; default state after reset,

1 = pin RCV2 is switched to output.

0 PRCV2 0 = polarity of RCV2 as output is active HIGH, rising edge is takenwhen input, respectively; default state after reset,

1 = polarity of RCV2 as output is active LOW, falling edge is takenwhen input, respectively.

Table 54: Selection of the signal type on pin RCV1

SRCV11 SRCV10 RCV1 Function

0 0 VS Vertical Sync each field; default state after reset

0 1 FS Frame Sync (odd/even).

1 0 FSEQ Field Sequence, vertical sync every fourth field (PAL = 0),eighth field (PAL = 1) or twelfth field (SECAM = 1).

1 1 - not applicable



7 to 0 HTRIG[7:0] These are the 8 LSBs of the 11-bit code that sets the horizontal triggerphase related to the signal on RCV1 or RCV2 input. The 3 MSBs are heldin subaddress 6Dh; see Table 56. Values above 1715 (FISE = 1) or1727 (FISE = 0) are not allowed. Increasing HTRIG[10:0] decreasesdelays of all internally generated timing signals. Reference mark: analogoutput horizontal sync (leading slope) coincides with active edge of RCVused for triggering at HTRIG[10:0] = 4Fh (79).

Table 53: Subaddress 6Bh …continued







7 HTRIG10 these are the 3 MSBs of the horizontal trigger phase code; see Table 55

6 HTRIG9

5 HTRIG8

4 VTRIG4 sets the vertical trigger phase related to signal on RCV1 input; increasingVTRIG decreases delays of all internally generated timing signals,measured in half lines; variation range of VTRIG[4:0] = 0 to 31 (1Fh)

3 VTRIG3

2 VTRIG2

1 VTRIG1

0 VTRIG0



7 SBLBN 0 = vertical blanking is defined by programming of FAL and LAL; defaultstate after reset,

1 = vertical blanking is forced in accordance with ITU-R BT.624 (50 Hz) orRS170A (60 Hz).

6 BLCKON 0 = encoder in normal operation mode,

1 = output signal is forced to blanking level; default state after reset.

5 PHRES1 these 2 bits select the phase reset mode of the color subcarriergenerator; see Table 584 PHRES0

3 LDEL1 these 2 bits select the delay on luminance path with reference tochrominance path; see Table 592 LDEL0

1 FLC1 these 2 bits select field length control; see Table 60

0 FLC0

Table 58: Selection of phase reset mode

PHRES1 PHRES0 Description

0 0 no reset or reset via RTCI from SAA7113 or SAA7118 if bit RTCE = 1;default value after reset

0 1 reset every two lines or SECAM specific if bit SECAM = 1

1 0 reset every eight fields

1 1 reset every four fields

Table 59: Selection of luminance path delay

LDEL1 LDEL0 Luminance path delay

0 0 no luminance delay; default value after reset

0 1 1 LLC luminance delay






Table 60: Selection of field length control

FLC1 FLC0 Description

0 0 interlaced 312.5 lines/field at 50 Hz, 262.5 lines/field at 60 Hz; defaultvalue after reset

0 1 non-interlaced 312 lines/field at 50 Hz, 262 lines/field at 60 Hz

1 0 non-interlaced 313 lines/field at 50 Hz, 263 lines/field at 60 Hz

1 1



7 CCEN1 these 2 bits enable individual line 21 encoding; see Table 62

6 CCEN0

5 TTXEN 0 = disables teletext insertion; default state after reset,

1 = enables teletext insertion.

4 SCCLN4 these 5 bits select the actual line where closed caption or extended dataare encoded:

3 SCCLN3 line = (SCCLN[4:0] + 4) for M-systems

line = (SCCLN[4:0] + 1) for other systems.2 SCCLN2

1 SCCLN1

0 SCCLN0

Table 62: Selection of line 21 encoding

CCEN1 CCEN0 Line 21 encoding

0 0 line 21 encoding off; default value after reset

0 1 enables encoding in field 1 (odd)

1 0 enables encoding in field 2 (even)

1 1 enables encoding in both fields



7 to 0 RCV2S[7:0] these are the 8 LSBs of the 11-bit code that determines the start of theoutput signal on the RCV2 pin; the 3 MSBs of the 11-bit code are held atsubaddress 72h; see Table 65; values above 1715 (FISE = 1)or 1727 (FISE = 0) are not allowed; leading sync slope at CVBS outputcoincides with leading slope of RCV2 out at RCV2S = 49h



7 to 0 RCV2E[7:0] these are the 8 LSBs of the 11-bit code that determines the end of theoutput signal on the RCV2 pin; the 3 MSBs of the 11-bit code are held atsubaddress 72h; see Table 65; values above 1715 (FISE = 1)or 1727 (FISE = 0) are not allowed; leading sync slope at CVBS outputcoincides with trailing slope of RCV2 out at RCV2E = 49h






7 - this bit is reserved and must be set to a logic 0

6 RCV2E10 these are the 3 MSBs of end of output signal code; see Table 64

5 RCV2E9

4 RCV2E8

3 - this bit is reserved and must be set to a logic 0

2 RCV2S10 these are the 3 MSBs of start of output signal code; see Table 63

1 RCV2S9

0 RCV2S8



7 to 0 TTXHS[7:0] start of signal on pin TTXRQ; see Figure 23:

PAL: TTXHS[7:0] = 42h

NTSC: TTXHS[7:0] = 54h.



7 to 0 TTXHD[7:0] indicates the delay in clock cycles between rising edge of TTXRQ outputand valid data at pin TTX:

minimum value: TTXHD[7:0] = 2.



7 CSYNCA4 advanced composite sync against RGB output from 0 to 31 LLC clockperiods6 CSYNCA3

5 CSYNCA2

4 CSYNCA1

3 CSYNCA0

2 VS_S2 vertical sync shift between RCV1 and RCV2 (switched to output); inmaster mode it is possible to shift Hsync (RCV2; CBLF = 0) againstVsync (RCV1; SRCV11 = 0 and SRCV10 = 0):

Standard value: VS_S[2:0] = 3.

1 VS_S1

0 VS_S0


Bit Symbol Description Remarks

7 to 0 TTXOVS[7:0] These are the 8 LSBs of the 9-bit code thatdetermines the first line of occurrence of signalon pin TTXRQ in odd field. The MSB is held insubaddress 7Ch; see Table 75:

PAL:TTXOVS = 05h;NTSC:TTXOVS = 06h

line = (TTXOVS[8:0] + 4) for M-systems

line = (TTXOVS[8:0] + 1) for other systems.






7 to 0 TTXOVE[7:0] These are the 8 LSBs of the 9-bit code thatdetermines the last line of occurrence of signal onpin TTXRQ in odd field. The MSB is held insubaddress 7Ch; see Table 75:

PAL:TTXOVE = 16h;NTSC:TTXOVE = 10h

Last line = (TTXOVE[8:0] + 3) for M-systems

Last line = TTXOVE[8:0] for other systems.



7 to 0 TTXEVS[7:0] These are the 8 LSBs of the 9-bit code thatdetermines the first line of occurrence of signal onpin TTXRQ in even field. The MSB is held insubaddress 7Ch; see Table 75:

PAL:TTXEVS = 04h;NTSC:TTXEVS = 05h

first line = (TTXEVS[8:0] + 4) for M-systems

first line = (TTXEVS[8:0] + 1) for other systems.



7 to 0 TTXEVE[7:0] These are the 8 LSBs of the 9-bit code thatdetermines the last line of occurrence of signal onpin TTXRQ in even field. The MSB is held insubaddress 7Ch; see Table 75:

PAL:TTXEVE = 16h;NTSC:TTXEVE = 10h

last line = (TTXEVE[8:0] + 3) for M-systems

last line = TTXEVE[8:0] for other systems.



7 to 0 FAL[7:0] These are the 8 LSBs of the 9-bit code that determines the first activeline. The MSB is held in subaddress 7Ch; see Table 75; FAL[8:0] = 0coincides with the first field synchronization pulse:

first active line = (FAL[8:0] + 4) for M-systems

first active line = (FAL[8:0] + 1) for other systems.



7 to 0 LAL[7:0] These are the 8 LSBs of the 9-bit code that determines the last activeline. The MSB is held in subaddress 7Ch; see Table 75; LAL[8:0] = 0coincides with the first field synchronization pulse:

last active line = (LAL[8:0] + 3) for M-systems

last active line = LAL[8:0] for other systems.






7 TTX60 0 = enables NABTS (FISE = 1) or European teletext (FISE = 0); defaultstate after reset,

1 = enables World Standard Teletext 60 Hz (FISE = 1).

6 LAL8 MSB of the last active line code; see Table 74

5 TTXO 0 = new teletext protocol selected: at each rising edge of TTXRQ asingle teletext bit is requested; see Figure 23; default state after reset,

1 = old teletext protocol selected: the encoder provides a window ofTTXRQ going HIGH; the length of the window depends on the chosenteletext standard; see Figure 23.

4 FAL8 MSB of the first active line code; see Table 73

3 TTXEVE8 MSB of the 9-bit code that selects the last line of occurrence of signalon pin TTXRQ in even field; see Table 72

2 TTXOVE8 MSB of the 9-bit code that selects the last line of occurrence of signalon pin TTXRQ in odd field; see Table 70

1 TTXEVS8 MSB of the 9-bit code that selects the first line of occurrence of signalon pin TTXRQ in even field; see Table 71

0 TTXOVS8 MSB of the 9-bit code that selects the first line of occurrence of signalon pin TTXRQ in odd field; see Table 69



7 to 0 LINE[12:5] Individual lines in both fields (PAL counting) can be disabled for insertionof teletext by the respective LINE bits. Disabled line = LINEnn (50 Hzfield rate). This bit mask is effective only, if the lines are enabled byTTXOVS/TTXOVE and TTXEVS/TTXEVE.



7 to 0 LINE[20:13] Individual lines in both fields (PAL counting) can be disabled for insertionof teletext by the respective LINE bits. Disabled line = LINEnn (50 Hzfield rate). This bit mask is effective only, if the lines are enabled byTTXOVS/TTXOVE and TTXEVS/TTXEVE.




7.14 Slave transmitterThe slave transmitter slave address is 89h.



7 VER2 these 3 bits form the version identification number of the device: it will bechanged with all versions of the IC that have different programmingmodels; current version is 000b

6 VER1

5 VER0

4 CCRDO 1 = closed caption bytes of the odd field have been encoded,

0 = the bit is reset after information has been written to thesubaddresses 67h and 68h; it is set immediately after the data has beenencoded.

3 CCRDE 1 = closed caption bytes of the even field have been encoded,

0 = the bit is reset after information has been written to the subaddresses69h and 6Ah; it is set immediately after the data has been encoded.

2 - not used; set to logic 0

1 FSEQ 1 = during first field of a sequence (repetition rate: NTSC = 4 fields,PAL = 8 fields, SECAM = 12 fields),

0 = not first field of a sequence.

0 O_E 1 = during even field,

0 = during odd field.

(1) SCBW = 1

(2) SCBW = 0

Fig 8. Chrominance transfer characteristic 1

f (MHz)

mbe737

−30

−18

−42

−6

6

Gv(dB)

−540 1410 1282 4 6

(1) (2)




(1) SCBW = 1

(2) SCBW = 0

Fig 9. Chrominance transfer characteristic 2

(1) CCRS1 = 0; CCRS0 = 1

(2) CCRS1 = 1; CCRS0 = 0

(3) CCRS1 = 1; CCRS0 = 1

(4) CCRS1 = 0; CCRS0 = 0

Fig 10. Luminance transfer characteristic 1

0 0.4 0.8 1.6

2

0

−4

−6

−2

1.2 f (MHz)

Gv(dB)

(1)

(2)

mbe735

f (MHz)

mgd672

−30

−18

−42

−6

6

Gv(dB)

−540 1410 1282 4 6

(1)

(2)

(4)

(3)




(1) CCRS1 = 0; CCRS0 = 0

Fig 11. Luminance transfer characteristic 2

Fig 12. Luminance transfer characteristic in RGB

0 2

(1)

6

1

0

−1

−2

−3

−4

−5

mbe736

4 f (MHz)

Gv(dB)

f (MHz)

mgb708

−30

−18

−42

−6

6

Gv(dB)

−540 1410 1282 4 6




Fig 13. Color difference transfer characteristic in RGB

Fig 14. Gain of SECAM pre-emphasis

f (MHz)

mgb706

−30

−18

−42

−6

6

Gv(dB)

−540 1410 1282 4 6

f (MHz)0 1.61.20.4 0.8

mgb705

4

6

2

8

10

Gv(dB)

0




Fig 15. Phase of SECAM pre-emphasis

Fig 16. Gain of SECAM anti-Cloche

f (MHz)0 1.61.20.4 0.8

mgb704

10

20

30

ϕ(deg)

0

f (MHz)0 1.61.20.4 0.8

mgb703

8

12

4

16

20

Gv(dB)

0




Fig 17. Phase of SECAM anti-Cloche

(1) HTRIG = 0

(2) PRCV2 = 0

(3) TRCV2 = 1

(4) ORCV2 = 0

Fig 18. Sync and video input timing

f (MHz)0 1.61.20.4 0.8

mgb702

40

20

60

80

ϕ(deg)

0

mhb579

CVBS output

RCV2 input

MP input

82 LLC

79 LLC




8. Limiting values

[1] Class 2 according to EIA/JESD22-114-B.

[2] Class A according to EIA/JESD22-115-A.

9. Thermal characteristics

[1] The overall Rth(j-a) value can vary depending on the board layout. To minimize the effective Rth(j-a) all power and ground pins must beconnected to the power and ground layers directly. An ample copper area directly under the SAA7128H; SAA7129H with severalthrough-hole platings, which connect to the ground layer (four-layer board: second layer), can also reduce the effective Rth(j-a). Please donot use any solder-stop varnish under the chip. In addition the usage of soldering glue with a high thermal conductance after curing isrecommended.

(1) RCV2S = 0

(2) PRCV2 = 0

(3) ORCV2 = 1

Fig 19. Sync and video output timing

mhb580

CVBS output

RCV2 output

73 LLC

Table 79: Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134). All ground pins connected together and all supplypins connected together.

Symbol Parameter Conditions Min Max Unit

VDDD digital supply voltage −0.5 +4.6 V

VDDA analog supply voltage −0.5 +4.6 V

Vo(A) output voltage at analog output −0.5 VDDA + 0.5 V

Vi(D) input voltage at digital inputs or I/O pins outputs in 3-state −0.5 +5.5 V

Vo(D) output voltage at digital outputs outputs active −0.5 VDDD + 0.5 V

∆VSS voltage difference between VSSAall andVSSDall

- 100 mV

Tstg storage temperature −65 +150 °C

Tamb ambient temperature 0 70 °C

Vesd electrostatic discharge voltage human body model [1] - ±2000 V

machine model [2] - ±150 V

Table 80: Thermal characteristics

Symbol Parameter Conditions Typ Unit

Rth(j-a) thermal resistance from junction to ambient in free air [1] 53 K/W




10. Characteristics

Table 81: CharacteristicsVDDD = 3.0 V to 3.6 V; Tamb = 0 °C to 70 °C; unless otherwise specified.


Supply

VDDA analog supply voltage 3.15 3.3 3.45 V

VDDD digital supply voltage 3.0 3.3 3.6 V

IDDA analog supply current [1] - 130 150 mA

IDDD digital supply current VDDD = 3.3 V [1] - 75 100 mA

Inputs: LLC1, RCV1, RCV2, MP7 to MP0, RTCI, SA, RESET_N and TTX

VIL LOW-level input voltage −0.5 - +0.8 V

VIH HIGH-level input voltage 2.0 - VDDD + 0.3 V

ILI input leakage current - - 1 µA

Ci input capacitance clocks - - 10 pF

data - - 8 pF

I/Os at high-impedance - - 8 pF

Outputs: RCV1, RCV2 and TTXRQ

VOL LOW-level output voltage IOL = 2 mA - - 0.4 V

VOH HIGH-level output voltage IOH = −2 mA 2.4 - - V

I2C-bus: SDA and SCL

VIL LOW-level input voltage −0.5 - +0.3VDD(I2C) V

VIH HIGH-level input voltage 0.7VDD(I2C) - VDD(I2C) + 0.3 V

Ii input current Vi = LOW or HIGH −10 - +10 µA

VOL LOW-level output voltage (pinSDA)

IOL = 3 mA - - 0.4 V

Io output current during acknowledge 3 - - mA

Clock timing: LLC1 and XCLK

TLLC1 cycle time [2] 34 - 41 ns

δ duty factor tHIGH/TLLC1 LLC1 input 40 - 60 %

duty factor tHIGH/TXCLK XCLK output 50 %(typical)

40 - 60 %

tr rise time [2] - - 5 ns

tf fall time [2] - - 6 ns

Input timing: RCV1, RCV2, MP7 to MP0, RTCI, SA and TTX

tSU;DAT input data set-up time 6 - - ns

tHD;DAT input data hold time 3 - - ns

Crystal oscillator

fn nominal frequency (usually27 MHz)

3rd harmonic - - 30 MHz

∆f/fn permissible deviation of nominalfrequency

[3] −50 × 10−6 - +50 × 10−6

Crystal specification

Tamb ambient temperature 0 - 70 °C




[1] At maximum supply voltage with highly active input signals.

[2] The data is for both input and output direction.

[3] If an internal oscillator is used, crystal deviation of nominal frequency is directly proportional to the deviation of subcarrier frequency andline/field frequency.

[4] For full digital range, without load, VDDA = 3.3 V. The typical minimum output voltage (digital zero at DAC) is 0.2 V.

[5] Referring to peak-to-peak analog voltages resulting from identical peak-to-peak digital codes.

CL load capacitance 8 - - pF

RS series resistance - - 80 Ω

Cmot motional capacitance (typical) 1.5 − 20 % - 1.5 + 20 % fF

Cpar parallel capacitance (typical) 3.5 − 20 % - 3.5 + 20 % pF

Data and reference signal output timing

CL output load capacitance 7.5 - 40 pF

th output hold time 4 - - ns

td output delay time - - 18 ns

Outputs: C, VBS, CVBS and RGB

Vo(p-p) output signal voltage(peak-to-peak value)

[4] 1.25 1.35 1.50 V

∆V inequality of output signalvoltages

[5] - - 2 %

Rint internal serial resistance 1 - 3 Ω

RL output load resistance 75 - 300 Ω

B output signal bandwidth of DACs −3 dB 10 - - MHz

LElf(i) low frequency integral linearityerror of DACs

- - ±3 LSB

LElf(d) low frequency differentiallinearity error of DACs

- - ±1 LSB

td(pipe)(MP) total pipeline delay from MP port 27 MHz - - 82 LLC

Table 81: Characteristics …continuedVDDD = 3.0 V to 3.6 V; Tamb = 0 °C to 70 °C; unless otherwise specified.





10.1 Explanation of RTCI data bitsRefer to Figure 22:

• The HPLL increment is not evaluated by the SAA7128H; SAA7129H.

• The SAA7128H; SAA7129H generates the subcarrier frequency from the FSCPLLincrement if enabled (see last bullet).

• The PAL bit indicates the line with inverted (R − Y) component of color differencesignal.

• If the reset bit is enabled (RTCE = 1; DECPH = 1; PHRES = 00), the phase of thesubcarrier is reset in each line whenever the reset bit of RTCI input is set to logic 1.

• If the FISE bit is enabled (RTCE = 1; DECFIS = 1), the SAA7128H; SAA7129H takesthis bit instead of the FISE bit in subaddress 61h.

Fig 20. Clock data timing

mhb581

MP input data

output data

LLC1

2.0 V

0.8 V

th

td

tHIGH

TLLC1

tSU; DAT tHD; DAT tSU; DAT tHD; DAT

trtf

MPposnot

valid

2.6 V1.5 V0.6 V

MPneg MPposnot

valid

2.4 V

0.6 Vvalid not valid valid

The data demultiplexing phase is coupled to the internal horizontal phase.

The phase of the RCV2 signal is programmed to 262 for 50 Hz and to 234 for 60 Hz in this example in output mode(RCV2S).

Fig 21. Functional timing

MP(n)

LLC

CB(0) Y(0) CR(0) Y(1) CB(2)

RCV2mgb699




• If the odd/even bit is enabled (RTCE = 1; DECOE = 1), the SAA7128H; SAA7129Hignores its internally generated odd/even flag and takes the odd/even bit from RTCIinput.

• If the color detection bit is enabled (RTCE = 1; DECCOL = 1) and no color wasdetected (color detection bit = 0), the subcarrier frequency is generated by theSAA7128H; SAA7129H. In the other case (color detection bit = 1) the subcarrierfrequency is evaluated out of FSCPLL increment.

If the color detection bit is disabled (RTCE = 1; DECCOL = 0), the subcarrierfrequency is evaluated out of FSCPLL increment, independent of the color detectionbit of RTCI input.

(1) SAA7113 and SAA7118 support RTC level 3.1.

(2) Sequence bit: PAL: 0 = (R−Y) line normal, 1 = (R−Y) line inverted; NTSC: 0 = no change.

(3) FISE bit: 0 = 50 Hz, 1 = 60 Hz.

(4) Odd/even bit: odd_even from external.

(5) Color detection: 0 = no color detected, 1 = color detected.

(6) Reserved bits: 229 with 50 Hz systems, 226 with 60 Hz systems.

Fig 22. RTCI timing

12813

14 19 6764 69 72 7468

0 1

0 022RTCI

HPLLincrement (1) FSCPLL increment (1)

HIGH-to-LOW transitioncount start

4 bitsreserved

validsample

invalidsamplenot used in SAA7128H/29H

3 bitsreserved

8/LLC001aac192

LOW

time slot:

(2)(1)

(4)(5)

(6)

(3)




10.2 Teletext timingTime tFD is the time needed to interpolate input data TTX and insert it into the CVBS andVBS output signal, such that it appears at tTTX = 9.78 µs (PAL) or tTTX = 10.5 µs (NTSC)after the leading edge of the horizontal synchronization pulse.

Time tPD is the pipeline delay time introduced by the source that is gated by TTXRQ inorder to deliver TTX data. This delay is programmable by register TTXHD. For every activeHIGH state at output pin TTXRQ, a new teletext bit must be provided by the source (newprotocol) or a window of TTXRQ going HIGH is provided and the number of teletext bits,depending on the chosen teletext standard, is requested at input pin TTX (old protocol).

Since the beginning of the pulses representing the TTXRQ signal and the delay betweenthe rising edge of TTXRQ and valid teletext input data are fully programmable (TTXHSand TTXHD), the TTX data is always inserted at the correct position after the leading edgeof outgoing horizontal synchronization pulse.

Time ti(TTXW) is the internally used insertion window for TTX data; it has a constant lengththat allows insertion of 360 teletext bits at a text data rate of 6.9375 Mbit/s (PAL),296 teletext bits at a text data rate of 5.7272 Mbit/s (WST) or 288 teletext bits at a textdata rate of 5.7272 Mbit/s (NABTS). The insertion window is not opened if the control bitTTXEN is logic 0.

Using appropriate programming, all suitable lines of the odd field (TTXOVS and TTXOVE)plus all suitable lines of the even field (TTXEVS and TTXEVE) can be used for teletextinsertion.

Fig 23. Teletext timing

t i(TTXW)tTTX

tPD tFD

CVBS/Y

TTX

TTXRQ (new)

TTXRQ (old)

text bit #: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

mhb504



xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x

9397 750 14325

Product data shee

Philips S

emiconduc

11.A

pplication in

0.1 µF

+3.3 V analog

0.1 µF1 nF

10 pF 10 pF

27.0 MHz

AGND

DGND

use one capacitor

0.1 µF10 µH

+3.3 V digital

DGND

use one capacitor

t

VDDA1 to VDDA3VDDA4

25, 28, 3136

3rd harmonicX1

XTALOXTALI

AGND for each VDDA

VDDD1 to VDDD3

35 34 6, 17, 39

for each VDDD

torsS

AA

7128H; S

AA

7129HD

igital video encoder

formation

mhb583

23 Ω

75 ΩUB0.70 V (p-p)

(2)

AGND

23 Ω

75 ΩUG0.70 V (p-p)

(2)

AGND

23 Ω

75 ΩUR0.70 V (p-p)

(2)

AGND

10 Ω

75 ΩUC0.89 V (p-p)

(2)

AGND

10 Ω

75 ΩUVBS1.00 V (p-p)

(2)

AGND

4.7 Ω

75 ΩUCVBS1.23 V (p-p)

(2)

AGND

© K



ll rights reserved.

Rev. 03 —

9 Decem

ber 200447 of 55

(1) Typical value.

(2) For 100⁄100 color bar.

Fig 24. Application circuit

2 Ω(1)

VSSA1 to VSSA3

22, 32, 33

DAC6 BLUE

AGND

VSSD1 to VSSD3

5, 18, 38

DGND

29

2 Ω(1)DAC5 GREEN26

2 Ω(1)DAC4 RED23

2 Ω(1)DAC3 C24

2 Ω(1)DAC2 VBS27

2 Ω(1)DAC1 CVBS

digitalinputs and

outputs

30

SAA7128HSAA7129H


11.1 Analog output voltagesThe analog output voltages are dependent on the open-loop voltage of the operationalamplifiers for full-scale conversion (typical value 1.35 V), the internal series resistor(typical value 2 Ω), the external series resistor and the external load impedance.

The digital output signals in front of the DACs under nominal conditions occupy differentconversion ranges, as indicated in Table 82 for a 100⁄100 color bar signal.

Values for the external series resistors result in a 75 Ω load.

Table 82: Digital output signals conversion range Ordering information

Conversion range (peak-to-peak)

CVBS sync-tip to peak-carrier(digits)

Y (VBS) sync-tip to white(digits)

RGB (Y) black to white atGDY = GDC = −6 (digits)

1016 881 712




12. Package outline

Fig 25. Package outline SOT307-2 (QFP44)

UNIT A1 A2 A3 bp c E(1) e HE L L p Zywv θ

REFERENCESOUTLINEVERSION

EUROPEANPROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.250.05

1.851.65

0.250.40.2

0.250.14

10.19.9

0.8 1.312.912.3

1.20.8

100

o

o0.15 0.10.15

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

0.950.55

SOT307-297-08-0103-02-25

D(1) (1)(1)

10.19.9

HD

12.912.3

EZ

1.20.8

D

e

E

B

11

c

EH

D

ZD

A

ZE

e

v M A

X

1

44

34

33 23

22

12

y

θ

A1A

Lp

detail X

L

(A )3A2

pin 1 index

DH v M B

bp

bp

w M

w M

0 2.5 5 mm

scale

QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm SOT307-2

Amax.

2.1




13. Soldering

13.1 Introduction to soldering surface mount packagesThis text gives a very brief insight to a complex technology. A more in-depth account ofsoldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages(document order number 9398 652 90011).

There is no soldering method that is ideal for all surface mount IC packages. Wavesoldering can still be used for certain surface mount ICs, but it is not suitable for fine pitchSMDs. In these situations reflow soldering is recommended.

13.2 Reflow solderingReflow soldering requires solder paste (a suspension of fine solder particles, flux andbinding agent) to be applied to the printed-circuit board by screen printing, stencilling orpressure-syringe dispensing before package placement. Driven by legislation andenvironmental forces the worldwide use of lead-free solder pastes is increasing.

Several methods exist for reflowing; for example, convection or convection/infraredheating in a conveyor type oven. Throughput times (preheating, soldering and cooling)vary between 100 seconds and 200 seconds depending on heating method.

Typical reflow peak temperatures range from 215 °C to 270 °C depending on solder pastematerial. The top-surface temperature of the packages should preferably be kept:

• below 225 °C (SnPb process) or below 245 °C (Pb-free process)

– for all BGA, HTSSON..T and SSOP..T packages

– for packages with a thickness ≥ 2.5 mm

– for packages with a thickness < 2.5 mm and a volume ≥ 350 mm3 so calledthick/large packages.

• below 240 °C (SnPb process) or below 260 °C (Pb-free process) for packages with athickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages.

Moisture sensitivity precautions, as indicated on packing, must be respected at all times.

13.3 Wave solderingConventional single wave soldering is not recommended for surface mount devices(SMDs) or printed-circuit boards with a high component density, as solder bridging andnon-wetting can present major problems.

To overcome these problems the double-wave soldering method was specificallydeveloped.

If wave soldering is used the following conditions must be observed for optimal results:

• Use a double-wave soldering method comprising a turbulent wave with high upwardpressure followed by a smooth laminar wave.

• For packages with leads on two sides and a pitch (e):

– larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to beparallel to the transport direction of the printed-circuit board;




– smaller than 1.27 mm, the footprint longitudinal axis must be parallel to thetransport direction of the printed-circuit board.

The footprint must incorporate solder thieves at the downstream end.

• For packages with leads on four sides, the footprint must be placed at a 45° angle tothe transport direction of the printed-circuit board. The footprint must incorporatesolder thieves downstream and at the side corners.

During placement and before soldering, the package must be fixed with a droplet ofadhesive. The adhesive can be applied by screen printing, pin transfer or syringedispensing. The package can be soldered after the adhesive is cured.

Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 °Cor 265 °C, depending on solder material applied, SnPb or Pb-free respectively.

A mildly-activated flux will eliminate the need for removal of corrosive residues in mostapplications.

13.4 Manual solderingFix the component by first soldering two diagonally-opposite end leads. Use a low voltage(24 V or less) soldering iron applied to the flat part of the lead. Contact time must belimited to 10 seconds at up to 300 °C.

When using a dedicated tool, all other leads can be soldered in one operation within2 seconds to 5 seconds between 270 °C and 320 °C.

13.5 Package related soldering information

[1] For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026);order a copy from your Philips Semiconductors sales office.

[2] All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, themaximum temperature (with respect to time) and body size of the package, there is a risk that internal orexternal package cracks may occur due to vaporization of the moisture in them (the so called popcorneffect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated CircuitPackages; Section: Packing Methods.

[3] These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on noaccount be processed through more than one soldering cycle or subjected to infrared reflow soldering withpeak temperature exceeding 217 °C ± 10 °C measured in the atmosphere of the reflow oven. The packagebody peak temperature must be kept as low as possible.

Table 83: Suitability of surface mount IC packages for wave and reflow soldering methods

Package [1] Soldering method

Wave Reflow [2]

BGA, HTSSON..T [3], LBGA, LFBGA, SQFP,SSOP..T [3], TFBGA, VFBGA, XSON

not suitable suitable

DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP,HSQFP, HSSON, HTQFP, HTSSOP, HVQFN,HVSON, SMS

not suitable [4] suitable

PLCC [5], SO, SOJ suitable suitable

LQFP, QFP, TQFP not recommended [5] [6] suitable

SSOP, TSSOP, VSO, VSSOP not recommended [7] suitable

CWQCCN..L [8], PMFP [9], WQCCN..L [8] not suitable not suitable




[4] These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, thesolder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsinkon the top side, the solder might be deposited on the heatsink surface.

[5] If wave soldering is considered, then the package must be placed at a 45° angle to the solder wavedirection. The package footprint must incorporate solder thieves downstream and at the side corners.

[6] Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it isdefinitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

[7] Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or largerthan 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

[8] Image sensor packages in principle should not be soldered. They are mounted in sockets or deliveredpre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex foil byusing a hot bar soldering process. The appropriate soldering profile can be provided on request.

[9] Hot bar soldering or manual soldering is suitable for PMFP packages.




14. Revision history

Table 84: Revision history

Document ID Releasedate

Data sheet status Changenotice

Doc. number Supersedes

SAA7128H_SAA7129H_3 20041209 Product data sheet - 9397 750 14325 SAA7128H_7129H_2

Modifications: • Added Table 79 “Limiting values”

• Updated Table 80 “Thermal characteristics”

• Changed the type number of some referenced ICs.

SAA7128H_7129H_2 20021015 Product specification - 9397 750 09727 SAA7128H_7129H_1

SAA7128H_7129H_1 000308 Product specification - 9397 750 06127




15. Data sheet status

[1] Please consult the most recently issued data sheet before initiating or completing a design.

[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet atURL http://www.semiconductors.philips.com.

[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

16. Definitions

Short-form specification — The data in a short-form specification isextracted from a full data sheet with the same type number and title. Fordetailed information see the relevant data sheet or data handbook.

Limiting values definition — Limiting values given are in accordance withthe Absolute Maximum Rating System (IEC 60134). Stress above one ormore of the limiting values may cause permanent damage to the device.These are stress ratings only and operation of the device at these or at anyother conditions above those given in the Characteristics sections of thespecification is not implied. Exposure to limiting values for extended periodsmay affect device reliability.

Application information — Applications that are described herein for anyof these products are for illustrative purposes only. Philips Semiconductorsmake no representation or warranty that such applications will be suitable forthe specified use without further testing or modification.

17. Disclaimers

Life support — These products are not designed for use in life supportappliances, devices, or systems where malfunction of these products canreasonably be expected to result in personal injury. Philips Semiconductorscustomers using or selling these products for use in such applications do soat their own risk and agree to fully indemnify Philips Semiconductors for anydamages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right tomake changes in the products - including circuits, standard cells, and/orsoftware - described or contained herein in order to improve design and/orperformance. When the product is in full production (status ‘Production’),relevant changes will be communicated via a Customer Product/ProcessChange Notification (CPCN). Philips Semiconductors assumes no

responsibility or liability for the use of any of these products, conveys nolicense or title under any patent, copyright, or mask work right to theseproducts, and makes no representations or warranties that these products arefree from patent, copyright, or mask work right infringement, unless otherwisespecified.

18. Licenses

19. Patents

Notice is herewith given that the subject device uses one or more of thefollowing patents and that each of these patents may have correspondingpatents in other jurisdictions.

US 4631603 — owned by Macrovision Corporation



20. Trademarks

Macrovision — is a registered trademark of Macrovision Corporation

21. Contact information

For additional information, please visit: http://www.semiconductors.philips.com

For sales office addresses, send an email to: [email protected]

Level Data sheet status [1] Product status [2] [3] Definition

I Objective data Development This data sheet contains data from the objective specification for product development. PhilipsSemiconductors reserves the right to change the specification in any manner without notice.

II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be publishedat a later date. Philips Semiconductors reserves the right to change the specification without notice, inorder to improve the design and supply the best possible product.

III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves theright to make changes at any time in order to improve the design, manufacturing and supply. Relevantchanges will be communicated via a Customer Product/Process Change Notification (CPCN).

Purchase of Philips I 2C-bus components

Purchase of Philips I2C-bus components conveys alicense under the Philips’ I2C-bus patent to use thecomponents in the I2C-bus system provided the systemconforms to the I2C-bus specification defined byKoninklijke Philips Electronics N.V. This specificationcan be ordered using the code 9398 393 40011.




22. Contents

1 General description . . . . . . . . . . . . . . . . . . . . . . 12 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Quick reference data . . . . . . . . . . . . . . . . . . . . . 24 Ordering information . . . . . . . . . . . . . . . . . . . . . 25 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Pinning information . . . . . . . . . . . . . . . . . . . . . . 46.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 47 Functional description . . . . . . . . . . . . . . . . . . . 67.1 Versatile fader . . . . . . . . . . . . . . . . . . . . . . . . . . 77.1.1 Configuration examples . . . . . . . . . . . . . . . . . . 77.1.1.1 Configuration 1 . . . . . . . . . . . . . . . . . . . . . . . . . 77.1.1.2 Configuration 2 . . . . . . . . . . . . . . . . . . . . . . . . . 87.1.1.3 Configuration 3 . . . . . . . . . . . . . . . . . . . . . . . . . 87.1.1.4 Configuration 4 . . . . . . . . . . . . . . . . . . . . . . . . . 97.1.2 Parameters of the fader . . . . . . . . . . . . . . . . . . 97.2 Data manager . . . . . . . . . . . . . . . . . . . . . . . . . 107.3 Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107.3.1 Video path. . . . . . . . . . . . . . . . . . . . . . . . . . . . 107.3.2 Teletext insertion and encoding . . . . . . . . . . . 107.3.3 Video Programming System (VPS) encoding. 117.3.4 Closed caption encoder . . . . . . . . . . . . . . . . . 117.3.5 Anti-taping (SAA7128H only) . . . . . . . . . . . . . 117.4 RGB processor . . . . . . . . . . . . . . . . . . . . . . . . 117.5 SECAM processor . . . . . . . . . . . . . . . . . . . . . 117.6 Output interface/DACs . . . . . . . . . . . . . . . . . . 127.7 Synchronization . . . . . . . . . . . . . . . . . . . . . . . 127.8 Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137.9 I2C-bus interface . . . . . . . . . . . . . . . . . . . . . . . 137.10 Input levels and formats . . . . . . . . . . . . . . . . . 147.11 Bit allocation map . . . . . . . . . . . . . . . . . . . . . . 157.12 I2C-bus format. . . . . . . . . . . . . . . . . . . . . . . . . 187.13 Slave receiver . . . . . . . . . . . . . . . . . . . . . . . . . 187.14 Slave transmitter . . . . . . . . . . . . . . . . . . . . . . . 358 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 419 Thermal characteristics. . . . . . . . . . . . . . . . . . 4110 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 4210.1 Explanation of RTCI data bits . . . . . . . . . . . . . 4410.2 Teletext timing. . . . . . . . . . . . . . . . . . . . . . . . . 4611 Application information. . . . . . . . . . . . . . . . . . 4711.1 Analog output voltages . . . . . . . . . . . . . . . . . . 4812 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 4913 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5013.1 Introduction to soldering surface mount

packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

13.2 Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 5013.3 Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 5013.4 Manual soldering . . . . . . . . . . . . . . . . . . . . . . 5113.5 Package related soldering information . . . . . . 5114 Revision history . . . . . . . . . . . . . . . . . . . . . . . 5315 Data sheet status. . . . . . . . . . . . . . . . . . . . . . . 5416 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5417 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 5418 Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5419 Patents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5420 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 5421 Contact information . . . . . . . . . . . . . . . . . . . . 54

© Koninklijke Philips Electronics N.V. 2004All rights are reserved. Reproduction in whole or in part is prohibited without the priorwritten consent of the copyright owner. The information presented in this document doesnot form part of any quotation or contract, is believed to be accurate and reliable and maybe changed without notice. No liability will be accepted by the publisher for anyconsequence of its use. Publication thereof does not convey nor imply any license underpatent- or other industrial or intellectual property rights.

Date of release: 9 December 2004Document number: 9397 750 14325

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