Sales Training 3/14/2013Owner : SAYD Cypress Confidential

IDT ICS8543 vs. Cypress CY2DL1504

Clock distribution in Router applications

Clock signals delivered on time! Everytime!

2Owner : SAYD Cypress Confidential Sales Training 3/14/2013

CYPRESS INTERNAL USE ONLY

IDT ICS8543 Overview

IDT ICS8543 is a high performance fan-out buffer featuring Maximum frequency of 0.8 GHz

Additive RMS phase jitter of 0.32 ps

Output skew of 40 ps and propagation delay of 2600 ps

Supports single ended and multiple differential input standards including LVPECL,LVDS,HSTL,SSTL,CML and HSCL

4 differential LVDS output pairs

IDT ICS8543 find applications in: Networking systems

Telecommunication systems

Storage

Infrastructure and Test Equipment

IDT ICS8543 accepts wide range of input standards

IDT ICS8543

3Owner : SAYD Cypress Confidential Sales Training 3/14/2013

CYPRESS INTERNAL USE ONLY

Challenges using IDT ICS8543

1. 40G/100G Enterprise routers have high frequency requirementsHigh speed Enterprise routers utilize I2C Voltage Controlled Oscillators (VCXO) which operate upto frequencies of 945 MHz

IDT ICS8543 has a maximum operating frequency of 800 MHz

IDT ICS8543 does not support such high frequency requirements

2. Additive noise increases Bit Error Rate (BER)High noise levels in the circuit result in increased errors during bit detection

Low additive RMS phase jitter is a critical requirement for enterprise routers

IDT ICS8543 has additive RMS phase jitter of 0.164 ps

3. Propagation delays result in packet lossDelay in propagation of clock signals to PHY circuits result in loss of data at transceiver ports

IDT ICS8543 has high propagation delay of 2600 ps

CY2DL1504 solves these problemsCY2DL1504 has a maximum operating frequency of 1500 MHz supporting higher frequency requirements

CY2DL1504 has a very low additive RMS phase jitter of .05 ps resulting in less noise addition to clock signals

CY2DL1504 ensures faster signal transmission with propagation delays of less than 480 ps

Ethernet routers require high frequency clock distributors

CY2DL1504 High Performance Buffer ensures clock signal distribution with least additive noise and low propagation delay

Enterprise Routers

4Owner : SAYD Cypress Confidential Sales Training 3/14/2013

CYPRESS INTERNAL USE ONLY

IDT ICS8543 vs CY2DL1504

Cypress Confidential

The indicated parameters are in the perceived order of importance

*Duty Cycle of 50/50 is ideal

Feature IDT ICS8543 CY2DL1504

Additive RMS phase jitter (ps) 0.164 .05

Max propagation delay - Tpd (ps) 2600 480

Max Output Skew (ps) 40 30

Trise/ Tfall (ps) (max) 450 300

Fmax (GHz) (max) 0.8 1.5

Duty Cycle* 45/55 500MHz 48/52 500MHz

Input Standards LVPECL,LVDS,HSTL,SSTL,CML,HSCL LVDS,LVPECL,HSCL,CML

Output Standard LVDS LVDS

Operating Temperature (oC) 0 to 70 -45 to 85

Device Package 20 -TSSOP 20 -TSSOP

5Owner : SAYD Cypress Confidential Sales Training 3/14/2013

CYPRESS INTERNAL USE ONLY

Customer objections to adoptingCY2DL1504 over IDT ICS8543 “Previous design was using IDT ICS8543”CY2DL1504 is pin to pin compatible with IDT ICS8543

CY2DL1504 offers better specifications and performance than the IDT ICS8543

“CY2DL1504 does not accept SSTL and HSTL clock input standards”CY2DL1504 accepts LVDS,LVPECL,HSCL,CML inputs which are the most popularly used clock input standards for Enterprise

Router applications

6Owner : SAYD Cypress Confidential Sales Training 3/14/2013

CYPRESS INTERNAL USE ONLY

Sales Cautions for CY2DL1504

Cypress has a narrow portfolio in clock distributionCypress has a limited portfolio of 4 output High Performance Buffers when compared to IDT’s broader portfolio for 4 output fan -out buffers, offering more options to customers

Cypress Confidential

7Owner : SAYD Cypress Confidential Sales Training 3/14/2013

CYPRESS INTERNAL USE ONLY

CY2DL1504 Design Win Example –Enterprise Router

Product Selector Guide: Clocks and BuffersBasic Training: Perfect Timing II Book White Paper:

Timing Uncertainty in High Performance Clock Distribution 

Data Sheets: CY2DL1504

Design ChallengesMinimize BER due to noise (Jitter)Minimize clock signal propagation delays to minimize data loss

CY2DL1504 SolutionVery low addditive RMS phase jitter of 0.05 ps minimizes

effects of noise Low propagation delay of 480 ps ensures faster clock signal delivery to router components

CY2DL1504 Value

Suggested Collateral

IDT ICS8543

Block Diagram

Competition

40G/100G Enterprise routerCY2DL1504 provides lowest additive RMS phase jitter of 0.05 ps and low propagation delay of 480 ps