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SAM D5xE5x Family SAM D5xE5x Family Silicon Errata and Data Sheet

Clarification

SAM D5xE5x Family ErrataThe SAM D5xE5x family of devices that you have received conform functionally to the current preliminary DeviceData Sheet (DS60001507E) except for the anomalies described in this document

The silicon issues discussed in the following pages are for silicon revisions with the Device and Revision IDs listed inTable 1 SAM D5xE5x Family Silicon Device Identification The silicon issues are summarized in the Table ofContents following this section

The errata described in this document will be addressed in future revisions of the SAM D5xE5x family silicon

Note This document summarizes all silicon errata issues from all revisions of silicon previous as well as current

copy 2019 Microchip Technology Inc DS80000748J-page 1

Table 1 SAM D5xE5x Family Silicon Device Identification

Part Number Device Identification (DID[310])Revision ID (DIDREVISION[30])

A D

ATSAME54P19A 0x61840x01

0x0 0x3


ATSAME54N19A 0x61840x03




ATSAME53J18A 0x61830x06








ATSAMD51P20A 0x60060x00


ATSAMD51N19A 0x60060x03


ATSAMD51J18A 0x60060x06



ATSAMD51G18A 0x60060x08


ATSAME51G18A 0x61810306NA 0x3

ATSAME51G19A 0x61810305

Data Sheet clarifications and corrections (if applicable) are located in the section Data Sheet Clarifications followingthe discussion of silicon issues

Note Refer to the ldquoDevice Service Unitrdquo chapter in the current preliminary device data sheet (DS60001507E) for adetailed information on Device Identification and Revision IDs for your specific device

SAM D5xE5x Family


Table of Contents

SAM D5xE5x Family Errata1

1 Silicon Errata Summary 4

2 Silicon Errata Issues 10

21 Analog-to-Digital Converter (ADC)1022 Analog Comparator (AC) 1123 Configurable Custom Logic (CCL) 1224 Controller Area Network (CAN)1225 Clock Failure Detector (CFD)1826 Device 1927 Device Service Unit (DSU)2028 48 MHz Digital Frequency-Locked Loop (DFLL48M)2129 Digital-to-Analog Converter (DAC)22210 Direct Memory Access Controller (DMAC)23211 Ethernet MAC (GMAC)24212 External Interrupt Controller (EIC)25213 Fractional Digital Phase-Locked Loop (FDPLL)25214 Non-Volatile Memory Controller (NVMCTRL)26215 Peripheral Access Controller (PAC) 26216 IO Pin Controller (PORT) 27217 Real-Time Counter (RTC) 28218 Serial Communication Interface (SERCOM)29219 Supply Controller (SUPC) 35220 TimerCounter (TC) 35221 TimerCounter for Control Applications (TCC)36222 Position Decoder (PDEC)37223 Voltage Reference System37

3 Data Sheet Clarifications38

4 Appendix A Revision History40

The Microchip Web Site 43

Customer Change Notification Service 43

Customer Support 43

Microchip Devices Code Protection Feature 43

Legal Notice 44

Trademarks 44

Quality Management System Certified by DNV 44

Worldwide Sales and Service45

SAM D5xE5x Family


1 Silicon Errata SummaryTable 1-1 Errata Summary

Module FeatureItem

NumberIssue Summary

EFPNon-EFP

AffectedRevisions

A D

Analog -to-DigitalConverter(ADC)

ADC SYNCBUSYSWTRIG 211The ADC SYNCBUSYSWTRIG gets stuck to 1 after wake-upfrom Standby Sleep mode

EFP - X

Non-EFP

X X


ADC TUEINLDNL 212

The ADC TUEINLDNL performance is not guaranteed in thefollowing scenarios

bull Sampling frequency is above 500 ksps

bull ADC VREF is different from VDDANA

EFP -

Non-EFP

X


Reference Buffer OffsetCompensation

213

ADC converted data could be erroneous when using theReference Buffer (REFCTRLREFSEL =INTREF INTVCC0INTVCC1 VREFA or VREB) and when Reference Buffer OffsetCompensation is enabled (REFCTRLREFCOMP = 1)

EFP - X

Non-EFP

X X


DMA Sequencing 214ADC DMA Sequencing with prescalergt8 (ADC-gtCTRLAbitPRESCALERgt2) does not produce the expectedchannel sequence

EFP - X

Non-EFP

X X


DMA Sequencing 215

ADC DMA Sequencing with averaging enabled(AVGCTRLSAMPLENUMgt1) without AVGCTRL bit set(DSEQCTRLAVGCTRL=0) in the update sequence does notproduce the expected channel sequence

EFP - X

Non-EFP

X X

Analog Comparator(AC)

AC Hysteresis 221Enabling Hysteresis (COMPCTRLnHYSTEN = 0x1) changes thethreshold voltage (VTH-) which could result in unexpectedbehavior of the Analog Comparator

EFP - X

Non-EFP

X X


Output 222In continuous mode the Comparator output may toggle duringstartup time before the Ready Status bit is set (STATUSBREADY= 1)

EFP - X

Non-EFP

X X

Configurable CustomLogic (CCL)

Enable Protected Registers 231The SEQCTRLx and LUCTRLx registers are enable-protected bythe CTRLENABLE bit whereas they should be enable-protectedby the LUTCTRLxENABLE bits

EFP - X

Non-EFP

X X


Sequential Logic 232LUT output is corrupted after enabling CCL when sequential logicis used

EFP - X

Non-EFP

X X

Controller AreaNetwork (CAN)

CAN Edge Filtering 241

When edge filtering is activated (CCCREFBI = 1) and when theend of the integration phase coincides with a falling edge at theRx input pin it may occur that the CAN synchronizes itselfincorrectly and does not correctly receive the first bit of the frameIn this case the CRC will detect the first bit that was receivedincorrectly it will rate the received FD frame as faulty and an errorframe will be send

EFP - X

Non-EFP

X X


Dominant Bit of Intermission 242

When NBTPNTSEG2 is configured to zero (Phase_Seg2(N) = 1)and when there is a pending transmission request a dominantthird bit of Intermission may cause the CAN to wrongly transmitthe first identifier bit dominant instead of recessive even if this bitwas configured as 1 in the Tx Buffer Element of the CAN module

EFP - X

Non-EFP

X X


INTFLAG Status 243 Message transmitted with wrong arbitration and control fields

EFP - X

Non-EFP

X X

SAM D5xE5x FamilySilicon Errata Summary


continued

Module FeatureItem

NumberIssue Summary

EFPNon-EFP

AffectedRevisions

A D


DAR Mode 244 Retransmission in DAR mode due to lost arbitration

EFP - X

Non-EFP

X X


High Priority Message(HPM) interrupt

245 Unexpected High Priority Message (HPM) interrupt

EFP - X

Non-EFP

X X


TxFIFO 246 Tx FIFO message sequence inversion

EFP - X

Non-EFP

X X

Clock Failure Detector(CFD)

CFD with XOSCXOSC32KOscillator

251When the CFD is enabled for the XOSCXOSC32K oscillator andthe oscillator input signal is stuck at 1 the clock failure detectionworks correctly but the switch to the safe clock will fail

EFP -

Non-EFP

X

DeviceReverse Current in VDDIOB

Domain261

For the device with 100-pin 120-pin and 128-pin counts whenVDDIOB is supplied with the voltage less than VDDIO - 07Vreverse current in VDDIOB cluster is observed

EFP -

Non-EFP

X

DeviceInternal Pull-up on the

RESET Pin262 The internal pull-up of the RESET pin is not functional

EFP -

Non-EFP

X

DeviceDetection of a Debugger

Probe263

The detection of a debugger probe could fail if the BOD33Disable fuse is cleared (ie BOD33 is enabled)

EFP - X

Non-EFP

X X

Device VBAT Mode 264 VBAT mode is not functional

EFP -

Non-EFP

X

Device Internal Reference 265When the internal reference is used with the DAC and ADC theiroutputs become non-linear when the operating temperature is lessthan 0degC

EFP -

Non-EFP

X

DeviceDevice Operation forTemperature lt -20degC

266If the operating temperature is less than -20degC the device doesnot start

EFP -

Non-EFP

X X

Device Service Unit CRC32 271DSU CRC32 will not complete when targeting NVM memoryspace while the NVM cache is disabled

EFP - X

Non-EFP

X X

48 MHz DigitalFrequency-LockedLoop (DFLL48M)

COARSE or FINECalibration Values During

the Locking Sequence281

If the DFLL48M reaches the maximum or minimum COARSE orFINE calibration values during the locking sequence an out ofbounds interrupt will be generated

EFP - X

Non-EFP

X X


STATUSDFLLRDY Bit inClose Loop Mode

282In Close Loop mode the STATUSDFLLRDY bit does not risebefore lock fine occurs Therefore the information about DFLLready to start Close Loop mode is not available

EFP - X

Non-EFP

X X


DFLLVALFINE Value WhenDFLL48M Re-enabled

283If the DFLL is disabled and then re-enabled the DFLLVALFINEvalue is ignored by the DFLL module which will then start its lockfine process at another frequency

EFP -

Non-EFP

X



continued

Module FeatureItem

NumberIssue Summary

EFPNon-EFP

AffectedRevisions

A D


LLAW 284

When the Lose Lock After Wake (LLAW) is set the DFLL maymaintain lock (STATTUSDFLLLOCK = 1) after the DFLL isdisabled If the DFLL lock (STATUSDFLLLOCK = 1) is maintainedwhen the DFLL is reconfigured and then enabled some bits maynot be properly set

EFP - X

Non-EFP

X X

Digital-to-AnalogConverter (DAC)

Differential Mode theSmoothing of the Output

Signal291

In Differential mode the smoothing of the output signal is not fullyfunctional

EFP - X

Non-EFP

X X


VDDANA as the DACReference

292The selection of VDDANA as the DAC reference inDACCTRLBREFSEL is non-functional

EFP -

Non-EFP

X


DAC on Negative InputAIN3

293No analog compare will be done on Comparator 1 (AC1) whenusing the DAC on negative input AIN3

EFP -

Non-EFP

X


Interpolation Mode 294If the Interpolation mode is enabled (with filter integrated to theDAC) the last data from the filter is missing hence the DAC finaloutput value does not correspond to the DAC input value

EFP - X

Non-EFP

X X


Reference 295The reference select of the DAC (CTRLBREFSEL) will default toa lsquo0rsquo if the DAC Software Reset (CTRLASWRST) is used to resetthe module

EFP - X

Non-EFP

X X

Direct Memory AccessController (DMAC)

Linked Descriptors 2101

When at least one channel using linked descriptors is alreadyactive a channel Fetch Error (FERR) could occur on enabling achannel with no linked descriptor or the second descriptor (index1) of the channel being enabled could be fetched by one of thealready active channels using linked descriptors

EFP - X

Non-EFP

X X


Channel Priority 2102When using channels with different priority levels the highestpriority channel could stall at the end of its current block

EFP -

Non-EFP

X


DMAC in Debug Mode 2103In debug mode DMAC does not restart after a debug halt whenDBGCTRLDBGRUN=0

EFP -

Non-EFP

X

Ethernet MAC (GMAC)Ethernet Functionality in 64-

pin Packages2111 Ethernet functionality in 64-pin packages is not available

EFP -

Non-EFP

X

External InterruptController (EIC)

Edge Detection 2121When enabling EIC SYNCBUSYENABLE is released before EICis fully enabled Edge detection can be done only after threecycles of the selected GCLK (GCLK_EIC or CLK_ULP32K)

EFP - X

Non-EFP

X X


Asynchronous EdgeDetection

2122When the asynchronous edge detection is enabled and thesystem is in Standby mode only the first edge will be detectedThe following edges are ignored until the system wakes up

EFP - X

Non-EFP

X X

Fractional DigitalPhase-Locked Loop

(FDPLL)

Low-Frequency Input Clockon FDPLLn

2131When using a low-frequency input clock (le400kHz) on FDPLLnseveral FDPLL unlocks could occur while the output frequency isstable

EFP - X

Non-EFP

X X


(FDPLL)

FDPLL Ratio inDPLLnRATIO

2132When changing the FDPLL ratio in DPLLnRATIO register on-the-fly STATUSDPLLnLDRTO will not beset when the ratio updatewill be completed

EFP - X

Non-EFP

X X



continued

Module FeatureItem

NumberIssue Summary

EFPNon-EFP

AffectedRevisions

A D

Non-Volatile MemoryController (NVMCTRL)

NVM Read Corruption 2141NVM reads could be corrupted when mixing NVM reads with PageBuffer writes

EFP - X

Non-EFP

X X

Peripheral AccessController (PAC)

PAC Protection Error inFREQM

2151FREQM reads on the Control B register (FREQMCTRLB)generate a PAC protection error

EFP - X

Non-EFP

X X


PAC Protection Error in CCL 2152Writing the Software Reset bit in the Control A register(CTRLASWRST) will trigger a PAC protection error

EFP - X

Non-EFP

X X

IO Pin Controller(PORT)

PORT ReadWrite Attemptson Non-Implemented

Registers2161

PORT readwrite attempts on non-implemented registersincluding addresses beyond the last implemented register group(PA PB) do not generate a PAC protection error

EFP - X

Non-EFP

X X


PORT Pull-UpPull-DownResistor

2162

The pull-down on PA24PA25 are activated during power-up andwhen Sleep mode is OFF On all other pins except those in theVSWOUT cluster the pull-up is activated during power-up andwhen Sleep mode is OFF

EFP -

Non-EFP

X

Real-Time Counter(RTC)

Write Corruption 2171

A 8-bit or 16-bit write access for a 32-bit register or 8-bit writeaccess for a 16-bit register can fail for the following registers

bull The COUNT register in COUNT32 mode


bull The CLOCK register in CLOCK mode

EFP - X

Non-EFP

X X


COUNTSYNC 2172When COUNTSYNC is enabled the first COUNT value is notcorrectly synchronized and therefore it is a wrong value

EFP - X

Non-EFP

X X


Tamper Input Filter 2173Majority debouncing as part of RTC tamper detection does notwork when enabled by setting Debouncer Majority Enable bitCTRLBDEBMAJ

EFP - X

Non-EFP

X X


Tamper Detection 2174Upon enabling the RTC a false tamper detection could bereported by the RTC

EFP - X

Non-EFP

X X


Tamper DetectionTimestamp

2175If an external reset occurs during a tamper detection theTIMESTAMP register will not be updated when next tamperdetection is triggered

EFP - X

Non-EFP

X X


PRESCALER 2176When the tamper or debouncing features (TAMPCTRL) areenabled periodic interrupts and events are generated when theprescaler is OFF (CTRLAPRESCALER=0)

EFP - X

Non-EFP

X X

Serial CommunicationInterface (SERCOM)

SERCOM-USART USARTAuto-Baud Mode

2181In USART Auto-Baud mode missing stop bits are not recognizedas inconsistent sync (ISF) or framing (FERR) errors

EFP - X

Non-EFP

X X


SERCOM-USART CollisionDetection

2182

In USART operating mode with Collision Detection enabled(CTRLBCOLDEN=1) the SERCOM will not abort the currenttransfer as expected if a collision is detected and if the SERCOMAPB Clock is lower than the SERCOM Generic Clock

EFP - X

Non-EFP

X X


SERCOM-USART DebugMode

2183In USART operating mode if DBGCTRLDBGSTOP=1 datatransmission is not halted after entering Debug mode

EFP - X

Non-EFP

X X



continued

Module FeatureItem

NumberIssue Summary

EFPNon-EFP

AffectedRevisions

A D


SERCOM-USART 32-bitExtension Mode

2184When 32-bit Extension mode is enabled and data to be sent is notin multiples of 4 bytes (which means the length counter must beenabled) additional bytes will be sent over the line

EFP - X

Non-EFP

X X


SERCOM-UART TXINVand RXINV Bits

2185The TXINV and RXINV bits in the CTRLA register have invertedfunctionality

EFP - X

Non-EFP

X X


SERCOM-I2C SDAHOLDTiming

2186SDAHOLD timing of the SERCOM-I2C does not match the valueshown in the current device data sheet

EFP - X

Non-EFP

X X


Repeated Start in High-Speed Master Write

Operation2187

For High-Speed Master Write operations writing CTRLBCMD =0x1 issues a STOP command instead of a Repeated Start makingrepeated start not possible in that mode

EFP - X

Non-EFP

X X


Repeated Start in High-Speed Master Read

Operation2188

For High-Speed Master Read operations sending a NACK(CTRLBCMD = 0x2) forces a STOP to be issued makingrepeated start not possible in that mode

EFP - X

Non-EFP

X X


STATUSCLKHOLD Bit inMaster and Slave Modes

2189The STATUSCLKHOLD bit in master and slave modes can bewritten whereas it is a read-only status bit

EFP - X

Non-EFP

X X


SERCOM-I2C I2C in SlaveMode

21810In I2C mode LENERR SEXTOUT LOWTOUT COLL andBUSERR bits are not cleared when INTFLAGAMATCH iscleared

EFP - X

Non-EFP

X X


SERCOM-I2C Slave Modewith DMA

21811In I2C Slave Transmitter mode at the reception of a NACK ifthere is still data to be sent in the DMA buffer the DMA will push adata to the DATA register

EFP - X

Non-EFP

X X


SERCOM-I2C I2C Slave inDATA32B Mode

21812

When SERCOM is configured as an I2C slave in 32-bit DataMode (DATA32B=1) and the I2C master reads from the I2C slave(slave transmitter) and outputs its NACK (indicating no more datais needed) the I2C slave still receives a DRDY interrupt

EFP - X

Non-EFP

X X


SERCOM-I2C 10-bitAddressing Mode

21813 10-bit addressing in I2C Slave mode is not functional

EFP - X

Non-EFP

X X


SERCOM-I2C RepeatedStart

21814When the Quick command is enabled (CTRLBQCEN=1)software can issue a repeated Start by writing either CTRLBCMDor ADDRADDR bit fields

EFP - X

Non-EFP

X X


SERCOM-SPI DataPreload

21815

In SPI Slave mode and with Slave Data Preload Enabled(CTRLBPLOADEN=1) the first data sent from the slave will be adummy byte if the master cannot keep the Slave Select (SS) linelow until the end of transmission

EFP - X

Non-EFP

X X


Repeated Start 21816For Master Write operations (excluding High-Speed mode) in 10-bit addressing mode writing CTRLBCMD = 0x1 does not issuecorrectly a Repeated Start command

EFP - X

Non-EFP

X X


Wakeup 21817The USART does not wake-up the device on Error(INTFLAGERROR=1) interrupt

EFP - X

Non-EFP

X X



continued

Module FeatureItem

NumberIssue Summary

EFPNon-EFP

AffectedRevisions

A D


LENGTH 21818

When the USART is used in 32-bit mode with hardwarehandshaking (CTSRTS) the TXC interrupt flag (INTFLAGTXC)may be set before transmission has completed The TXC interruptflag may incorrectly be set regardless of Data Length Enable(LENGTHLENEN) is set to 0 or 1

EFP - X

Non-EFP

X X

Supply Controller(SUPC)

Buck Converter Mode 2191Digital Phase-Locked Loop (FDPLL200Mx2) and DigitalFrequency-Locked Loop (DFLL48M) PLLrsquos cannot be used withmain voltage regulator in Buck converter mode

EFP - X

Non-EFP

X X


BOD33 Hysteresis 2192The hysteresis feature of the 33V BOD is not functional while thedevice is in STANDBY sleep mode

EFP - X

Non-EFP

X X

TimerCounter (TC) PERBUFCCBUFx Register 2201When clearing the STATUSPERBUFVSTATUSCCBUFx flag theSYNCBUSY flag is released before the PERBUFCCBUFxregister is restored to its appropriate value

EFP - X

Non-EFP

X X

TimerCounter forControl Applications

(TCC)

TCC with EVSYS in SYNCRESYNC Mode

2211TCC peripheral is not compatible with an EVSYS channel inSYNC or RESYNC mode

EFP - X

Non-EFP

X X


(TCC)

Dithering Mode withExternal Retrigger Events

2212Using TCC in Dithering mode with external retrigger events canlead to an unexpected stretch of right aligned pulses or shrink ofleft-aligned pulses

EFP - X

Non-EFP

X X


(TCC)ALOCK Feature 2213 ALOCK feature is not functional

EFP - X

Non-EFP

X X


(TCC)

LUPD feature in Down-Counting mode

2214In down-counting mode the Lock Update bit (CTRLBLUPD) doesnot protect against a PER register update from the PERBUFregister

EFP - X

Non-EFP

X X

PDEC X2 Mode 2221In X2 mode if index signal generated from the motor sensor isstuck at 0 then position counter does not work correctly

EFP - X

Non-EFP

X X

Voltage ReferenceSystem

Temperature sensor 2231 Temperature sensors are not supported

EFP X X

Non-EFP

X X

Note bull Cells with lsquoXrsquo indicates the issue is present in this revision of the siliconbull Cells with lsquo-rsquo indicates this silicon revision does not exist for this issuebull The blank cell indicates the issue has been corrected or does not exist in this revision of the silicon



2 Silicon Errata IssuesThe following issues apply to the SAM D5xE5x Family of devices

Note Cells with an lsquoXrsquo indicates the issue is present in this revision of the silicon

Cells with a dash (lsquo-rsquo) indicate this silicon revision does not exist for this issue

Blank cells indicate the issue has been corrected or does not exist in this revision of the silicon

21 Analog-to-Digital Converter (ADC)

211 ADC SYNCBUSYSWTRIGThe ADC SYNCBUSYSWTRIG gets stuck to 1 after wake-up from Standby Sleep mode

WorkaroundIgnore the ADC SYNCBUSYSWTRIG status when waking up from Sleep mode

Affected Silicon Revisions

Device A D

EFP - X

Non-EFP X X

212 ADC TUEINLDNL PerformanceThe ADC TUEINLDNL performance is not guaranteed in the following scenarios

bull Sampling frequency is above 500 ksps ANDbull ADC VREF is different from VDDANA

WorkaroundNone


Device A D

EFP -

Non-EFP X

213 Reference Buffer Offset CompensationADC converted data could be erroneous when using the Reference Buffer (REFCTRLREFSEL = INTREF INTVCC0INTVCC1 VREFA or VREB) and when Reference Buffer Offset Compensation is enabled (REFCTRLREFCOMP =1)

WorkaroundThe first five conversions must be ignored All further ADC module conversions are accurate

SAM D5xE5x FamilySilicon Errata Issues



Device A D

EFP - X

Non-EFP X X

214 DMA SequencingADC DMA Sequencing with prescaler gt 8 (ADC-gtCTRLAbitPRESCALERgt2) does not produce the expectedchannel sequence

WorkaroundKeep the prescaler setting to a maximum of 8 and use the GCLK Generator divider if more prescaling is needed


Device A D

EFP - X

Non-EFP X X

215 DMA SequencingADC DMA sequencing with averaging enabled (AVGCTRLSAMPLENUMgt1) without the AVGCTRL bit set(DSEQCTRLAVGCTRL=0) in the update sequence does not produce the expected channel sequence

WorkaroundAdd the AVGCTRL register in the register update list (DSEQCTRLAVGCTRL=1) and set the desired value in this list


Device A D

EFP - X

Non-EFP X X

22 Analog Comparator (AC)

221 AC HysteresisEnabling Hysteresis (COMPCTRLnHYSTEN = 0x1) changes the threshold voltage (VTH-) which could result inunexpected behavior of the Analog Comparator

WorkaroundNone


Device A D

EFP - X

Non-EFP X X



222 OutputIn Continuous mode the comparator output may toggle during startup time before the Ready Status bit is set(STATUSBREADY = 1)

WorkaroundNone


Device A D

EFP - X

Non-EFP X X

23 Configurable Custom Logic (CCL)

231 Enable Protected RegistersThe SEQCTRLx and LUCTRLx registers are enable-protected by the CTRLENABLE bit whereas they must beenable-protected by the LUTCTRLxENABLE bits

WorkaroundNone


Device A D

EFP - X

Non-EFP X X

232 Sequential Logic ReferenceLUT Output is corrupted after enabling CCL when sequential logic is used

WorkaroundWrite the CTRL register twice when enabling the CCL


Device A D

EFP - X

Non-EFP X X

24 Controller Area Network (CAN)

241 CAN Edge FilteringWhen edge filtering is activated (CCCREFBI = 1) and when the end of the integration phase coincides with a fallingedge at the Rx input pin it may occur that the CAN synchronizes itself incorrectly and does not correctly receive thefirst bit of the frame In this case the CRC will detect the first bit that was received incorrectly it will rate the receivedFD frame as faulty and an error frame will be send



The issue only occurs when there is a falling edge at the Rx input pin (CAN_RX) within the last time quantum (tq)before the end of the integration phase The last time quantum of the integration phase is at the sample point of the11th recessive bit of the integration phase When edge filtering is enabled the bit timing logic of the CAN sees the Rxinput signal delayed by the edge filtering When the integration phase ends edge filtering is automatically disabledThis affects the reset of the FD CRC registers at the beginning of the frame The Classical CRC register is notaffected hence this issue does not affect the reception of Classical frames

In CAN communication the CAN module may enter an integrating state (either by resetting the CCCRINIT or byprotocol exception event) while a frame is active on the bus In this case the 11 recessive bits are counted betweenthe acknowledge bit and the following start of frame All nodes have synchronized at the beginning of the dominantacknowledge bit This means that the edge of the following start of frame bit cannot fall on the sample point hencethe issue does not occur The issue occurs only when the CAN is by local errors mis-synchronized with regard to theother nodes

Glitch filtering as specified in ISO 11898-12015 is fully functional

Edge filtering was introduced for applications where the data bit time is at least 2-tq (of nominal bit time) long In thatcase edge filtering requires at least two consecutive dominant time quanta before the counter counting the 11recessive bits for idle detection is restarted This means edge filtering covers the theoretical case of occasional 1-tqlong dominant spikes on the CAN bus that would delay idle detection Repeated dominant spikes on the CAN buswould disturb all CAN communication so the filtering to speed up idle detection would not help network performance

When this rare event occurs the CAN sends an error frame and the sender of the affected frame retransmits theframe When the retransmitted frame is received the CAN has left the integration phase and the frame will bereceived correctly Edge filtering is only applied during the integration phase and it is never used during normaloperation Because the integration phase is very short with respect to active communication time the impact ontotal error frame rate is negligible The issue has no impact on data integrity

The CAN enters the integration phase under the following conditionsbull When CCCRINIT is set to 0 after start-upbull After a protocol exception event (only when CCCRPXHD = 0)

Scope

The erratum is limited to FD frame reception when edge filtering is active (CCCREFBI = 1) and when the end of theintegration phase coincides with a falling edge at the Rx input pin

Effects

The calculated CRC value does not match the CRC value of the received FD frame and the CAN module sends anerror frame After retransmission the frame is received correctly

Workaround

Disable edge filtering or wait on retransmission in the event that this rare event occurs


Device A D

EFP - X

Non-EFP X X

242 Dominant Bit of IntermissionWhen NBTPNTSEG2 is configured to zero (Phase_Seg2(N) = 1) and when there is a pending transmission requesta dominant third bit of intermission may cause the CAN to wrongly transmit the first identifier bit dominant instead ofrecessive even if this bit was configured as 1 in the Tx Buffer Element of the CAN module

WorkaroundA phase buffer segment 2 of length 1 (Phase_Seg2(N) = 1) is not sufficient to switch to the first identifier bit after thesample point in intermission where the dominant bit was detected



The CAN protocol according to ISO 11898-1 defines that a dominant third bit of intermission causes a pendingtransmission to be started immediately The received dominant bit is handled as if the CAN has transmitted a Start-of-Frame (SoF) bit

The ISO 11898-1 specifies the minimum configuration range for Phase_Seg2(N) to be 28 tq Therefore excluding aPhase_Seg2(N) of 1 will not affect CAN conformance

Effects

If NBTPNTSEG2 = 0 it may occur that the CAN transmits the first identifier bit dominant instead of recessive

Update configuration range of NBTPNTSEG2 from 0127 tq to 1127 tq in the CAN documentation


Device A D

EFP - X

Non-EFP X X

243 Message Transmitted with Wrong Arbitration and Control FieldsDescription

Under the following conditions a message with wrong ID format and DLC is transmitted

bull The CAN is in the Receiver (PSRACT ne0b10) state hence no pending transmissionbull A new transmission is requested before the third bit of intermission is reachedbull The CAN bus is sampled dominant at the third bit of intermission which is treated as SoF (See

ISO11898-12015 ldquoSection 10422rdquo)

Under the conditions above the following might happen

bull The shift register is not loaded with ID format and DLC of the requested messagebull The CAN will start arbitration with wrong ID format and DLC on the next bitbull If the ID wins arbitration a CAN message with a valid CRC is transmittedbull If this message is acknowledged the ID stored in the Tx event FIFO is the ID of the requested Tx message and

not the ID of the message transmitted on the CAN bus hence no error is detected by the transmitting CAN

Scope

The erratum is limited when CAN is in the Receiver (PSRACT = 0b10) state with no pending transmission (registerTXBRP == 0) and a new transmission is requested before the third bit of intermission is reached and this third bit ofintermission is seen dominant

When a transmission is requested by the CPU by writing to TXBAR the Tx message handler performs an internalarbitration and loads the pending transmit message with the highest priority into its output buffer and then sets thetransmission request for the CAN Protocol Controller The problem occurs only when the transmission request for theCAN Protocol Controller is activated in the critical time window between the sample points of the second and third bitof intermission and if that third bit of intermission is seen dominant

This dominant level at the third bit of intermission may result from an external disturbance or may be transmitted byanother node with a significantly faster clock

Effects

In the described case it may happen that the shift register is not loaded with arbitration and control field of themessage to be transmitted The frame is transmitted with wrong ID format and DLC but with the data field of therequested message The message is transmitted in correct CAN (FD) frame format with a valid CRC

If the message loses arbitration or is disturbed by an error it is retransmitted with correct arbitration and control fields

Workaroundsbull Workaround 1 Request a new transmission only if another transmission is already pending (that is register

TXBRP ne 0) or when the CAN is not in the Receiver (when PSRACT ne 0b10) state To avoid activating the



transmission request in the critical time window between the sample points of the second and third bit ofintermission the application software can evaluate the Rx interrupt flags such as IRDRX IRRF0N andIRRF1N which are set at the last bit of EoF when a received and accepted message becomes valid The lastbit of EoF is followed by third bits of intermission Therefore the critical time window has safely terminated threebit times after the Rx interrupt Now a transmission may be requested by writing to TXBAR After the interruptthe application has to take care that the transmission request for the CAN Protocol Controller is activated beforethe critical window of the following reception is reached

bull Workaround 2 If a transmission is to be requested while no other transmission request is already pending andthe CAN bus is not idle set the CCCRINIT bit (which stops the CAN protocol controller) set the transmissionrequest and clear the CCCRINIT bit The message currently being received when the CCCRINIT bit is set willbe lost but no errors (or error frames) will be generated and the CAN protocol controller will re-integrate into theCAN communication immediately at the 11 recessive bits of the next End-of-Frame including intermission

bull Workaround 3It is also possible to keep the number of pending transmissions always at gt 0 by frequentlyrequesting a message then the condition no pending transmission is never met The frequently requestedmessage may be given a low priority losing arbitration to all other messages


Device A D

EFP - X

Non-EFP X X

244 DAR ModeWhen the CAN is configured in DAR mode (CCCRDAR = 1) the automatic retransmission for transmitted messagesthat have been disturbed by an error or have lost arbitration is disabled When the transmission attempt is notsuccessful the Tx Bufferrsquos Transmission Request bit (TXBRPTRPn) will be cleared and the Tx Bufferrsquos CancellationFinished bit (TXBCFCFn) will be set

When the transmitted message loses arbitration at one of the first two identifier bits chances are that instead of thebits of the actually transmitted Tx Buffer the TXBRPTRPn and TXBCFCFn bits of the previously started Tx Buffer (orTx Buffer 0 if there is no previous transmission attempt) are written (TXBRPTRPn = 0 TXBCFCFn = 1)

If in this case the TXBRPTRPn bit of the Tx Buffer that lost arbitration at the first two identifier bits are not clearedretransmission is attempted When the CAN loses arbitration again at the immediately following retransmission thenactually and previously transmitted Tx Buffer are the same and this Tx Bufferrsquos TXBRPTRPn bit is cleared and itsTXBCFCFn bit is set

Scope

The erratum is limited to the case when the CAN loses arbitration at one of the first two transmitted identifier bitswhile in DAR mode The problem does not occur when the transmitted message is disturbed by an error

Effects

In this case it might happen that the TXBRPTRPn bit is cleared after the second transmission attempt instead of thefirst Additionally it may happen that the TXBRPTRPn bit of the previously started Tx Buffer is cleared if it has beenset again As in this case the previously started Tx Buffer has lost CAN internal arbitration against the active TxBuffer its message has a lower identifier priority It would also have lost arbitration on the CAN bus at the sameposition

WorkaroundNone


Device A D

EFP - X



continuedDevice A D

Non-EFP X X

245 High-Priority Message (HPM) interruptThere are two configurations where the issue occurs

Configuration A

bull At least one Standard Message ID Filter Element is configured with priority flag set (S0SFEC =0b1000b1010b110)

bull No Extended Message ID Filter Element configuredbull Non-matching extended frames are accepted (GFCANFE = 0b000b01)

The HPM interrupt flag IRHPM is set erroneously on reception of a non-high-priority extended message under thefollowing conditions

1 A standard HPM frame is received and accepted by a filter with priority flag set (that is Interrupt flag IRHPM isset as expected)

2 An extended frame is received and accepted because of the GFCANFE configuration (that is Interrupt flagIRHPM is set erroneously)

Configuration B

bull At least one Extended Message ID filter element is configured with priority flag set (F0EFEC =0b1000b1010b110)

bull No Standard Message ID filter element is configuredbull Non matching standard frames are accepted (GFCANFS = 0b000b01)

The HPM interrupt flag IRHPM is set erroneously on reception of a non high-priority standard message under thefollowing conditions

1 An extended HPM frame is received and accepted by a filter with priority flag set (that is Interrupt flag IRHPMis set as expected)

2 A standard frame is received and accepted because of the GFCANFS configuration (that is Interrupt flagIRHPM is set erroneously)

Scope

The erratum is limited to the following configurations

Configuration A

No Extended Message ID filter element is configured and non matching extended frames are accepted due to GlobalFilter Configuration (GFCANFE = 0b000b01)

Configuration B

No Standard Message ID Filter Element configured and non-matching standard frames are accepted due to GlobalFilter Configuration (GFCANFS = 0b000b01)

Effects

Interrupt flag IRHPM is set erroneously at the reception of a frame with

bull Configuration A Extended Message IDbull Configuration B Standard Message ID

WorkaroundConfiguration A

Setup an Extended Message ID filter element with the following configuration

bull F0EFEC = 001010 Select Rx FIFO for storage of extended framesbull F0EFID1 = any value The value is not relevant as all ID bits are masked out by F1EFID2



bull F1EFT = 10 Classic filter F0EFID1 = filter F1EFID2 = maskbull F1EFID2 = 0 All bits of the received extended ID are masked out

Now all extended frames are stored in Rx FIFO lsquo0rsquo or Rx FIFO lsquo1rsquo depending on the configuration of F0EFEC

Configuration B

Setup an Standard Message ID filter element with the following configuration

bull S0SFEC = 001010 Select Rx FIFO for storage of standard framesbull S0SFID1 = any value The value is not relevant as all ID bits are masked out by S0SFID2bull S0SFT = 10 Classic filter S0SFID1 = filter S0SFID2 = maskbull S0SFID2 = 0 All bits of the received standard ID are masked out

Now all standard frames are stored in Rx FIFO lsquo0rsquo or Rx FIFO lsquo1rsquo depending on the configuration of S0SFEC


Device A D

EFP - X

Non-EFP X X

246 Tx FIFO message sequence inversionAssuming that there are two Tx FIFO messages in the output pipeline of the Tx Message Handler Transmission of TxFIFO message 1 is started

Position 1 Tx FIFO message 1 (transmission ongoing)

Position 2 Tx FIFO message 2

Position 3 Free FIFO bugger

During the transmission of Tx FIFO message 1 a non Tx FIFO message with a higher CAN priority is requested Dueto its priority it will be inserted into the output pipeline The TxMH performs message scans to keep the outputpipeline up to date with the highest priority messages from the message RAM

After the following two message scans the output pipeline has the following content


Position 2 non Tx FIFO message with higher CAN priority


If the transmission of Tx FIFO message 1 is not successful (lost arbitration or CAN bus error) it is pushed from theoutput pipeline by the non Tx FIFO message with higher CAN priority The following scan again inserts Tx FIFOmessage 1 into the output pipeline at position 3

Position 1 non Tx FIFO message with higher CAN priority (transmission ongoing)



This results in Tx FIFO message 2 being in the output pipeline in front of Tx FIFO message 1 and they aretransmitted in that order resulting in a message sequence inversion

Scope

The erratum describes the case when the CAN uses both dedicated Tx Buffers and a Tx FIFO (TXBCTFQM = 0)and the messages in the Tx FIFO do not have the highest internal CAN priority The described sequence inversionmay also happen between two non Tx FIFO messages (Tx Queue or dedicated Tx Buffers) that have the same CANidentifier and that should be transmitted in the order of their buffer numbers (not the intended use)

Effects



In the described case it may happen that two consecutive messages from the Tx FIFO exchange their positions in thetransmit sequence

WorkaroundsWhen transmitting messages from a dedicated Tx Buffer with higher priority than the messages in the Tx FIFOchoose one of the following workarounds

Workaround 1

Use two dedicated Tx Buffers for example use Tx Buffers 4 and 5 instead of the Tx FIFO

The Transmit Loop below replaces the function that fills the Tx FIFO

Write the message to Tx Buffer 4

Transmit Loop

bull Request Tx Buffer 4 - write TXBARA4bull Write message to Tx Buffer 5bull Wait until transmission of Tx Buffer 4 completed - IRTC read TXBTOTO4bull Request Tx Buffer 5 - write TXBARA5bull Write message to Tx Buffer 4bull Wait until transmission of Tx Buffer 5 completed - IRTC read TXBTOTO5

Workaround 2

Ensure that only one Tx FIFO element is pending for transmission at any time

The Tx FIFO elements may be filled at any time with messages to be transmitted but their transmission requests arehandled separately Each time a Tx FIFO transmission has completed and the Tx FIFO becomes empty (IRTFE = 1)the next Tx FIFO element is requested

Workaround 3

Use only a Tx FIFO Send the message with the higher priority also from Tx FIFO

Drawback The higher priority message has to wait until the preceding messages in the Tx FIFO are sent


Device A D

EFP - X

Non-EFP X X

25 Clock Failure Detector (CFD)

251 CFD with XOSCXOSC32K OscillatorWhen the CFD is enabled for the XOSCXOSC32K oscillator and the oscillator input signal is stuck at 1 the clockfailure detection works correctly but the switch to the safe clock will fail

WorkaroundTwo possible workarounds are as follows

1 If the main clock source comes from the XOSCXOSC32K oscillator the only workaround is indirect (ie usingthe WDT in firmware and switch to safe clock source in firmware at WDT reset)

2 Because the clock failure detection is functional once the STATUSCLKFAIL is set and if theSTATUSCLKSW is not set manually switch to safe clock from firmware by changing the configurations of theGeneric Clock Generators that use the XOSCXOSC32K oscillator as a clock source to use another sourceclock instead




Device A D

EFP -

Non-EFP X

26 Device

261 Reverse Current in VDDIOB DomainFor the device with 100-pin 120-pin and 128-pin counts when VDDIOB is supplied with the voltage less thanVDDIO - 07V reverse current in VDDIOB cluster is observed

WorkaroundNone Pin PB13 must be tied to ground


Device A D

EFP -

Non-EFP X

262 Internal Pull-up on the RESET PinThe internal pull-up of the RESET pin is not functional

WorkaroundAn external 100K pull-up must be added on the RESET pin


Device A D

EFP -

Non-EFP X

263 Detection of a Debugger ProbeThe detection of a debugger probe could fail if the BOD33 Disable fuse is cleared (ie BOD33 is enabled)

WorkaroundTo secure the detection of debugger probes enable BOD33 using the SUPCBOD33 register instead of the BOD33Disable fuse The BOD33 Disable fuse must be kept set


Device A D

EFP - X

Non-EFP X X

264 VBAT ModeVBAT mode is not functional



WorkaroundNone


Device A D

EFP -

Non-EFP X

265 Internal ReferenceWhen the internal reference is used with the DAC and ADC their outputs become non-linear when the operatingtemperature is less than 0degC

WorkaroundThe internal reference must be used only for positive temperatures (ie above 0degC)


Device A D

EFP -

Non-EFP X

266 Device Operation for Temperature lt -20degCIf the operating temperature is less than -20degC the device does not start This erratum only applies to Revision Asilicon (all temperature grades) and Revision D silicon (85degC temperature grade)

WorkaroundFor non-EFP devices apply an external reset pulse at power-up when VDD is higher than 2V or keep reset line lowuntil VDD is lower than 2V


Device A D

EFP -

Non-EFP X X

27 Device Service Unit (DSU)

271 CRC32The DSU CRC32 will not complete when targeting NVM memory space while the NVM cache is disabled

WorkaroundBe sure to always enable the NVM cache when performing a DSU CRC32 request targeting the NVM memory space


Device A D

EFP - X

Non-EFP X X



28 48 MHz Digital Frequency-Locked Loop (DFLL48M)

281 COARSE or FINE Calibration Values During the Locking SequenceIf the DFLL48M reaches the maximum or minimum COARSE or FINE calibration values during the locking sequencean out of bounds interrupt will be generated These interrupts will be generated even if the final calibration values atDFLL48M lock are not at maximum or minimum and might therefore be false out of bounds interrupts

WorkaroundCheck that lock bits DFLLLCKC and DFLLLCKF in the OSCCTRL Interrupt Flag Status and Clear register(INTFLAG) are both set before enabling the DFLLOOB interrupt


Device A D

EFP - X

Non-EFP X X

282 STATUSDFLLRDY Bit in Close Loop ModeIn Close Loop mode the STATUSDFLLRDY bit does not rise before lock fine occurs Therefore the informationabout DFLL ready to start Close Loop mode is not available

WorkaroundNone


Device A D

EFP - X

Non-EFP X X

283 DFLLVALFINE Value When DFLL48M Re-enabledIf the DFLL is disabled and then re-enabled the DFLLVALFINE value is ignored by the DFLL module which will thenstart its lock fine process at another frequency

WorkaroundBefore writing the final configuration in the DFLLCTRLB register the DFLL module must be re-enabled in Open Loopmode to read and rewrite the DFLLVAL register

1 OSCCTRL-gtDFLLMULreg = X Write new DFLLMULL configuration2 OSCCTRLDFLLCTRLBreg = 0 Select Open loop configuration3 OSCCTRLDFLLCTRLAbitENABLE = 1 Enable DFLL4 OSCCTRLDFLLVALreg = OSCCTRL-gtDFLLVALreg Reload DFLLVAL register5 OSCCTRLDFLLCTRLBreg = X Write final DFLL configuration


Device A D

EFP -

Non-EFP X



284 LLAWWhen the Lose Lock After Wake (LLAW) is set the DFLL may maintain lock (STATTUSDFLLLOCK = 1) after theDFLL is disabled If the DFLL lock (STATUSDFLLLOCK = 1) is maintained when the DFLL is reconfigured and thenenabled some bits may not be properly set

WorkaroundWhen reconfiguring the DFLL wait for the lock status to set to lsquo0rsquo (STATUSDFLLLOCK = 0) after disabling the DFLL(DFLLCTRLAENABLE = 0)


Device A D

EFP - X

Non-EFP X X

29 Digital-to-Analog Converter (DAC)

291 Smoothing of the Output Signal in differential ModeIn Differential mode the smoothing of the output signal is not fully functional Smoothing works normally in Differentialmode as long as the value of two consecutive data are both positive or negative The behavior is incorrect when thedata changes from positive to negative or vice versa

WorkaroundNone


Device A D

EFP - X

Non-EFP X X

292 VDDANA as the DAC ReferenceThe selection of VDDANA as the DAC reference in DACCTRLBREFSEL is non-functional

WorkaroundThe VDDANA must be connected externally to a VREF pin and DACCTRLBVREFAU must be selected


Device A D

EFP -

Non-EFP X

293 DAC on Negative Input AIN3No analog compare will be done on Comparator 1 (AC1) when using the DAC on negative input AIN3

WorkaroundUse the internal VDD scaler




Device A D

EFP -

Non-EFP X

294 Interpolation ModeIf the Interpolation mode is enabled (with filter integrated to the DAC) the last data from the filter is missing andtherefore the DAC final output value does not correspond to the DAC input value

Although interrupt events are generated at the end of conversion (EOC) the EOC occurs before the final value fromthe filter and is of no use in the application

WorkaroundNone


Device A D

EFP - X

Non-EFP X X

295 ReferenceThe reference select of the DAC (CTRLBREFSEL) will default to a lsquo0rsquo if the DAC Software Reset (CTRLASWRST) isused to reset the module

WorkaroundNone


Device A D

EFP - X

Non-EFP X X

210 Direct Memory Access Controller (DMAC)

2101 Linked DescriptorsWhen at least one channel using linked descriptors is already active a channel Fetch Error (FERR) could occur onenabling a channel with no linked descriptor or the second descriptor (index 1) of the channel being enabled could befetched by one of the already active channels using linked descriptors These errors can occur when a channel isbeing enabled during the link request of another channel and if the channel number of the channel being enabled islower than the channel already active

WorkaroundWhen enabling a channel while other channels using linked descriptors are already active the channel number of thenew channel to enable must be greater than the other channel numbers




Device A D

EFP - X

Non-EFP X X

2102 Channel PriorityWhen using channels with different priority levels the highest priority channel could stall at the end of its currentblock

When this occurs the channel is seen as active with BTCNT = 0 in the ACTIVE register with Busy and Pending flagset in the CHSTATUSn register This condition also prevents the other channels from executing

WorkaroundNone


Device A D

EFP -

Non-EFP X

2103 DMAC in Debug ModeIn Debug mode DMAC does not restart after a debug halt when DBGCTRLDBGRUN = 0

WorkaroundSet DBGCTRLDBGRUN to 1 so that the DMAC continues normal operation when the CPU is halted by an externaldebugger


Device A D

EFP -

Non-EFP X

211 Ethernet MAC (GMAC)

2111 Ethernet Functionality in 64-pin PackagesEthernet functionality in 64-pin packages is not available

WorkaroundNone


Device A D

EFP -

Non-EFP X



212 External Interrupt Controller (EIC)

2121 Edge DetectionWhen enabling EIC SYNCBUSYENABLE is released before EIC is fully enabled Edge detection can be done onlyafter three cycles of the selected GCLK (GCLK_EIC or CLK_ULP32K)

WorkaroundNone


Device A D

EFP - X

Non-EFP X X

2122 Asynchronous Edge DetectionWhen the asynchronous edge detection is enabled and the system is in Standby mode only the first edge will bedetected The following edges are ignored until the system wakes up

WorkaroundUse the asynchronous edge detection with debouncer enabled It is recommended to set theDPRESCALERPRESCALER and DPRESCALERTICKON to have the lowest frequency possible To reduce thepower consumption set the EIC GCLK frequency as low as possible or select the ULP32K clock (EIC CTRLACKSELset)


Device A D

EFP - X

Non-EFP X X

213 Fractional Digital Phase-Locked Loop (FDPLL)

2131 Low-Frequency Input Clock on FDPLLnWhen using a low frequency input clock (le 400 kHz) for input to FDPLLn several FDPLL false unlock statusindications may occur while the FDPLL output frequency is actually stable

WorkaroundWhen using a low frequency input clock (le 400 kHz) on FDPLLn enable the lock bypass(OSCCTRLDPLLCTRLBLBYPASS = 1) and wake up fast (OSCCTRLDPLLCTRLBWUF = 1) to avoid losing FDPLLclock output during a false unlock status The workaround does not avoid false unlock indications but it disables thegating of the FDPLL clock output by the lock status therefore the clock is issued even if the FDPLL status showsunlocked The Clock Ready bit (OSCCTRLDPLLSTATUSCLKRDY) can be monitored by the application to ensureactivity is present on the FDPLLn output but clock ready does not provide any indication of FDPLLn Lock orfrequency A 10 ms delay is also suggested after the clock ready bit is set to allow the DPLL to achieve the targetfrequency

Pseudo Code

Set OSCCTRLDPLLCTRLBWUF = 1 and OSCCTRLDPLLCTRLBLBYPASS = 1

Set DPLLCTRLAENABLE = 1



Wait (OSCCTRLDPLLSTATUSCLKRDY==1)

Delay (10ms)

Set Source for GCLK with DPLL


Device A D

EFP - X

Non-EFP X X

2132 FDPLL Ratio in DPLLnRATIOWhen changing the FDPLL ratio in DPLLnRATIO register on-the-fly STATUSDPLLnLDRTO will not be set when theratio update will be completed

WorkaroundWait for the interruption flag INTFLAGDPLLnLDRTO instead


Device A D

EFP - X

Non-EFP X X

214 Non-Volatile Memory Controller (NVMCTRL)

2141 NVM Read CorruptionNVM reads could be corrupted when mixing NVM reads with Page Buffer writes

WorkaroundDisable cache lines before writing to the Page Buffer when executing from NVM or reading data from NVM whilewriting to the Page Buffer Cache lines are disabled by writing a one to CTRLACACHEDIS0 andCTRLACACHEDIS1


Device A D

EFP - X

Non-EFP X X

215 Peripheral Access Controller (PAC)

2151 PAC Protection Error in FREQMFREQM reads on the Control B register (FREQMCTRLB) generate a PAC protection error

WorkaroundNone




Device A D

EFP - X

Non-EFP X X

2152 PAC Protection Error in CCLWriting the Software Reset bit in the Control A register (CTRLASWRST) will trigger a PAC protection error

WorkaroundClear the CCL PAC error each time a CCL software reset is executed


Device A D

EFP - X

Non-EFP X X

216 IO Pin Controller (PORT)

2161 PORT ReadWrite Attempts on Non-Implemented RegistersPORT readwrite attempts on non-implemented registers including addresses beyond the last implemented registergroup (PA PB) do not generate a PAC protection error

WorkaroundNone


Device A D

EFP - X

Non-EFP X X

2162 PORT Pull-UpPull-Down ResistorThe pull-down on PA24PA25 are activated during power-up and when Sleep mode is OFF On all other pins exceptthose in the VSWOUT cluster the pull-up is activated during power-up and when Sleep mode is OFF

WorkaroundNone


Device A D

EFP -

Non-EFP X



217 Real-Time Counter (RTC)

2171 Write CorruptionA 8-bit or 16-bit write access for a 32-bit register or 8-bit write access for a 16-bit register can fail for the followingregisters

bull COUNT register in COUNT32 modebull COUNT register in COUNT16 modebull CLOCK register in CLOCK mode

WorkaroundWrite the registers with

bull A 32-bit write access for COUNT register in COUNT32 mode CLOCK register in CLOCK modebull A 16-bit write access for the COUNT register in COUNT16 mode


Device A D

EFP - X

Non-EFP X X

2172 COUNTSYNCWhen COUNTSYNC is enabled the first COUNT value is not correctly synchronized and thus it is a wrong value

WorkaroundAfter enabling COUNTSYNC read the COUNT register until its value is changed when compared to its first valueread After this all consequent value read from the COUNT register is valid


Device A D

EFP - X

Non-EFP X X

2173 Tamper Input FilterMajority debouncing as part of RTC tamper detection does not work when enabled by setting the DebouncerMajority Enable bit CTRLBDEBMAJ

WorkaroundNone


Device A D

EFP - X

Non-EFP X X

2174 Tamper DetectionUpon enabling the RTC tamper detection feature a false tamper detection can be reported by the RTC



WorkaroundsUse any one of the following workarounds

bull Workaround 1 Configure TAMPER detection as ONLY falling edgebull Workaround 2 If the user software has to use TAMPER detection as rising edge it must ignore the first tamper

interrupt generated immediately after enabling the RTC tamper detection


Device A D

EFP - X

Non-EFP X X

2175 Tamper Detection TimestampIf an external reset occurs during a tamper detection the TIMESTAMP register will not be updated when next tamperdetection is triggered

WorkaroundsEnable RTC tamper interrupt and copy the timestamp from the RTC CLOCK register to one of the followingdestinations

bull SRAMbull GPx register in RTCbull BKUPx register in RTC


Device A D

EFP - X

Non-EFP X X

2176 PrescalerWhen the tamper or debouncing features (TAMPCTRL) are enabled periodic interrupts and events are generatedwhen the prescaler is OFF (CTRLAPRESCALER=0)

WorkaroundsWhen the prescaler is OFF (CTRLAPRESCALER=0) clear the Periodic Interval n Event Output Enable bits(EVCTRLPEREOn=0 [n = 70]) and respective Periodic Interval n Interrupt Enable (INTENCLRPERn=1 [n = 70])bits


Device A D

EFP - X

Non-EFP X X

218 Serial Communication Interface (SERCOM)

2181 SERCOM-USART Auto-Baud ModeIn USART Auto-Baud mode missing stop bits are not recognized as inconsistent sync (ISF) or framing (FERR)errors



WorkaroundNone


Device A D

EFP - X

Non-EFP X X

2182 SERCOM-USART Collision DetectionIn USART operating mode with Collision Detection enabled (CTRLBCOLDEN = 1) the SERCOM will not abort thecurrent transfer as expected if a collision is detected and if the SERCOM APB Clock is lower than the SERCOMGeneric Clock

WorkaroundThe SERCOM APB clock must always be higher than the SERCOM Generic Clock to support collision detection


Device A D

EFP - X

Non-EFP X X

2183 SERCOM-USART Debug ModeIn USART operating mode if DBGCTRLDBGSTOP = 1 data transmission is not halted after entering Debug mode

WorkaroundNone


Device A D

EFP - X

Non-EFP X X

2184 SERCOM-USART 32-bit Extension ModeWhen 32-bit Extension mode is enabled and data to be sent is not in multiples of 4 bytes which means the lengthcounter must be enabled and additional bytes will be sent over the line


1 Write the Inter-Character Spacing bits (CTRLCICSPACE) to a non-zero-value2 Do not use length counter in firmware by keeping the data to be sent is in multiples of 4 bytes


Device A D

EFP - X

Non-EFP X X



2185 SERCOM-UART TXINV and RXINV BitsThe TXINV and RXINV bits in the CTRLA register have inverted functionality

WorkaroundIn software interpret the TXINV bit as a functionality of RXINV and conversely interpret the RXINV bit as afunctionality of TXINV


Device A D

EFP - X

Non-EFP X X

2186 SERCOM-I2C SDAHOLD TimingSDAHOLD timing of the SERCOM-I2C does not match the value shown in the current device data sheet Thefollowing table shows the specified and real values of SDA Hold timing

Table 2-1 SDA Hold Timing

SDA Hold Time Value Specified SDA Hold Time Real SDA Hold Time

0x0 Disabled Disabled

0x1 50 ns to 100 ns 20 ns to 40 ns

0x2 300 ns to 600 ns 100 ns to 250 ns

0x3 400 ns to 800 ns 150 ns to 350 ns

WorkaroundNone


Device A D

EFP - X

Non-EFP X X

2187 Repeated Start in High-Speed Master Write OperationFor High-Speed Master Write operations writing CTRLBCMD = 0x1 issues a STOP command instead of a RepeatedStart making repeated start not possible in that mode

WorkaroundNone


Device A D

EFP - X

Non-EFP X X

2188 Repeated Start in High-Speed Master Read OperationFor High-Speed Master Read operations sending a NACK (CTRLBCMD = 0x2) forces a STOP to be issued makingrepeated start not possible in that mode



WorkaroundNone


Device A D

EFP - X

Non-EFP X X

2189 STATUSCLKHOLD Bit in Master and Slave ModesThe STATUSCLKHOLD bit in master and slave modes can be written whereas it is a read-only status bit

WorkaroundDo not clear STATUSCLKHOLD bit to preserve the current clock hold state


Device A D

EFP - X

Non-EFP X X

21810 SERCOM-I2C I2C in Slave ModeIn I2C mode LENERR SEXTOUT LOWTOUT COLL and BUSERR bits are not cleared when INTFLAGAMATCH iscleared

WorkaroundManually clear status bits LENERR SEXTOUT LOWTOUT COLL and BUSERR by writing these bits to 1 when set


Device A D

EFP - X

Non-EFP X X

21811 SERCOM-I2C Slave Mode with DMAIn I2C Slave Transmitter mode at the reception of a NACK if there is still data to be sent in the DMA buffer the DMAwill push a data to the DATA register Because a NACK was received the transfer on the I 2C bus will not occurcausing the loss of this data

WorkaroundConfigure the DMA transfer size to the number of data to be received by the I2C master DMA cannot be used if thenumber of data to be received by the master is not known


Device A D

EFP - X

Non-EFP X X



21812 SERCOM-I2C I2C Slave in DATA32B ModeWhen SERCOM is configured as an I2C slave in 32-bit Data Mode (DATA32B = 1) and the I2C master reads from theI2C slave (slave transmitter) and outputs its NACK (indicating no more data is needed) the I2C slave still receives aDRDY interrupt

If the CPU does not write a new data to the I2C slave DATA register I2C slave will pull SDA line which will result installing the bus permanently

Workarounds1 Write a dummy data to data register when a NACK is received from the master2 Use command 2 (SERCOMx-gtI2CSCTRLBbitCMD = 2) when a NACK is received from the master

Important Because STATUSRXNACK always indicates the last received ACK to determine when aNACK is received from the I2C master the I2C slave software needs to consider I2CSSTATUSRXNACKonly on the second DRDY interrupt after receiving the AMATCH interrupt


Device A D

EFP - X

Non-EFP X X

21813 SERCOM-I2C 10-bit Addressing Mode10-bit addressing in I2C Slave mode is not functional

WorkaroundNone


Device A D

EFP - X

Non-EFP X X

21814 SERCOM-I2C Repeated StartWhen the Quick command is enabled (CTRLBQCEN = 1) software can issue a repeated Start by writing eitherCTRLBCMD or ADDRADDR bit fields If in these conditions SCL Stretch Mode is CTRLASCLSM = 1 a bus errorwill be generated

WorkaroundUse Quick Command mode (CTRLBQCEN = 1) only if SCL Stretch Mode is CTRLASCLSM = 0


Device A D

EFP - X

Non-EFP X X



21815 SERCOM-SPI Data PreloadIn SPI Slave mode and with Slave Data Preload Enabled (CTRLBPLOADEN = 1) the first data sent from the slavewill be a dummy byte if the master cannot keep the Slave Select (SS) line low until the end of transmission

WorkaroundsIn SPI Slave mode the Slave Select pin (SS) must be kept low by the master until the end of the transmission if theSlave Data Preload feature is used (CTRLBPLOADEN = 1)


Device A D

EFP - X

Non-EFP X X

21816 SERCOM I2C Repeated StartFor Master Write operations (excluding High-Speed mode) in 10-bit addressing mode writing CTRLBCMD = 0x1does not issue a Repeated Start command correctly

WorkaroundsWrite the same 10-bit address with the same direction bit to the ADDRADDR register to generate properly aRepeated Start


Device A D

EFP - X

Non-EFP X X

21817 WakeupThe USART does not wake-up the device on Error Interrupt (INTFLAGERROR=1)

WorkaroundsConfigure the USART to wake-up the device on the RX Complete Interrupt (INTENSETRXC=1) in order to check thePERRFERR status (STATUSPERR=1 or STATUSFERR=1)


Device A D

EFP - X

Non-EFP X X

21818 LENGTHWhen the USART is used in 32-bit mode with hardware handshaking (CTSRTS) the TXC interrupt flag(INTFLAGTXC) may be set before transmission has completed The TXC interrupt flag may incorrectly be setregardless of Data Length Enable (LENGTHLENEN) is set to 0 or 1

WorkaroundsNone




Device A D

EFP - X

Non-EFP X X

219 Supply Controller (SUPC)

2191 Buck Converter ModeBuck Converter mode is not supported when using PLLs As a result the information given in Table 54-9 ldquoActiveCurrent Consumption - Active Moderdquo data for Buck converter mode with FDPLL and DFLL configurations is not validand must be disregarded

WorkaroundUse the LDO Regulator mode when using FDPLL and DFLL configurations


Device A D

EFP - X

Non-EFP X X

2192 BOD33 HysteresisThe hysteresis feature of the 33V BOD is not functional while the device is in STANDBY sleep mode

WorkaroundNone


Device A D

EFP - X

Non-EFP X X

220 TimerCounter (TC)

2201 PERBUFCCBUFx RegisterWhen clearing the STATUSPERBUFVSTATUSCCBUFx flag the SYNCBUSY flag is released before the PERBUFCCBUFx register is restored to its appropriate value

WorkaroundClear successively twice the STATUSPERBUFVSTATUSCCBUFx flag to ensure that the PERBUFCCBUFxregister value is restored before updating it




Device A D

EFP - X

Non-EFP X X

221 TimerCounter for Control Applications (TCC)

2211 TCC with EVSYS in SYNCRESYNC ModeTCC peripheral is not compatible with an EVSYS channel in SYNC or RESYNC mode

WorkaroundUse TCC with an EVSYS channel in ASYNC mode


Device A D

EFP - X

Non-EFP X X

2212 Dithering Mode with External Retrigger EventsUsing TCC in Dithering mode with external retrigger events can lead to an unexpected stretch of right-aligned pulsesor shrink of left-aligned pulses

WorkaroundDo not use retrigger events or actions when the TCC module is configured in Dithering mode


Device A D

EFP - X

Non-EFP X X

2213 ALOCK FeatureALOCK feature is not functional

WorkaroundNone


Device A D

EFP - X

Non-EFP X X

2214 LUPD feature in Down-Counting ModeIn down-counting mode the Lock Update bit (CTRLBLUPD) does not protect against a PER register update from thePERBUF register



WorkaroundNone


Device A D

EFP - X

Non-EFP X X

222 Position Decoder (PDEC)

2221 X2 ModeIn X2 mode if the index signal generated from the motor sensor is stuck at 0 then the position counter increments by512 counts instead of 1 on every positive edge of the Count signal that is the PDEC peripheral counter presentsincorrect counts when used with position sensor with faulty (stuck at 0) index signal

WorkaroundNone


Device A D

EFP - X

Non-EFP X X

223 Voltage Reference System

2231 Temperature SensorBoth internal temperature sensors TSENSP and TSENSC are not supported and should not be used

WorkaroundNone


Device A D

EFP X X

Non-EFP X X



3 Data Sheet ClarificationsThe following typographic corrections and clarifications are to be noted for the device data sheet (DS60001507E)and are showed in BOLD type

DAC - 85degCTable 54-29 in the ldquoElectrical Characteristics at 85degCrdquo chapter has an incorrect value for the DNL the corrected valueis listed in the table below

Table 3-1 Differential Mode

Symbol Parameters Conditions Min Typ Max Unit

DNL Differential Non LinearityBest-fit curve from 0x080 to 0xF7F

i12clk = 12 MHz VDDANA = 30V External Ref = 20V CLOAD= 50 pF

- plusmn24 plusmn36 LSB

i12clk = 12 MHz VDDANA = 30V Internal Ref CLOAD = 50 pF - plusmn35 plusmn54

Table 54-30 listed an incorrect value for INL maximum output the corrected value is listed in the table below

Table 3-2 Single-Ended Mode


INL Integral Non LinearityBest-fit curve from 0x080 to 0xF7F



i12clk = 12 MHz VDDANA = 30V Internal Ref CLOAD = 50 pF - plusmn52 82

DAC - 105degCTable 55-12 displays an incorrect maximum value for DNL The corrected value is listed in the table below



DNL Differential Non Linearity Best Fit curve from 0x080 to 0xF7F

i12clk =12 MHzVDDANA = 30V External Ref = 20V

Cload = 50 pF- plusmn24 plusmn36

LSBi12clk = 12 MHz

VDDANA = 30V Internal Ref = 1V


Table 55-13 shows an incorrect maximum value for the INL The corrected value is listed in the table below



INL Integral Non Linearity Best Fit curve from 0x080 to 0xF7F

i12clk = 12 MHzVDDANA = 30V External Ref = 20V


LSBi12clk = 12 MHz



SAM D5xE5x FamilyData Sheet Clarifications


DAC - 125degCTable 56-15 has incorrect maximum values displayed for the INL and DNL The corrected value is listed in the tablebelow




i12clk = 12 MHz VDDANA = 30V External Ref = 20V CLOAD= 50 pF - plusmn27 plusmn60

LSBi12clk = 12 MHz VDDANA = 30V Internal Ref CLOAD = 50 pF - plusmn52 plusmn112


i12clk = 12 MHz VDDANA = 30V External Ref = 20V CLOAD =50 pF - plusmn35 plusmn81




4 Appendix A Revision History

Rev J (112019)Added new silicon errata for 2231 Voltage Reference System

Rev H (72019)The Silicon errata for Device Operation for Temperature lt -20degC was updated with text denoting which siliconversions it applies to

Rev G (62019)The Errata Summary Table and The affected silicon revision tables in 2 Silicon Errata Issues have been updated toreflect the addition of EFP and Non-EFP silicon revisionsThe following Silicon issues were added

bull ADCndash 214 DMA Sequencingndash 215 DMA Sequencing

bull AC 222 Outputbull DFLL48 284 LLAWbull DAC 295 Referencebull RTC 2176 Prescalerbull SERCOM

ndash 21817 Wakeupndash 21818 LENGTH

The following Data Sheet Clarifications were addedbull DAC - 85degCbull DAC - 105degCbull DAC - 125degC

Rev F (22019)The following Silicon Issues were updated

bull FDPLL 2131 Low-Frequency Input Clock on FDPLLn

The following Data Sheet Clarifications were added

bull Update to Initialization Enabling Disabling and Resettingbull Update to Loop Divider Ratio Updates

Rev E (112018)The following silicon issues were added

bull SERCOM I2Cndash 21816 SERCOM I2C Repeated Start

bull CAN-FDndash 243 Message Transmitted with Wrong Arbitration and Control Fieldsndash 244 DAR Modendash 245 High-Priority Message (HPM) interruptndash 246 Tx FIFO message sequence inversion

bull PDECndash 2221 X2 Mode

bull DMACndash 2102 Channel Priority

SAM D5xE5x FamilyAppendix A Revision History


ndash 2103 DMAC in Debug Modebull RTC

ndash 2172 COUNTSYNCndash 2173 Tamper Input Filterndash 2174 Tamper Detectionndash 2175 Tamper Detection Timestamp

bull SUPCndash 2192 BOD33 Hysteresis

bull TCCndash 2213 ALOCK Featurendash 2214 LUPD feature in Down-Counting Mode

The following Data Sheet Clarifications were addedbull Table 54-35 Flash Timing Characteristics was updatedbull BOD12 Register Information was updated

Rev D (082018)The current device data sheet revision letter was updated

The following silicon issues were added

bull Configurable Custom Logic (CCL)ndash Enable Protected Registersndash Sequential Logic Reference

bull Devicendash Reverse Current in VDDIOB Domain

bull SERCOMndash Repeated Start in High-Speed Master Write Operationndash Repeated Start in High-Speed Master Read Operationndash STATUSCLKHOLD Bit in Master and Slave Modes

bull Supply Controller (SUPC)ndash Buck Converter Mode

bull TCCndash TCC with EVSYS in SYNCRESYNC Mode

Rev C (042018)The current device data sheet revision letter was updated

The following silicon issues were addedbull Analog-to-Digital Converter (ADC)

ndash Reference Buffer Offset Compensationbull Peripheral Access Controller (PAC)

ndash PAC Protectionndash PAC Protection

bull Real-Time Counter (RTC)ndash Write Corruption

bull SERCOM-I2Cndash Slave Mode with DMAndash I2C Slave in DATA32B Modendash I2C Slave Mode in 10-bit Addressndash Repeated Start

bull SERCOM-SPIndash Data Preload



bull SERCOM-UARTndash Collision Detection

All Data Sheet Clarifications were removed

Rev B (102017)This revision includes the following additions

Silicon Issuesbull Ethernet Functionality in 64-pin Packages

Data Sheet Clarificationsbull ADC Operating Conditionsbull GMAC IEEE 8023AZ Energy Efficient Supportbull SERCOM Baud Rate Equationsbull SERCOM in SPI Mode Timingbull TQFP 64-pin Packagebull DAC Operating Conditions

Rev A (72017)Initial release of this document



The Microchip Web Site

Microchip provides online support via our web site at httpwwwmicrochipcom This web site is used as a means tomake files and information easily available to customers Accessible by using your favorite Internet browser the website contains the following information

bull Product Support ndash Data sheets and errata application notes and sample programs design resources userrsquosguides and hardware support documents latest software releases and archived software

bull General Technical Support ndash Frequently Asked Questions (FAQ) technical support requests online discussiongroups Microchip consultant program member listing

bull Business of Microchip ndash Product selector and ordering guides latest Microchip press releases listing ofseminars and events listings of Microchip sales offices distributors and factory representatives

Customer Change Notification Service

Microchiprsquos customer notification service helps keep customers current on Microchip products Subscribers willreceive e-mail notification whenever there are changes updates revisions or errata related to a specified productfamily or development tool of interest

To register access the Microchip web site at httpwwwmicrochipcom Under ldquoSupportrdquo click on ldquoCustomer ChangeNotificationrdquo and follow the registration instructions

Customer Support

Users of Microchip products can receive assistance through several channels

bull Distributor or Representativebull Local Sales Officebull Field Application Engineer (FAE)bull Technical Support

Customers should contact their distributor representative or Field Application Engineer (FAE) for support Local salesoffices are also available to help customers A listing of sales offices and locations is included in the back of thisdocument

Technical support is available through the web site at httpwwwmicrochipcomsupport

Microchip Devices Code Protection Feature

Note the following details of the code protection feature on Microchip devices

bull Microchip products meet the specification contained in their particular Microchip Data Sheetbull Microchip believes that its family of products is one of the most secure families of its kind on the market today

when used in the intended manner and under normal conditionsbull There are dishonest and possibly illegal methods used to breach the code protection feature All of these

methods to our knowledge require using the Microchip products in a manner outside the operatingspecifications contained in Microchiprsquos Data Sheets Most likely the person doing so is engaged in theft ofintellectual property

bull Microchip is willing to work with the customer who is concerned about the integrity of their codebull Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code Code

protection does not mean that we are guaranteeing the product as ldquounbreakablerdquo

Code protection is constantly evolving We at Microchip are committed to continuously improving the code protectionfeatures of our products Attempts to break Microchiprsquos code protection feature may be a violation of the DigitalMillennium Copyright Act If such acts allow unauthorized access to your software or other copyrighted work youmay have a right to sue for relief under that Act

SAM D5xE5x Family


Legal Notice

Information contained in this publication regarding device applications and the like is provided only for yourconvenience and may be superseded by updates It is your responsibility to ensure that your application meets withyour specifications MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHEREXPRESS OR IMPLIED WRITTEN OR ORAL STATUTORY OR OTHERWISE RELATED TO THE INFORMATIONINCLUDING BUT NOT LIMITED TO ITS CONDITION QUALITY PERFORMANCE MERCHANTABILITY ORFITNESS FOR PURPOSE Microchip disclaims all liability arising from this information and its use Use of Microchipdevices in life support andor safety applications is entirely at the buyerrsquos risk and the buyer agrees to defendindemnify and hold harmless Microchip from any and all damages claims suits or expenses resulting from suchuse No licenses are conveyed implicitly or otherwise under any Microchip intellectual property rights unlessotherwise stated

Trademarks

The Microchip name and logo the Microchip logo AnyRate AVR AVR logo AVR Freaks BeaconThings BitCloudCryptoMemory CryptoRF dsPIC FlashFlex flexPWR Heldo JukeBlox KeeLoq KeeLoq logo Kleer LANCheckLINK MD maXStylus maXTouch MediaLB megaAVR MOST MOST logo MPLAB OptoLyzer PIC picoPowerPICSTART PIC32 logo Prochip Designer QTouch RightTouch SAM-BA SpyNIC SST SST Logo SuperFlashtinyAVR UNIO and XMEGA are registered trademarks of Microchip Technology Incorporated in the USA andother countries

ClockWorks The Embedded Control Solutions Company EtherSynch Hyper Speed Control HyperLight LoadIntelliMOS mTouch Precision Edge and Quiet-Wire are registered trademarks of Microchip Technology Incorporatedin the USA

Adjacent Key Suppression AKS Analog-for-the-Digital Age Any Capacitor AnyIn AnyOut BodyCom chipKITchipKIT logo CodeGuard CryptoAuthentication CryptoCompanion CryptoController dsPICDEM dsPICDEMnetDynamic Average Matching DAM ECAN EtherGREEN In-Circuit Serial Programming ICSP Inter-ChipConnectivity JitterBlocker KleerNet KleerNet logo Mindi MiWi motorBench MPASM MPF MPLAB Certified logoMPLIB MPLINK MultiTRAK NetDetach Omniscient Code Generation PICDEM PICDEMnet PICkit PICtailPureSilicon QMatrix RightTouch logo REAL ICE Ripple Blocker SAM-ICE Serial Quad IO SMART-IS SQISuperSwitcher SuperSwitcher II Total Endurance TSHARC USBCheck VariSense ViewSpan WiperLockWireless DNA and ZENA are trademarks of Microchip Technology Incorporated in the USA and other countries

SQTP is a service mark of Microchip Technology Incorporated in the USA

Silicon Storage Technology is a registered trademark of Microchip Technology Inc in other countries

GestIC is a registered trademark of Microchip Technology Germany II GmbH amp Co KG a subsidiary of MicrochipTechnology Inc in other countries

All other trademarks mentioned herein are property of their respective companiescopy 2018 Microchip Technology Incorporated Printed in the USA All Rights Reserved

ISBN 978-1-5224-5227-0

Quality Management System Certified by DNV

ISOTS 16949Microchip received ISOTS-169492009 certification for its worldwide headquarters design and wafer fabricationfacilities in Chandler and Tempe Arizona Gresham Oregon and design centers in California and India TheCompanyrsquos quality system processes and procedures are for its PICreg MCUs and dsPICreg DSCs KEELOQreg codehopping devices Serial EEPROMs microperipherals nonvolatile memory and analog products In additionMicrochiprsquos quality system for the design and manufacture of development systems is ISO 90012000 certified

SAM D5xE5x Family


AMERICAS ASIAPACIFIC ASIAPACIFIC EUROPECorporate Office2355 West Chandler BlvdChandler AZ 85224-6199Tel 480-792-7200Fax 480-792-7277Technical SupporthttpwwwmicrochipcomsupportWeb AddresswwwmicrochipcomAtlantaDuluth GATel 678-957-9614Fax 678-957-1455Austin TXTel 512-257-3370BostonWestborough MATel 774-760-0087Fax 774-760-0088ChicagoItasca ILTel 630-285-0071Fax 630-285-0075DallasAddison TXTel 972-818-7423Fax 972-818-2924DetroitNovi MITel 248-848-4000Houston TXTel 281-894-5983IndianapolisNoblesville INTel 317-773-8323Fax 317-773-5453Tel 317-536-2380Los AngelesMission Viejo CATel 949-462-9523Fax 949-462-9608Tel 951-273-7800Raleigh NCTel 919-844-7510New York NYTel 631-435-6000San Jose CATel 408-735-9110Tel 408-436-4270Canada - TorontoTel 905-695-1980Fax 905-695-2078

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Austria - WelsTel 43-7242-2244-39Fax 43-7242-2244-393Denmark - CopenhagenTel 45-4450-2828Fax 45-4485-2829Finland - EspooTel 358-9-4520-820France - ParisTel 33-1-69-53-63-20Fax 33-1-69-30-90-79Germany - GarchingTel 49-8931-9700Germany - HaanTel 49-2129-3766400Germany - HeilbronnTel 49-7131-67-3636Germany - KarlsruheTel 49-721-625370Germany - MunichTel 49-89-627-144-0Fax 49-89-627-144-44Germany - RosenheimTel 49-8031-354-560Israel - RarsquoananaTel 972-9-744-7705Italy - MilanTel 39-0331-742611Fax 39-0331-466781Italy - PadovaTel 39-049-7625286Netherlands - DrunenTel 31-416-690399Fax 31-416-690340Norway - TrondheimTel 47-7289-7561Poland - WarsawTel 48-22-3325737Romania - BucharestTel 40-21-407-87-50Spain - MadridTel 34-91-708-08-90Fax 34-91-708-08-91Sweden - GothenbergTel 46-31-704-60-40Sweden - StockholmTel 46-8-5090-4654UK - WokinghamTel 44-118-921-5800Fax 44-118-921-5820

Worldwide Sales and Service


SAM D5xE5x Family Errata

Table of Contents

1 Silicon Errata Summary

2 Silicon Errata Issues


211 ADC SYNCBUSYSWTRIG

212 ADC TUEINLDNL Performance

213 Reference Buffer Offset Compensation

214 DMA Sequencing

215 DMA Sequencing


221 AC Hysteresis

222 Output


231 Enable Protected Registers

232 Sequential Logic Reference


241 CAN Edge Filtering

242 Dominant Bit of Intermission

243 Message Transmitted with Wrong Arbitration and Control Fields

244 DAR Mode

245 High-Priority Message (HPM) interrupt

246 Tx FIFO message sequence inversion


251 CFD with XOSCXOSC32K Oscillator

26 Device

261 Reverse Current in VDDIOB Domain

262 Internal Pull-up on the RESET Pin

263 Detection of a Debugger Probe

264 VBAT Mode

265 Internal Reference

266 Device Operation for Temperature lt -20degC


271 CRC32


281 COARSE or FINE Calibration Values During the Locking Sequence

282 STATUSDFLLRDY Bit in Close Loop Mode

283 DFLLVALFINE Value When DFLL48M Re-enabled

284 LLAW


291 Smoothing of the Output Signal in differential Mode

292 VDDANA as the DAC Reference

293 DAC on Negative Input AIN3

294 Interpolation Mode

295 Reference


2101 Linked Descriptors

2102 Channel Priority

2103 DMAC in Debug Mode


2111 Ethernet Functionality in 64-pin Packages


2121 Edge Detection

2122 Asynchronous Edge Detection


2131 Low-Frequency Input Clock on FDPLLn

2132 FDPLL Ratio in DPLLnRATIO


2141 NVM Read Corruption


2151 PAC Protection Error in FREQM

2152 PAC Protection Error in CCL


2161 PORT ReadWrite Attempts on Non-Implemented Registers

2162 PORT Pull-UpPull-Down Resistor


2171 Write Corruption

2172 COUNTSYNC

2173 Tamper Input Filter

2174 Tamper Detection

2175 Tamper Detection Timestamp

2176 Prescaler


2181 SERCOM-USART Auto-Baud Mode

2182 SERCOM-USART Collision Detection

2183 SERCOM-USART Debug Mode

2184 SERCOM-USART 32-bit Extension Mode

2185 SERCOM-UART TXINV and RXINV Bits

2186 SERCOM-I2C SDAHOLD Timing

2187 Repeated Start in High-Speed Master Write Operation

2188 Repeated Start in High-Speed Master Read Operation

2189 STATUSCLKHOLD Bit in Master and Slave Modes

21810 SERCOM-I2C I2C in Slave Mode

21811 SERCOM-I2C Slave Mode with DMA

21812 SERCOM-I2C I2C Slave in DATA32B Mode

21813 SERCOM-I2C 10-bit Addressing Mode

21814 SERCOM-I2C Repeated Start

21815 SERCOM-SPI Data Preload

21816 SERCOM I2C Repeated Start

21817 Wakeup

21818 LENGTH


2191 Buck Converter Mode

2192 BOD33 Hysteresis


2201 PERBUFCCBUFx Register


2211 TCC with EVSYS in SYNCRESYNC Mode

2212 Dithering Mode with External Retrigger Events

2213 ALOCK Feature

2214 LUPD feature in Down-Counting Mode


2221 X2 Mode


2231 Temperature Sensor

3 Data Sheet Clarifications




Customer Support


Legal Notice

Trademarks



Table 1 SAM D5xE5x Family Silicon Device Identification

Part Number Device Identification (DID[310])Revision ID (DIDREVISION[30])

A D


0x0 0x3























ATSAME51G18A 0x61810306NA 0x3

ATSAME51G19A 0x61810305

Data Sheet clarifications and corrections (if applicable) are located in the section Data Sheet Clarifications followingthe discussion of silicon issues

Note Refer to the ldquoDevice Service Unitrdquo chapter in the current preliminary device data sheet (DS60001507E) for adetailed information on Device Identification and Revision IDs for your specific device

SAM D5xE5x Family


Table of Contents









Customer Support 43


Legal Notice 44

Trademarks 44



SAM D5xE5x Family



Module FeatureItem

NumberIssue Summary

EFPNon-EFP

AffectedRevisions

A D



EFP - X

Non-EFP

X X


ADC TUEINLDNL 212




EFP -

Non-EFP

X



213


EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X


DMA Sequencing 215


EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X



continued

Module FeatureItem

NumberIssue Summary

EFPNon-EFP

AffectedRevisions

A D



EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X




EFP -

Non-EFP

X


Domain261


EFP -

Non-EFP

X



EFP -

Non-EFP

X


Probe263


EFP - X

Non-EFP

X X


EFP -

Non-EFP

X


EFP -

Non-EFP

X



EFP -

Non-EFP

X X


EFP - X

Non-EFP

X X





EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X




EFP -

Non-EFP

X



continued

Module FeatureItem

NumberIssue Summary

EFPNon-EFP

AffectedRevisions

A D


LLAW 284


EFP - X

Non-EFP

X X



Signal291


EFP - X

Non-EFP

X X




EFP -

Non-EFP

X




EFP -

Non-EFP

X



EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X



EFP -

Non-EFP

X



EFP -

Non-EFP

X



EFP -

Non-EFP

X



EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X


(FDPLL)



EFP - X

Non-EFP

X X


(FDPLL)



EFP - X

Non-EFP

X X



continued

Module FeatureItem

NumberIssue Summary

EFPNon-EFP

AffectedRevisions

A D



EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X



Registers2161


EFP - X

Non-EFP

X X



2162


EFP -

Non-EFP

X







EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X



2182


EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X



continued

Module FeatureItem

NumberIssue Summary

EFPNon-EFP

AffectedRevisions

A D




EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X



Operation2187


EFP - X

Non-EFP

X X



Operation2188


EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X



21812


EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X



21815


EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X



continued

Module FeatureItem

NumberIssue Summary

EFPNon-EFP

AffectedRevisions

A D


LENGTH 21818


EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X


EFP - X

Non-EFP

X X


(TCC)



EFP - X

Non-EFP

X X


(TCC)



EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X


(TCC)



EFP - X

Non-EFP

X X


EFP - X

Non-EFP

X X



EFP X X

Non-EFP

X X












Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP -

Non-EFP X






Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X











Scope


Effects


Workaround



Device A D

EFP - X

Non-EFP X X







Effects




Device A D

EFP - X

Non-EFP X X








Scope




Effects











Device A D

EFP - X

Non-EFP X X




Scope


Effects


WorkaroundNone


Device A D

EFP - X



continuedDevice A D

Non-EFP X X


Configuration A






Configuration B






Scope


Configuration A


Configuration B


Effects










Configuration B





Device A D

EFP - X

Non-EFP X X















Scope


Effects





Workaround 1




Transmit Loop


Workaround 2



Workaround 3




Device A D

EFP - X

Non-EFP X X









Device A D

EFP -

Non-EFP X

26 Device




Device A D

EFP -

Non-EFP X




Device A D

EFP -

Non-EFP X




Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP -

Non-EFP X




Device A D

EFP -

Non-EFP X




Device A D

EFP -

Non-EFP X X





Device A D

EFP - X

Non-EFP X X







Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X





Device A D

EFP -

Non-EFP X






Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP -

Non-EFP X






Device A D

EFP -

Non-EFP X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X







Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP -

Non-EFP X




Device A D

EFP -

Non-EFP X



WorkaroundNone


Device A D

EFP -

Non-EFP X





WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Pseudo Code






Delay (10ms)



Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X



WorkaroundNone




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP -

Non-EFP X









Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X








Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X





WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X






Device A D

EFP - X

Non-EFP X X





0x1 50 ns to 100 ns 20 ns to 40 ns

0x2 300 ns to 600 ns 100 ns to 250 ns

0x3 400 ns to 800 ns 150 ns to 350 ns

WorkaroundNone


Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X








Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X






Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundsNone




Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X







Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP X X

Non-EFP X X
























LSBi12clk = 12 MHz









LSBi12clk = 12 MHz








































































Customer Support













SAM D5xE5x Family


Legal Notice


Trademarks








ISBN 978-1-5224-5227-0



SAM D5xE5x Family









Table of Contents







214 DMA Sequencing

215 DMA Sequencing


221 AC Hysteresis

222 Output








244 DAR Mode





26 Device




264 VBAT Mode




271 CRC32





284 LLAW






295 Reference








2121 Edge Detection















2172 COUNTSYNC




2176 Prescaler


















21817 Wakeup

21818 LENGTH









2213 ALOCK Feature



2221 X2 Mode







Customer Support


Legal Notice

Trademarks



Table of Contents









Customer Support 43


Legal Notice 44

Trademarks 44



SAM D5xE5x Family



Module FeatureItem

NumberIssue Summary

EFPNon-EFP

AffectedRevisions

A D



EFP - X

Non-EFP

X X


ADC TUEINLDNL 212




EFP -

Non-EFP

X



213


EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X


DMA Sequencing 215


EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X



continued

Module FeatureItem

NumberIssue Summary

EFPNon-EFP

AffectedRevisions

A D



EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X




EFP -

Non-EFP

X


Domain261


EFP -

Non-EFP

X



EFP -

Non-EFP

X


Probe263


EFP - X

Non-EFP

X X


EFP -

Non-EFP

X


EFP -

Non-EFP

X



EFP -

Non-EFP

X X


EFP - X

Non-EFP

X X





EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X




EFP -

Non-EFP

X



continued

Module FeatureItem

NumberIssue Summary

EFPNon-EFP

AffectedRevisions

A D


LLAW 284


EFP - X

Non-EFP

X X



Signal291


EFP - X

Non-EFP

X X




EFP -

Non-EFP

X




EFP -

Non-EFP

X



EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X



EFP -

Non-EFP

X



EFP -

Non-EFP

X



EFP -

Non-EFP

X



EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X


(FDPLL)



EFP - X

Non-EFP

X X


(FDPLL)



EFP - X

Non-EFP

X X



continued

Module FeatureItem

NumberIssue Summary

EFPNon-EFP

AffectedRevisions

A D



EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X



Registers2161


EFP - X

Non-EFP

X X



2162


EFP -

Non-EFP

X







EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X



2182


EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X



continued

Module FeatureItem

NumberIssue Summary

EFPNon-EFP

AffectedRevisions

A D




EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X



Operation2187


EFP - X

Non-EFP

X X



Operation2188


EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X



21812


EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X



21815


EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X



continued

Module FeatureItem

NumberIssue Summary

EFPNon-EFP

AffectedRevisions

A D


LENGTH 21818


EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X


EFP - X

Non-EFP

X X


(TCC)



EFP - X

Non-EFP

X X


(TCC)



EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X


(TCC)



EFP - X

Non-EFP

X X


EFP - X

Non-EFP

X X



EFP X X

Non-EFP

X X












Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP -

Non-EFP X






Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X











Scope


Effects


Workaround



Device A D

EFP - X

Non-EFP X X







Effects




Device A D

EFP - X

Non-EFP X X








Scope




Effects











Device A D

EFP - X

Non-EFP X X




Scope


Effects


WorkaroundNone


Device A D

EFP - X



continuedDevice A D

Non-EFP X X


Configuration A






Configuration B






Scope


Configuration A


Configuration B


Effects










Configuration B





Device A D

EFP - X

Non-EFP X X















Scope


Effects





Workaround 1




Transmit Loop


Workaround 2



Workaround 3




Device A D

EFP - X

Non-EFP X X









Device A D

EFP -

Non-EFP X

26 Device




Device A D

EFP -

Non-EFP X




Device A D

EFP -

Non-EFP X




Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP -

Non-EFP X




Device A D

EFP -

Non-EFP X




Device A D

EFP -

Non-EFP X X





Device A D

EFP - X

Non-EFP X X







Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X





Device A D

EFP -

Non-EFP X






Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP -

Non-EFP X






Device A D

EFP -

Non-EFP X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X







Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP -

Non-EFP X




Device A D

EFP -

Non-EFP X



WorkaroundNone


Device A D

EFP -

Non-EFP X





WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Pseudo Code






Delay (10ms)



Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X



WorkaroundNone




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP -

Non-EFP X









Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X








Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X





WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X






Device A D

EFP - X

Non-EFP X X





0x1 50 ns to 100 ns 20 ns to 40 ns

0x2 300 ns to 600 ns 100 ns to 250 ns

0x3 400 ns to 800 ns 150 ns to 350 ns

WorkaroundNone


Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X








Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X






Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundsNone




Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X







Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP X X

Non-EFP X X
























LSBi12clk = 12 MHz









LSBi12clk = 12 MHz








































































Customer Support













SAM D5xE5x Family


Legal Notice


Trademarks








ISBN 978-1-5224-5227-0



SAM D5xE5x Family









Table of Contents







214 DMA Sequencing

215 DMA Sequencing


221 AC Hysteresis

222 Output








244 DAR Mode





26 Device




264 VBAT Mode




271 CRC32





284 LLAW






295 Reference








2121 Edge Detection















2172 COUNTSYNC




2176 Prescaler


















21817 Wakeup

21818 LENGTH









2213 ALOCK Feature



2221 X2 Mode







Customer Support


Legal Notice

Trademarks




Module FeatureItem

NumberIssue Summary

EFPNon-EFP

AffectedRevisions

A D



EFP - X

Non-EFP

X X


ADC TUEINLDNL 212




EFP -

Non-EFP

X



213


EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X


DMA Sequencing 215


EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X



continued

Module FeatureItem

NumberIssue Summary

EFPNon-EFP

AffectedRevisions

A D



EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X




EFP -

Non-EFP

X


Domain261


EFP -

Non-EFP

X



EFP -

Non-EFP

X


Probe263


EFP - X

Non-EFP

X X


EFP -

Non-EFP

X


EFP -

Non-EFP

X



EFP -

Non-EFP

X X


EFP - X

Non-EFP

X X





EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X




EFP -

Non-EFP

X



continued

Module FeatureItem

NumberIssue Summary

EFPNon-EFP

AffectedRevisions

A D


LLAW 284


EFP - X

Non-EFP

X X



Signal291


EFP - X

Non-EFP

X X




EFP -

Non-EFP

X




EFP -

Non-EFP

X



EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X



EFP -

Non-EFP

X



EFP -

Non-EFP

X



EFP -

Non-EFP

X



EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X


(FDPLL)



EFP - X

Non-EFP

X X


(FDPLL)



EFP - X

Non-EFP

X X



continued

Module FeatureItem

NumberIssue Summary

EFPNon-EFP

AffectedRevisions

A D



EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X



Registers2161


EFP - X

Non-EFP

X X



2162


EFP -

Non-EFP

X







EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X



2182


EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X



continued

Module FeatureItem

NumberIssue Summary

EFPNon-EFP

AffectedRevisions

A D




EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X



Operation2187


EFP - X

Non-EFP

X X



Operation2188


EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X



21812


EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X



21815


EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X



continued

Module FeatureItem

NumberIssue Summary

EFPNon-EFP

AffectedRevisions

A D


LENGTH 21818


EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X


EFP - X

Non-EFP

X X


(TCC)



EFP - X

Non-EFP

X X


(TCC)



EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X


(TCC)



EFP - X

Non-EFP

X X


EFP - X

Non-EFP

X X



EFP X X

Non-EFP

X X












Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP -

Non-EFP X






Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X











Scope


Effects


Workaround



Device A D

EFP - X

Non-EFP X X







Effects




Device A D

EFP - X

Non-EFP X X








Scope




Effects











Device A D

EFP - X

Non-EFP X X




Scope


Effects


WorkaroundNone


Device A D

EFP - X



continuedDevice A D

Non-EFP X X


Configuration A






Configuration B






Scope


Configuration A


Configuration B


Effects










Configuration B





Device A D

EFP - X

Non-EFP X X















Scope


Effects





Workaround 1




Transmit Loop


Workaround 2



Workaround 3




Device A D

EFP - X

Non-EFP X X









Device A D

EFP -

Non-EFP X

26 Device




Device A D

EFP -

Non-EFP X




Device A D

EFP -

Non-EFP X




Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP -

Non-EFP X




Device A D

EFP -

Non-EFP X




Device A D

EFP -

Non-EFP X X





Device A D

EFP - X

Non-EFP X X







Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X





Device A D

EFP -

Non-EFP X






Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP -

Non-EFP X






Device A D

EFP -

Non-EFP X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X







Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP -

Non-EFP X




Device A D

EFP -

Non-EFP X



WorkaroundNone


Device A D

EFP -

Non-EFP X





WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Pseudo Code






Delay (10ms)



Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X



WorkaroundNone




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP -

Non-EFP X









Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X








Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X





WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X






Device A D

EFP - X

Non-EFP X X





0x1 50 ns to 100 ns 20 ns to 40 ns

0x2 300 ns to 600 ns 100 ns to 250 ns

0x3 400 ns to 800 ns 150 ns to 350 ns

WorkaroundNone


Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X








Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X






Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundsNone




Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X







Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP X X

Non-EFP X X
























LSBi12clk = 12 MHz









LSBi12clk = 12 MHz








































































Customer Support













SAM D5xE5x Family


Legal Notice


Trademarks








ISBN 978-1-5224-5227-0



SAM D5xE5x Family









Table of Contents







214 DMA Sequencing

215 DMA Sequencing


221 AC Hysteresis

222 Output








244 DAR Mode





26 Device




264 VBAT Mode




271 CRC32





284 LLAW






295 Reference








2121 Edge Detection















2172 COUNTSYNC




2176 Prescaler


















21817 Wakeup

21818 LENGTH









2213 ALOCK Feature



2221 X2 Mode







Customer Support


Legal Notice

Trademarks



continued

Module FeatureItem

NumberIssue Summary

EFPNon-EFP

AffectedRevisions

A D



EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X




EFP -

Non-EFP

X


Domain261


EFP -

Non-EFP

X



EFP -

Non-EFP

X


Probe263


EFP - X

Non-EFP

X X


EFP -

Non-EFP

X


EFP -

Non-EFP

X



EFP -

Non-EFP

X X


EFP - X

Non-EFP

X X





EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X




EFP -

Non-EFP

X



continued

Module FeatureItem

NumberIssue Summary

EFPNon-EFP

AffectedRevisions

A D


LLAW 284


EFP - X

Non-EFP

X X



Signal291


EFP - X

Non-EFP

X X




EFP -

Non-EFP

X




EFP -

Non-EFP

X



EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X



EFP -

Non-EFP

X



EFP -

Non-EFP

X



EFP -

Non-EFP

X



EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X


(FDPLL)



EFP - X

Non-EFP

X X


(FDPLL)



EFP - X

Non-EFP

X X



continued

Module FeatureItem

NumberIssue Summary

EFPNon-EFP

AffectedRevisions

A D



EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X



Registers2161


EFP - X

Non-EFP

X X



2162


EFP -

Non-EFP

X







EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X



2182


EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X



continued

Module FeatureItem

NumberIssue Summary

EFPNon-EFP

AffectedRevisions

A D




EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X



Operation2187


EFP - X

Non-EFP

X X



Operation2188


EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X



21812


EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X



21815


EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X



continued

Module FeatureItem

NumberIssue Summary

EFPNon-EFP

AffectedRevisions

A D


LENGTH 21818


EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X


EFP - X

Non-EFP

X X


(TCC)



EFP - X

Non-EFP

X X


(TCC)



EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X


(TCC)



EFP - X

Non-EFP

X X


EFP - X

Non-EFP

X X



EFP X X

Non-EFP

X X












Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP -

Non-EFP X






Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X











Scope


Effects


Workaround



Device A D

EFP - X

Non-EFP X X







Effects




Device A D

EFP - X

Non-EFP X X








Scope




Effects











Device A D

EFP - X

Non-EFP X X




Scope


Effects


WorkaroundNone


Device A D

EFP - X



continuedDevice A D

Non-EFP X X


Configuration A






Configuration B






Scope


Configuration A


Configuration B


Effects










Configuration B





Device A D

EFP - X

Non-EFP X X















Scope


Effects





Workaround 1




Transmit Loop


Workaround 2



Workaround 3




Device A D

EFP - X

Non-EFP X X









Device A D

EFP -

Non-EFP X

26 Device




Device A D

EFP -

Non-EFP X




Device A D

EFP -

Non-EFP X




Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP -

Non-EFP X




Device A D

EFP -

Non-EFP X




Device A D

EFP -

Non-EFP X X





Device A D

EFP - X

Non-EFP X X







Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X





Device A D

EFP -

Non-EFP X






Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP -

Non-EFP X






Device A D

EFP -

Non-EFP X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X







Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP -

Non-EFP X




Device A D

EFP -

Non-EFP X



WorkaroundNone


Device A D

EFP -

Non-EFP X





WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Pseudo Code






Delay (10ms)



Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X



WorkaroundNone




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP -

Non-EFP X









Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X








Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X





WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X






Device A D

EFP - X

Non-EFP X X





0x1 50 ns to 100 ns 20 ns to 40 ns

0x2 300 ns to 600 ns 100 ns to 250 ns

0x3 400 ns to 800 ns 150 ns to 350 ns

WorkaroundNone


Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X








Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X






Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundsNone




Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X







Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP X X

Non-EFP X X
























LSBi12clk = 12 MHz









LSBi12clk = 12 MHz








































































Customer Support













SAM D5xE5x Family


Legal Notice


Trademarks








ISBN 978-1-5224-5227-0



SAM D5xE5x Family









Table of Contents







214 DMA Sequencing

215 DMA Sequencing


221 AC Hysteresis

222 Output








244 DAR Mode





26 Device




264 VBAT Mode




271 CRC32





284 LLAW






295 Reference








2121 Edge Detection















2172 COUNTSYNC




2176 Prescaler


















21817 Wakeup

21818 LENGTH









2213 ALOCK Feature



2221 X2 Mode







Customer Support


Legal Notice

Trademarks



continued

Module FeatureItem

NumberIssue Summary

EFPNon-EFP

AffectedRevisions

A D


LLAW 284


EFP - X

Non-EFP

X X



Signal291


EFP - X

Non-EFP

X X




EFP -

Non-EFP

X




EFP -

Non-EFP

X



EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X



EFP -

Non-EFP

X



EFP -

Non-EFP

X



EFP -

Non-EFP

X



EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X


(FDPLL)



EFP - X

Non-EFP

X X


(FDPLL)



EFP - X

Non-EFP

X X



continued

Module FeatureItem

NumberIssue Summary

EFPNon-EFP

AffectedRevisions

A D



EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X



Registers2161


EFP - X

Non-EFP

X X



2162


EFP -

Non-EFP

X







EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X



2182


EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X



continued

Module FeatureItem

NumberIssue Summary

EFPNon-EFP

AffectedRevisions

A D




EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X



Operation2187


EFP - X

Non-EFP

X X



Operation2188


EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X



21812


EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X



21815


EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X



continued

Module FeatureItem

NumberIssue Summary

EFPNon-EFP

AffectedRevisions

A D


LENGTH 21818


EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X


EFP - X

Non-EFP

X X


(TCC)



EFP - X

Non-EFP

X X


(TCC)



EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X


(TCC)



EFP - X

Non-EFP

X X


EFP - X

Non-EFP

X X



EFP X X

Non-EFP

X X












Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP -

Non-EFP X






Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X











Scope


Effects


Workaround



Device A D

EFP - X

Non-EFP X X







Effects




Device A D

EFP - X

Non-EFP X X








Scope




Effects











Device A D

EFP - X

Non-EFP X X




Scope


Effects


WorkaroundNone


Device A D

EFP - X



continuedDevice A D

Non-EFP X X


Configuration A






Configuration B






Scope


Configuration A


Configuration B


Effects










Configuration B





Device A D

EFP - X

Non-EFP X X















Scope


Effects





Workaround 1




Transmit Loop


Workaround 2



Workaround 3




Device A D

EFP - X

Non-EFP X X









Device A D

EFP -

Non-EFP X

26 Device




Device A D

EFP -

Non-EFP X




Device A D

EFP -

Non-EFP X




Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP -

Non-EFP X




Device A D

EFP -

Non-EFP X




Device A D

EFP -

Non-EFP X X





Device A D

EFP - X

Non-EFP X X







Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X





Device A D

EFP -

Non-EFP X






Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP -

Non-EFP X






Device A D

EFP -

Non-EFP X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X







Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP -

Non-EFP X




Device A D

EFP -

Non-EFP X



WorkaroundNone


Device A D

EFP -

Non-EFP X





WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Pseudo Code






Delay (10ms)



Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X



WorkaroundNone




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP -

Non-EFP X









Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X








Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X





WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X






Device A D

EFP - X

Non-EFP X X





0x1 50 ns to 100 ns 20 ns to 40 ns

0x2 300 ns to 600 ns 100 ns to 250 ns

0x3 400 ns to 800 ns 150 ns to 350 ns

WorkaroundNone


Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X








Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X






Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundsNone




Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X







Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP X X

Non-EFP X X
























LSBi12clk = 12 MHz









LSBi12clk = 12 MHz








































































Customer Support













SAM D5xE5x Family


Legal Notice


Trademarks








ISBN 978-1-5224-5227-0



SAM D5xE5x Family









Table of Contents







214 DMA Sequencing

215 DMA Sequencing


221 AC Hysteresis

222 Output








244 DAR Mode





26 Device




264 VBAT Mode




271 CRC32





284 LLAW






295 Reference








2121 Edge Detection















2172 COUNTSYNC




2176 Prescaler


















21817 Wakeup

21818 LENGTH









2213 ALOCK Feature



2221 X2 Mode







Customer Support


Legal Notice

Trademarks



continued

Module FeatureItem

NumberIssue Summary

EFPNon-EFP

AffectedRevisions

A D



EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X



Registers2161


EFP - X

Non-EFP

X X



2162


EFP -

Non-EFP

X







EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X



2182


EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X



continued

Module FeatureItem

NumberIssue Summary

EFPNon-EFP

AffectedRevisions

A D




EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X



Operation2187


EFP - X

Non-EFP

X X



Operation2188


EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X



21812


EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X



21815


EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X



continued

Module FeatureItem

NumberIssue Summary

EFPNon-EFP

AffectedRevisions

A D


LENGTH 21818


EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X


EFP - X

Non-EFP

X X


(TCC)



EFP - X

Non-EFP

X X


(TCC)



EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X


(TCC)



EFP - X

Non-EFP

X X


EFP - X

Non-EFP

X X



EFP X X

Non-EFP

X X












Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP -

Non-EFP X






Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X











Scope


Effects


Workaround



Device A D

EFP - X

Non-EFP X X







Effects




Device A D

EFP - X

Non-EFP X X








Scope




Effects











Device A D

EFP - X

Non-EFP X X




Scope


Effects


WorkaroundNone


Device A D

EFP - X



continuedDevice A D

Non-EFP X X


Configuration A






Configuration B






Scope


Configuration A


Configuration B


Effects










Configuration B





Device A D

EFP - X

Non-EFP X X















Scope


Effects





Workaround 1




Transmit Loop


Workaround 2



Workaround 3




Device A D

EFP - X

Non-EFP X X









Device A D

EFP -

Non-EFP X

26 Device




Device A D

EFP -

Non-EFP X




Device A D

EFP -

Non-EFP X




Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP -

Non-EFP X




Device A D

EFP -

Non-EFP X




Device A D

EFP -

Non-EFP X X





Device A D

EFP - X

Non-EFP X X







Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X





Device A D

EFP -

Non-EFP X






Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP -

Non-EFP X






Device A D

EFP -

Non-EFP X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X







Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP -

Non-EFP X




Device A D

EFP -

Non-EFP X



WorkaroundNone


Device A D

EFP -

Non-EFP X





WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Pseudo Code






Delay (10ms)



Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X



WorkaroundNone




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP -

Non-EFP X









Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X








Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X





WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X






Device A D

EFP - X

Non-EFP X X





0x1 50 ns to 100 ns 20 ns to 40 ns

0x2 300 ns to 600 ns 100 ns to 250 ns

0x3 400 ns to 800 ns 150 ns to 350 ns

WorkaroundNone


Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X








Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X






Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundsNone




Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X







Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP X X

Non-EFP X X
























LSBi12clk = 12 MHz









LSBi12clk = 12 MHz








































































Customer Support













SAM D5xE5x Family


Legal Notice


Trademarks








ISBN 978-1-5224-5227-0



SAM D5xE5x Family









Table of Contents







214 DMA Sequencing

215 DMA Sequencing


221 AC Hysteresis

222 Output








244 DAR Mode





26 Device




264 VBAT Mode




271 CRC32





284 LLAW






295 Reference








2121 Edge Detection















2172 COUNTSYNC




2176 Prescaler


















21817 Wakeup

21818 LENGTH









2213 ALOCK Feature



2221 X2 Mode







Customer Support


Legal Notice

Trademarks



continued

Module FeatureItem

NumberIssue Summary

EFPNon-EFP

AffectedRevisions

A D




EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X



Operation2187


EFP - X

Non-EFP

X X



Operation2188


EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X



21812


EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X




EFP - X

Non-EFP

X X



21815


EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X



continued

Module FeatureItem

NumberIssue Summary

EFPNon-EFP

AffectedRevisions

A D


LENGTH 21818


EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X


EFP - X

Non-EFP

X X


(TCC)



EFP - X

Non-EFP

X X


(TCC)



EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X


(TCC)



EFP - X

Non-EFP

X X


EFP - X

Non-EFP

X X



EFP X X

Non-EFP

X X












Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP -

Non-EFP X






Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X











Scope


Effects


Workaround



Device A D

EFP - X

Non-EFP X X







Effects




Device A D

EFP - X

Non-EFP X X








Scope




Effects











Device A D

EFP - X

Non-EFP X X




Scope


Effects


WorkaroundNone


Device A D

EFP - X



continuedDevice A D

Non-EFP X X


Configuration A






Configuration B






Scope


Configuration A


Configuration B


Effects










Configuration B





Device A D

EFP - X

Non-EFP X X















Scope


Effects





Workaround 1




Transmit Loop


Workaround 2



Workaround 3




Device A D

EFP - X

Non-EFP X X









Device A D

EFP -

Non-EFP X

26 Device




Device A D

EFP -

Non-EFP X




Device A D

EFP -

Non-EFP X




Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP -

Non-EFP X




Device A D

EFP -

Non-EFP X




Device A D

EFP -

Non-EFP X X





Device A D

EFP - X

Non-EFP X X







Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X





Device A D

EFP -

Non-EFP X






Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP -

Non-EFP X






Device A D

EFP -

Non-EFP X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X







Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP -

Non-EFP X




Device A D

EFP -

Non-EFP X



WorkaroundNone


Device A D

EFP -

Non-EFP X





WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Pseudo Code






Delay (10ms)



Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X



WorkaroundNone




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP -

Non-EFP X









Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X








Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X





WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X






Device A D

EFP - X

Non-EFP X X





0x1 50 ns to 100 ns 20 ns to 40 ns

0x2 300 ns to 600 ns 100 ns to 250 ns

0x3 400 ns to 800 ns 150 ns to 350 ns

WorkaroundNone


Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X








Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X






Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundsNone




Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X







Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP X X

Non-EFP X X
























LSBi12clk = 12 MHz









LSBi12clk = 12 MHz








































































Customer Support













SAM D5xE5x Family


Legal Notice


Trademarks








ISBN 978-1-5224-5227-0



SAM D5xE5x Family









Table of Contents







214 DMA Sequencing

215 DMA Sequencing


221 AC Hysteresis

222 Output








244 DAR Mode





26 Device




264 VBAT Mode




271 CRC32





284 LLAW






295 Reference








2121 Edge Detection















2172 COUNTSYNC




2176 Prescaler


















21817 Wakeup

21818 LENGTH









2213 ALOCK Feature



2221 X2 Mode







Customer Support


Legal Notice

Trademarks



continued

Module FeatureItem

NumberIssue Summary

EFPNon-EFP

AffectedRevisions

A D


LENGTH 21818


EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X


EFP - X

Non-EFP

X X


(TCC)



EFP - X

Non-EFP

X X


(TCC)



EFP - X

Non-EFP

X X



EFP - X

Non-EFP

X X


(TCC)



EFP - X

Non-EFP

X X


EFP - X

Non-EFP

X X



EFP X X

Non-EFP

X X












Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP -

Non-EFP X






Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X











Scope


Effects


Workaround



Device A D

EFP - X

Non-EFP X X







Effects




Device A D

EFP - X

Non-EFP X X








Scope




Effects











Device A D

EFP - X

Non-EFP X X




Scope


Effects


WorkaroundNone


Device A D

EFP - X



continuedDevice A D

Non-EFP X X


Configuration A






Configuration B






Scope


Configuration A


Configuration B


Effects










Configuration B





Device A D

EFP - X

Non-EFP X X















Scope


Effects





Workaround 1




Transmit Loop


Workaround 2



Workaround 3




Device A D

EFP - X

Non-EFP X X









Device A D

EFP -

Non-EFP X

26 Device




Device A D

EFP -

Non-EFP X




Device A D

EFP -

Non-EFP X




Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP -

Non-EFP X




Device A D

EFP -

Non-EFP X




Device A D

EFP -

Non-EFP X X





Device A D

EFP - X

Non-EFP X X







Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X





Device A D

EFP -

Non-EFP X






Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP -

Non-EFP X






Device A D

EFP -

Non-EFP X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X







Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP -

Non-EFP X




Device A D

EFP -

Non-EFP X



WorkaroundNone


Device A D

EFP -

Non-EFP X





WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Pseudo Code






Delay (10ms)



Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X



WorkaroundNone




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP -

Non-EFP X









Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X








Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X





WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X






Device A D

EFP - X

Non-EFP X X





0x1 50 ns to 100 ns 20 ns to 40 ns

0x2 300 ns to 600 ns 100 ns to 250 ns

0x3 400 ns to 800 ns 150 ns to 350 ns

WorkaroundNone


Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X








Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X






Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundsNone




Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X







Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP X X

Non-EFP X X
























LSBi12clk = 12 MHz









LSBi12clk = 12 MHz








































































Customer Support













SAM D5xE5x Family


Legal Notice


Trademarks








ISBN 978-1-5224-5227-0



SAM D5xE5x Family









Table of Contents







214 DMA Sequencing

215 DMA Sequencing


221 AC Hysteresis

222 Output








244 DAR Mode





26 Device




264 VBAT Mode




271 CRC32





284 LLAW






295 Reference








2121 Edge Detection















2172 COUNTSYNC




2176 Prescaler


















21817 Wakeup

21818 LENGTH









2213 ALOCK Feature



2221 X2 Mode







Customer Support


Legal Notice

Trademarks











Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP -

Non-EFP X






Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X











Scope


Effects


Workaround



Device A D

EFP - X

Non-EFP X X







Effects




Device A D

EFP - X

Non-EFP X X








Scope




Effects











Device A D

EFP - X

Non-EFP X X




Scope


Effects


WorkaroundNone


Device A D

EFP - X



continuedDevice A D

Non-EFP X X


Configuration A






Configuration B






Scope


Configuration A


Configuration B


Effects










Configuration B





Device A D

EFP - X

Non-EFP X X















Scope


Effects





Workaround 1




Transmit Loop


Workaround 2



Workaround 3




Device A D

EFP - X

Non-EFP X X









Device A D

EFP -

Non-EFP X

26 Device




Device A D

EFP -

Non-EFP X




Device A D

EFP -

Non-EFP X




Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP -

Non-EFP X




Device A D

EFP -

Non-EFP X




Device A D

EFP -

Non-EFP X X





Device A D

EFP - X

Non-EFP X X







Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X





Device A D

EFP -

Non-EFP X






Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP -

Non-EFP X






Device A D

EFP -

Non-EFP X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X







Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP -

Non-EFP X




Device A D

EFP -

Non-EFP X



WorkaroundNone


Device A D

EFP -

Non-EFP X





WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Pseudo Code






Delay (10ms)



Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X



WorkaroundNone




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP -

Non-EFP X









Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X








Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X





WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X






Device A D

EFP - X

Non-EFP X X





0x1 50 ns to 100 ns 20 ns to 40 ns

0x2 300 ns to 600 ns 100 ns to 250 ns

0x3 400 ns to 800 ns 150 ns to 350 ns

WorkaroundNone


Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X








Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X






Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundsNone




Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X







Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP X X

Non-EFP X X
























LSBi12clk = 12 MHz









LSBi12clk = 12 MHz








































































Customer Support













SAM D5xE5x Family


Legal Notice


Trademarks








ISBN 978-1-5224-5227-0



SAM D5xE5x Family









Table of Contents







214 DMA Sequencing

215 DMA Sequencing


221 AC Hysteresis

222 Output








244 DAR Mode





26 Device




264 VBAT Mode




271 CRC32





284 LLAW






295 Reference








2121 Edge Detection















2172 COUNTSYNC




2176 Prescaler


















21817 Wakeup

21818 LENGTH









2213 ALOCK Feature



2221 X2 Mode







Customer Support


Legal Notice

Trademarks




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X











Scope


Effects


Workaround



Device A D

EFP - X

Non-EFP X X







Effects




Device A D

EFP - X

Non-EFP X X








Scope




Effects











Device A D

EFP - X

Non-EFP X X




Scope


Effects


WorkaroundNone


Device A D

EFP - X



continuedDevice A D

Non-EFP X X


Configuration A






Configuration B






Scope


Configuration A


Configuration B


Effects










Configuration B





Device A D

EFP - X

Non-EFP X X















Scope


Effects





Workaround 1




Transmit Loop


Workaround 2



Workaround 3




Device A D

EFP - X

Non-EFP X X









Device A D

EFP -

Non-EFP X

26 Device




Device A D

EFP -

Non-EFP X




Device A D

EFP -

Non-EFP X




Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP -

Non-EFP X




Device A D

EFP -

Non-EFP X




Device A D

EFP -

Non-EFP X X





Device A D

EFP - X

Non-EFP X X







Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X





Device A D

EFP -

Non-EFP X






Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP -

Non-EFP X






Device A D

EFP -

Non-EFP X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X







Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP -

Non-EFP X




Device A D

EFP -

Non-EFP X



WorkaroundNone


Device A D

EFP -

Non-EFP X





WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Pseudo Code






Delay (10ms)



Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X



WorkaroundNone




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP -

Non-EFP X









Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X








Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X





WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X






Device A D

EFP - X

Non-EFP X X





0x1 50 ns to 100 ns 20 ns to 40 ns

0x2 300 ns to 600 ns 100 ns to 250 ns

0x3 400 ns to 800 ns 150 ns to 350 ns

WorkaroundNone


Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X








Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X






Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundsNone




Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X







Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP X X

Non-EFP X X
























LSBi12clk = 12 MHz









LSBi12clk = 12 MHz








































































Customer Support













SAM D5xE5x Family


Legal Notice


Trademarks








ISBN 978-1-5224-5227-0



SAM D5xE5x Family









Table of Contents







214 DMA Sequencing

215 DMA Sequencing


221 AC Hysteresis

222 Output








244 DAR Mode





26 Device




264 VBAT Mode




271 CRC32





284 LLAW






295 Reference








2121 Edge Detection















2172 COUNTSYNC




2176 Prescaler


















21817 Wakeup

21818 LENGTH









2213 ALOCK Feature



2221 X2 Mode







Customer Support


Legal Notice

Trademarks




WorkaroundNone


Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X











Scope


Effects


Workaround



Device A D

EFP - X

Non-EFP X X







Effects




Device A D

EFP - X

Non-EFP X X








Scope




Effects











Device A D

EFP - X

Non-EFP X X




Scope


Effects


WorkaroundNone


Device A D

EFP - X



continuedDevice A D

Non-EFP X X


Configuration A






Configuration B






Scope


Configuration A


Configuration B


Effects










Configuration B





Device A D

EFP - X

Non-EFP X X















Scope


Effects





Workaround 1




Transmit Loop


Workaround 2



Workaround 3




Device A D

EFP - X

Non-EFP X X









Device A D

EFP -

Non-EFP X

26 Device




Device A D

EFP -

Non-EFP X




Device A D

EFP -

Non-EFP X




Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP -

Non-EFP X




Device A D

EFP -

Non-EFP X




Device A D

EFP -

Non-EFP X X





Device A D

EFP - X

Non-EFP X X







Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X





Device A D

EFP -

Non-EFP X






Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP -

Non-EFP X






Device A D

EFP -

Non-EFP X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X







Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP -

Non-EFP X




Device A D

EFP -

Non-EFP X



WorkaroundNone


Device A D

EFP -

Non-EFP X





WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Pseudo Code






Delay (10ms)



Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X



WorkaroundNone




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP -

Non-EFP X









Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X








Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X





WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X






Device A D

EFP - X

Non-EFP X X





0x1 50 ns to 100 ns 20 ns to 40 ns

0x2 300 ns to 600 ns 100 ns to 250 ns

0x3 400 ns to 800 ns 150 ns to 350 ns

WorkaroundNone


Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X








Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X






Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundsNone




Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X







Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP X X

Non-EFP X X
























LSBi12clk = 12 MHz









LSBi12clk = 12 MHz








































































Customer Support













SAM D5xE5x Family


Legal Notice


Trademarks








ISBN 978-1-5224-5227-0



SAM D5xE5x Family









Table of Contents







214 DMA Sequencing

215 DMA Sequencing


221 AC Hysteresis

222 Output








244 DAR Mode





26 Device




264 VBAT Mode




271 CRC32





284 LLAW






295 Reference








2121 Edge Detection















2172 COUNTSYNC




2176 Prescaler


















21817 Wakeup

21818 LENGTH









2213 ALOCK Feature



2221 X2 Mode







Customer Support


Legal Notice

Trademarks









Scope


Effects


Workaround



Device A D

EFP - X

Non-EFP X X







Effects




Device A D

EFP - X

Non-EFP X X








Scope




Effects











Device A D

EFP - X

Non-EFP X X




Scope


Effects


WorkaroundNone


Device A D

EFP - X



continuedDevice A D

Non-EFP X X


Configuration A






Configuration B






Scope


Configuration A


Configuration B


Effects










Configuration B





Device A D

EFP - X

Non-EFP X X















Scope


Effects





Workaround 1




Transmit Loop


Workaround 2



Workaround 3




Device A D

EFP - X

Non-EFP X X









Device A D

EFP -

Non-EFP X

26 Device




Device A D

EFP -

Non-EFP X




Device A D

EFP -

Non-EFP X




Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP -

Non-EFP X




Device A D

EFP -

Non-EFP X




Device A D

EFP -

Non-EFP X X





Device A D

EFP - X

Non-EFP X X







Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X





Device A D

EFP -

Non-EFP X






Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP -

Non-EFP X






Device A D

EFP -

Non-EFP X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X







Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP -

Non-EFP X




Device A D

EFP -

Non-EFP X



WorkaroundNone


Device A D

EFP -

Non-EFP X





WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Pseudo Code






Delay (10ms)



Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X



WorkaroundNone




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP -

Non-EFP X









Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X








Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X





WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X






Device A D

EFP - X

Non-EFP X X





0x1 50 ns to 100 ns 20 ns to 40 ns

0x2 300 ns to 600 ns 100 ns to 250 ns

0x3 400 ns to 800 ns 150 ns to 350 ns

WorkaroundNone


Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X








Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X






Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundsNone




Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X







Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP X X

Non-EFP X X
























LSBi12clk = 12 MHz









LSBi12clk = 12 MHz








































































Customer Support













SAM D5xE5x Family


Legal Notice


Trademarks








ISBN 978-1-5224-5227-0



SAM D5xE5x Family









Table of Contents







214 DMA Sequencing

215 DMA Sequencing


221 AC Hysteresis

222 Output








244 DAR Mode





26 Device




264 VBAT Mode




271 CRC32





284 LLAW






295 Reference








2121 Edge Detection















2172 COUNTSYNC




2176 Prescaler


















21817 Wakeup

21818 LENGTH









2213 ALOCK Feature



2221 X2 Mode







Customer Support


Legal Notice

Trademarks





Effects




Device A D

EFP - X

Non-EFP X X








Scope




Effects











Device A D

EFP - X

Non-EFP X X




Scope


Effects


WorkaroundNone


Device A D

EFP - X



continuedDevice A D

Non-EFP X X


Configuration A






Configuration B






Scope


Configuration A


Configuration B


Effects










Configuration B





Device A D

EFP - X

Non-EFP X X















Scope


Effects





Workaround 1




Transmit Loop


Workaround 2



Workaround 3




Device A D

EFP - X

Non-EFP X X









Device A D

EFP -

Non-EFP X

26 Device




Device A D

EFP -

Non-EFP X




Device A D

EFP -

Non-EFP X




Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP -

Non-EFP X




Device A D

EFP -

Non-EFP X




Device A D

EFP -

Non-EFP X X





Device A D

EFP - X

Non-EFP X X







Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X





Device A D

EFP -

Non-EFP X






Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP -

Non-EFP X






Device A D

EFP -

Non-EFP X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X







Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP -

Non-EFP X




Device A D

EFP -

Non-EFP X



WorkaroundNone


Device A D

EFP -

Non-EFP X





WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Pseudo Code






Delay (10ms)



Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X



WorkaroundNone




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP -

Non-EFP X









Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X








Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X





WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X






Device A D

EFP - X

Non-EFP X X





0x1 50 ns to 100 ns 20 ns to 40 ns

0x2 300 ns to 600 ns 100 ns to 250 ns

0x3 400 ns to 800 ns 150 ns to 350 ns

WorkaroundNone


Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X








Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X






Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundsNone




Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X







Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP X X

Non-EFP X X
























LSBi12clk = 12 MHz









LSBi12clk = 12 MHz








































































Customer Support













SAM D5xE5x Family


Legal Notice


Trademarks








ISBN 978-1-5224-5227-0



SAM D5xE5x Family









Table of Contents







214 DMA Sequencing

215 DMA Sequencing


221 AC Hysteresis

222 Output








244 DAR Mode





26 Device




264 VBAT Mode




271 CRC32





284 LLAW






295 Reference








2121 Edge Detection















2172 COUNTSYNC




2176 Prescaler


















21817 Wakeup

21818 LENGTH









2213 ALOCK Feature



2221 X2 Mode







Customer Support


Legal Notice

Trademarks







Device A D

EFP - X

Non-EFP X X




Scope


Effects


WorkaroundNone


Device A D

EFP - X



continuedDevice A D

Non-EFP X X


Configuration A






Configuration B






Scope


Configuration A


Configuration B


Effects










Configuration B





Device A D

EFP - X

Non-EFP X X















Scope


Effects





Workaround 1




Transmit Loop


Workaround 2



Workaround 3




Device A D

EFP - X

Non-EFP X X









Device A D

EFP -

Non-EFP X

26 Device




Device A D

EFP -

Non-EFP X




Device A D

EFP -

Non-EFP X




Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP -

Non-EFP X




Device A D

EFP -

Non-EFP X




Device A D

EFP -

Non-EFP X X





Device A D

EFP - X

Non-EFP X X







Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X





Device A D

EFP -

Non-EFP X






Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP -

Non-EFP X






Device A D

EFP -

Non-EFP X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X







Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP -

Non-EFP X




Device A D

EFP -

Non-EFP X



WorkaroundNone


Device A D

EFP -

Non-EFP X





WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Pseudo Code






Delay (10ms)



Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X



WorkaroundNone




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP -

Non-EFP X









Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X








Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X





WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X






Device A D

EFP - X

Non-EFP X X





0x1 50 ns to 100 ns 20 ns to 40 ns

0x2 300 ns to 600 ns 100 ns to 250 ns

0x3 400 ns to 800 ns 150 ns to 350 ns

WorkaroundNone


Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X








Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X






Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundsNone




Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X







Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP X X

Non-EFP X X
























LSBi12clk = 12 MHz









LSBi12clk = 12 MHz








































































Customer Support













SAM D5xE5x Family


Legal Notice


Trademarks








ISBN 978-1-5224-5227-0



SAM D5xE5x Family









Table of Contents







214 DMA Sequencing

215 DMA Sequencing


221 AC Hysteresis

222 Output








244 DAR Mode





26 Device




264 VBAT Mode




271 CRC32





284 LLAW






295 Reference








2121 Edge Detection















2172 COUNTSYNC




2176 Prescaler


















21817 Wakeup

21818 LENGTH









2213 ALOCK Feature



2221 X2 Mode







Customer Support


Legal Notice

Trademarks



continuedDevice A D

Non-EFP X X


Configuration A






Configuration B






Scope


Configuration A


Configuration B


Effects










Configuration B





Device A D

EFP - X

Non-EFP X X















Scope


Effects





Workaround 1




Transmit Loop


Workaround 2



Workaround 3




Device A D

EFP - X

Non-EFP X X









Device A D

EFP -

Non-EFP X

26 Device




Device A D

EFP -

Non-EFP X




Device A D

EFP -

Non-EFP X




Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP -

Non-EFP X




Device A D

EFP -

Non-EFP X




Device A D

EFP -

Non-EFP X X





Device A D

EFP - X

Non-EFP X X







Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X





Device A D

EFP -

Non-EFP X






Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP -

Non-EFP X






Device A D

EFP -

Non-EFP X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X







Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP -

Non-EFP X




Device A D

EFP -

Non-EFP X



WorkaroundNone


Device A D

EFP -

Non-EFP X





WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Pseudo Code






Delay (10ms)



Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X



WorkaroundNone




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP -

Non-EFP X









Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X








Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X





WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X






Device A D

EFP - X

Non-EFP X X





0x1 50 ns to 100 ns 20 ns to 40 ns

0x2 300 ns to 600 ns 100 ns to 250 ns

0x3 400 ns to 800 ns 150 ns to 350 ns

WorkaroundNone


Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X








Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X






Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundsNone




Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X







Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP X X

Non-EFP X X
























LSBi12clk = 12 MHz









LSBi12clk = 12 MHz








































































Customer Support













SAM D5xE5x Family


Legal Notice


Trademarks








ISBN 978-1-5224-5227-0



SAM D5xE5x Family









Table of Contents







214 DMA Sequencing

215 DMA Sequencing


221 AC Hysteresis

222 Output








244 DAR Mode





26 Device




264 VBAT Mode




271 CRC32





284 LLAW






295 Reference








2121 Edge Detection















2172 COUNTSYNC




2176 Prescaler


















21817 Wakeup

21818 LENGTH









2213 ALOCK Feature



2221 X2 Mode







Customer Support


Legal Notice

Trademarks





Configuration B





Device A D

EFP - X

Non-EFP X X















Scope


Effects





Workaround 1




Transmit Loop


Workaround 2



Workaround 3




Device A D

EFP - X

Non-EFP X X









Device A D

EFP -

Non-EFP X

26 Device




Device A D

EFP -

Non-EFP X




Device A D

EFP -

Non-EFP X




Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP -

Non-EFP X




Device A D

EFP -

Non-EFP X




Device A D

EFP -

Non-EFP X X





Device A D

EFP - X

Non-EFP X X







Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X





Device A D

EFP -

Non-EFP X






Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP -

Non-EFP X






Device A D

EFP -

Non-EFP X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X







Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP -

Non-EFP X




Device A D

EFP -

Non-EFP X



WorkaroundNone


Device A D

EFP -

Non-EFP X





WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Pseudo Code






Delay (10ms)



Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X



WorkaroundNone




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP -

Non-EFP X









Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X








Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X





WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X






Device A D

EFP - X

Non-EFP X X





0x1 50 ns to 100 ns 20 ns to 40 ns

0x2 300 ns to 600 ns 100 ns to 250 ns

0x3 400 ns to 800 ns 150 ns to 350 ns

WorkaroundNone


Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X








Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X






Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundsNone




Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X







Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP X X

Non-EFP X X
























LSBi12clk = 12 MHz









LSBi12clk = 12 MHz








































































Customer Support













SAM D5xE5x Family


Legal Notice


Trademarks








ISBN 978-1-5224-5227-0



SAM D5xE5x Family









Table of Contents







214 DMA Sequencing

215 DMA Sequencing


221 AC Hysteresis

222 Output








244 DAR Mode





26 Device




264 VBAT Mode




271 CRC32





284 LLAW






295 Reference








2121 Edge Detection















2172 COUNTSYNC




2176 Prescaler


















21817 Wakeup

21818 LENGTH









2213 ALOCK Feature



2221 X2 Mode







Customer Support


Legal Notice

Trademarks





Workaround 1




Transmit Loop


Workaround 2



Workaround 3




Device A D

EFP - X

Non-EFP X X









Device A D

EFP -

Non-EFP X

26 Device




Device A D

EFP -

Non-EFP X




Device A D

EFP -

Non-EFP X




Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP -

Non-EFP X




Device A D

EFP -

Non-EFP X




Device A D

EFP -

Non-EFP X X





Device A D

EFP - X

Non-EFP X X







Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X





Device A D

EFP -

Non-EFP X






Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP -

Non-EFP X






Device A D

EFP -

Non-EFP X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X







Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP -

Non-EFP X




Device A D

EFP -

Non-EFP X



WorkaroundNone


Device A D

EFP -

Non-EFP X





WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Pseudo Code






Delay (10ms)



Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X



WorkaroundNone




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP -

Non-EFP X









Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X








Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X





WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X






Device A D

EFP - X

Non-EFP X X





0x1 50 ns to 100 ns 20 ns to 40 ns

0x2 300 ns to 600 ns 100 ns to 250 ns

0x3 400 ns to 800 ns 150 ns to 350 ns

WorkaroundNone


Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X








Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X






Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundsNone




Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X







Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP X X

Non-EFP X X
























LSBi12clk = 12 MHz









LSBi12clk = 12 MHz








































































Customer Support













SAM D5xE5x Family


Legal Notice


Trademarks








ISBN 978-1-5224-5227-0



SAM D5xE5x Family









Table of Contents







214 DMA Sequencing

215 DMA Sequencing


221 AC Hysteresis

222 Output








244 DAR Mode





26 Device




264 VBAT Mode




271 CRC32





284 LLAW






295 Reference








2121 Edge Detection















2172 COUNTSYNC




2176 Prescaler


















21817 Wakeup

21818 LENGTH









2213 ALOCK Feature



2221 X2 Mode







Customer Support


Legal Notice

Trademarks




Device A D

EFP -

Non-EFP X

26 Device




Device A D

EFP -

Non-EFP X




Device A D

EFP -

Non-EFP X




Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP -

Non-EFP X




Device A D

EFP -

Non-EFP X




Device A D

EFP -

Non-EFP X X





Device A D

EFP - X

Non-EFP X X







Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X





Device A D

EFP -

Non-EFP X






Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP -

Non-EFP X






Device A D

EFP -

Non-EFP X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X







Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP -

Non-EFP X




Device A D

EFP -

Non-EFP X



WorkaroundNone


Device A D

EFP -

Non-EFP X





WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Pseudo Code






Delay (10ms)



Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X



WorkaroundNone




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP -

Non-EFP X









Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X








Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X





WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X






Device A D

EFP - X

Non-EFP X X





0x1 50 ns to 100 ns 20 ns to 40 ns

0x2 300 ns to 600 ns 100 ns to 250 ns

0x3 400 ns to 800 ns 150 ns to 350 ns

WorkaroundNone


Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X








Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X






Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundsNone




Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X







Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP X X

Non-EFP X X
























LSBi12clk = 12 MHz









LSBi12clk = 12 MHz








































































Customer Support













SAM D5xE5x Family


Legal Notice


Trademarks








ISBN 978-1-5224-5227-0



SAM D5xE5x Family









Table of Contents







214 DMA Sequencing

215 DMA Sequencing


221 AC Hysteresis

222 Output








244 DAR Mode





26 Device




264 VBAT Mode




271 CRC32





284 LLAW






295 Reference








2121 Edge Detection















2172 COUNTSYNC




2176 Prescaler


















21817 Wakeup

21818 LENGTH









2213 ALOCK Feature



2221 X2 Mode







Customer Support


Legal Notice

Trademarks



WorkaroundNone


Device A D

EFP -

Non-EFP X




Device A D

EFP -

Non-EFP X




Device A D

EFP -

Non-EFP X X





Device A D

EFP - X

Non-EFP X X







Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X





Device A D

EFP -

Non-EFP X






Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP -

Non-EFP X






Device A D

EFP -

Non-EFP X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X







Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP -

Non-EFP X




Device A D

EFP -

Non-EFP X



WorkaroundNone


Device A D

EFP -

Non-EFP X





WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Pseudo Code






Delay (10ms)



Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X



WorkaroundNone




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP -

Non-EFP X









Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X








Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X





WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X






Device A D

EFP - X

Non-EFP X X





0x1 50 ns to 100 ns 20 ns to 40 ns

0x2 300 ns to 600 ns 100 ns to 250 ns

0x3 400 ns to 800 ns 150 ns to 350 ns

WorkaroundNone


Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X








Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X






Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundsNone




Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X







Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP X X

Non-EFP X X
























LSBi12clk = 12 MHz









LSBi12clk = 12 MHz








































































Customer Support













SAM D5xE5x Family


Legal Notice


Trademarks








ISBN 978-1-5224-5227-0



SAM D5xE5x Family









Table of Contents







214 DMA Sequencing

215 DMA Sequencing


221 AC Hysteresis

222 Output








244 DAR Mode





26 Device




264 VBAT Mode




271 CRC32





284 LLAW






295 Reference








2121 Edge Detection















2172 COUNTSYNC




2176 Prescaler


















21817 Wakeup

21818 LENGTH









2213 ALOCK Feature



2221 X2 Mode







Customer Support


Legal Notice

Trademarks







Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X





Device A D

EFP -

Non-EFP X






Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP -

Non-EFP X






Device A D

EFP -

Non-EFP X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X







Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP -

Non-EFP X




Device A D

EFP -

Non-EFP X



WorkaroundNone


Device A D

EFP -

Non-EFP X





WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Pseudo Code






Delay (10ms)



Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X



WorkaroundNone




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP -

Non-EFP X









Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X








Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X





WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X






Device A D

EFP - X

Non-EFP X X





0x1 50 ns to 100 ns 20 ns to 40 ns

0x2 300 ns to 600 ns 100 ns to 250 ns

0x3 400 ns to 800 ns 150 ns to 350 ns

WorkaroundNone


Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X








Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X






Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundsNone




Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X







Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP X X

Non-EFP X X
























LSBi12clk = 12 MHz









LSBi12clk = 12 MHz








































































Customer Support













SAM D5xE5x Family


Legal Notice


Trademarks








ISBN 978-1-5224-5227-0



SAM D5xE5x Family









Table of Contents







214 DMA Sequencing

215 DMA Sequencing


221 AC Hysteresis

222 Output








244 DAR Mode





26 Device




264 VBAT Mode




271 CRC32





284 LLAW






295 Reference








2121 Edge Detection















2172 COUNTSYNC




2176 Prescaler


















21817 Wakeup

21818 LENGTH









2213 ALOCK Feature



2221 X2 Mode







Customer Support


Legal Notice

Trademarks






Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP -

Non-EFP X






Device A D

EFP -

Non-EFP X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X







Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP -

Non-EFP X




Device A D

EFP -

Non-EFP X



WorkaroundNone


Device A D

EFP -

Non-EFP X





WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Pseudo Code






Delay (10ms)



Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X



WorkaroundNone




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP -

Non-EFP X









Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X








Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X





WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X






Device A D

EFP - X

Non-EFP X X





0x1 50 ns to 100 ns 20 ns to 40 ns

0x2 300 ns to 600 ns 100 ns to 250 ns

0x3 400 ns to 800 ns 150 ns to 350 ns

WorkaroundNone


Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X








Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X






Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundsNone




Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X







Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP X X

Non-EFP X X
























LSBi12clk = 12 MHz









LSBi12clk = 12 MHz








































































Customer Support













SAM D5xE5x Family


Legal Notice


Trademarks








ISBN 978-1-5224-5227-0



SAM D5xE5x Family









Table of Contents







214 DMA Sequencing

215 DMA Sequencing


221 AC Hysteresis

222 Output








244 DAR Mode





26 Device




264 VBAT Mode




271 CRC32





284 LLAW






295 Reference








2121 Edge Detection















2172 COUNTSYNC




2176 Prescaler


















21817 Wakeup

21818 LENGTH









2213 ALOCK Feature



2221 X2 Mode







Customer Support


Legal Notice

Trademarks




Device A D

EFP -

Non-EFP X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X







Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP -

Non-EFP X




Device A D

EFP -

Non-EFP X



WorkaroundNone


Device A D

EFP -

Non-EFP X





WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Pseudo Code






Delay (10ms)



Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X



WorkaroundNone




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP -

Non-EFP X









Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X








Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X





WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X






Device A D

EFP - X

Non-EFP X X





0x1 50 ns to 100 ns 20 ns to 40 ns

0x2 300 ns to 600 ns 100 ns to 250 ns

0x3 400 ns to 800 ns 150 ns to 350 ns

WorkaroundNone


Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X








Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X






Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundsNone




Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X







Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP X X

Non-EFP X X
























LSBi12clk = 12 MHz









LSBi12clk = 12 MHz








































































Customer Support













SAM D5xE5x Family


Legal Notice


Trademarks








ISBN 978-1-5224-5227-0



SAM D5xE5x Family









Table of Contents







214 DMA Sequencing

215 DMA Sequencing


221 AC Hysteresis

222 Output








244 DAR Mode





26 Device




264 VBAT Mode




271 CRC32





284 LLAW






295 Reference








2121 Edge Detection















2172 COUNTSYNC




2176 Prescaler


















21817 Wakeup

21818 LENGTH









2213 ALOCK Feature



2221 X2 Mode







Customer Support


Legal Notice

Trademarks




Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP -

Non-EFP X




Device A D

EFP -

Non-EFP X



WorkaroundNone


Device A D

EFP -

Non-EFP X





WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Pseudo Code






Delay (10ms)



Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X



WorkaroundNone




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP -

Non-EFP X









Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X








Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X





WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X






Device A D

EFP - X

Non-EFP X X





0x1 50 ns to 100 ns 20 ns to 40 ns

0x2 300 ns to 600 ns 100 ns to 250 ns

0x3 400 ns to 800 ns 150 ns to 350 ns

WorkaroundNone


Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X








Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X






Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundsNone




Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X







Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP X X

Non-EFP X X
























LSBi12clk = 12 MHz









LSBi12clk = 12 MHz








































































Customer Support













SAM D5xE5x Family


Legal Notice


Trademarks








ISBN 978-1-5224-5227-0



SAM D5xE5x Family









Table of Contents







214 DMA Sequencing

215 DMA Sequencing


221 AC Hysteresis

222 Output








244 DAR Mode





26 Device




264 VBAT Mode




271 CRC32





284 LLAW






295 Reference








2121 Edge Detection















2172 COUNTSYNC




2176 Prescaler


















21817 Wakeup

21818 LENGTH









2213 ALOCK Feature



2221 X2 Mode







Customer Support


Legal Notice

Trademarks





WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Pseudo Code






Delay (10ms)



Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X



WorkaroundNone




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP -

Non-EFP X









Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X








Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X





WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X






Device A D

EFP - X

Non-EFP X X





0x1 50 ns to 100 ns 20 ns to 40 ns

0x2 300 ns to 600 ns 100 ns to 250 ns

0x3 400 ns to 800 ns 150 ns to 350 ns

WorkaroundNone


Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X








Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X






Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundsNone




Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X







Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP X X

Non-EFP X X
























LSBi12clk = 12 MHz









LSBi12clk = 12 MHz








































































Customer Support













SAM D5xE5x Family


Legal Notice


Trademarks








ISBN 978-1-5224-5227-0



SAM D5xE5x Family









Table of Contents







214 DMA Sequencing

215 DMA Sequencing


221 AC Hysteresis

222 Output








244 DAR Mode





26 Device




264 VBAT Mode




271 CRC32





284 LLAW






295 Reference








2121 Edge Detection















2172 COUNTSYNC




2176 Prescaler


















21817 Wakeup

21818 LENGTH









2213 ALOCK Feature



2221 X2 Mode







Customer Support


Legal Notice

Trademarks




Delay (10ms)



Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X



WorkaroundNone




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP -

Non-EFP X









Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X








Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X





WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X






Device A D

EFP - X

Non-EFP X X





0x1 50 ns to 100 ns 20 ns to 40 ns

0x2 300 ns to 600 ns 100 ns to 250 ns

0x3 400 ns to 800 ns 150 ns to 350 ns

WorkaroundNone


Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X








Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X






Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundsNone




Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X







Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP X X

Non-EFP X X
























LSBi12clk = 12 MHz









LSBi12clk = 12 MHz








































































Customer Support













SAM D5xE5x Family


Legal Notice


Trademarks








ISBN 978-1-5224-5227-0



SAM D5xE5x Family









Table of Contents







214 DMA Sequencing

215 DMA Sequencing


221 AC Hysteresis

222 Output








244 DAR Mode





26 Device




264 VBAT Mode




271 CRC32





284 LLAW






295 Reference








2121 Edge Detection















2172 COUNTSYNC




2176 Prescaler


















21817 Wakeup

21818 LENGTH









2213 ALOCK Feature



2221 X2 Mode







Customer Support


Legal Notice

Trademarks




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP -

Non-EFP X









Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X








Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X





WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X






Device A D

EFP - X

Non-EFP X X





0x1 50 ns to 100 ns 20 ns to 40 ns

0x2 300 ns to 600 ns 100 ns to 250 ns

0x3 400 ns to 800 ns 150 ns to 350 ns

WorkaroundNone


Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X








Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X






Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundsNone




Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X







Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP X X

Non-EFP X X
























LSBi12clk = 12 MHz









LSBi12clk = 12 MHz








































































Customer Support













SAM D5xE5x Family


Legal Notice


Trademarks








ISBN 978-1-5224-5227-0



SAM D5xE5x Family









Table of Contents







214 DMA Sequencing

215 DMA Sequencing


221 AC Hysteresis

222 Output








244 DAR Mode





26 Device




264 VBAT Mode




271 CRC32





284 LLAW






295 Reference








2121 Edge Detection















2172 COUNTSYNC




2176 Prescaler


















21817 Wakeup

21818 LENGTH









2213 ALOCK Feature



2221 X2 Mode







Customer Support


Legal Notice

Trademarks









Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X








Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X





WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X






Device A D

EFP - X

Non-EFP X X





0x1 50 ns to 100 ns 20 ns to 40 ns

0x2 300 ns to 600 ns 100 ns to 250 ns

0x3 400 ns to 800 ns 150 ns to 350 ns

WorkaroundNone


Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X








Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X






Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundsNone




Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X







Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP X X

Non-EFP X X
























LSBi12clk = 12 MHz









LSBi12clk = 12 MHz








































































Customer Support













SAM D5xE5x Family


Legal Notice


Trademarks








ISBN 978-1-5224-5227-0



SAM D5xE5x Family









Table of Contents







214 DMA Sequencing

215 DMA Sequencing


221 AC Hysteresis

222 Output








244 DAR Mode





26 Device




264 VBAT Mode




271 CRC32





284 LLAW






295 Reference








2121 Edge Detection















2172 COUNTSYNC




2176 Prescaler


















21817 Wakeup

21818 LENGTH









2213 ALOCK Feature



2221 X2 Mode







Customer Support


Legal Notice

Trademarks







Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X





WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X






Device A D

EFP - X

Non-EFP X X





0x1 50 ns to 100 ns 20 ns to 40 ns

0x2 300 ns to 600 ns 100 ns to 250 ns

0x3 400 ns to 800 ns 150 ns to 350 ns

WorkaroundNone


Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X








Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X






Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundsNone




Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X







Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP X X

Non-EFP X X
























LSBi12clk = 12 MHz









LSBi12clk = 12 MHz








































































Customer Support













SAM D5xE5x Family


Legal Notice


Trademarks








ISBN 978-1-5224-5227-0



SAM D5xE5x Family









Table of Contents







214 DMA Sequencing

215 DMA Sequencing


221 AC Hysteresis

222 Output








244 DAR Mode





26 Device




264 VBAT Mode




271 CRC32





284 LLAW






295 Reference








2121 Edge Detection















2172 COUNTSYNC




2176 Prescaler


















21817 Wakeup

21818 LENGTH









2213 ALOCK Feature



2221 X2 Mode







Customer Support


Legal Notice

Trademarks



WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X






Device A D

EFP - X

Non-EFP X X





0x1 50 ns to 100 ns 20 ns to 40 ns

0x2 300 ns to 600 ns 100 ns to 250 ns

0x3 400 ns to 800 ns 150 ns to 350 ns

WorkaroundNone


Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X








Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X






Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundsNone




Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X







Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP X X

Non-EFP X X
























LSBi12clk = 12 MHz









LSBi12clk = 12 MHz








































































Customer Support













SAM D5xE5x Family


Legal Notice


Trademarks








ISBN 978-1-5224-5227-0



SAM D5xE5x Family









Table of Contents







214 DMA Sequencing

215 DMA Sequencing


221 AC Hysteresis

222 Output








244 DAR Mode





26 Device




264 VBAT Mode




271 CRC32





284 LLAW






295 Reference








2121 Edge Detection















2172 COUNTSYNC




2176 Prescaler


















21817 Wakeup

21818 LENGTH









2213 ALOCK Feature



2221 X2 Mode







Customer Support


Legal Notice

Trademarks






Device A D

EFP - X

Non-EFP X X





0x1 50 ns to 100 ns 20 ns to 40 ns

0x2 300 ns to 600 ns 100 ns to 250 ns

0x3 400 ns to 800 ns 150 ns to 350 ns

WorkaroundNone


Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X








Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X






Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundsNone




Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X







Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP X X

Non-EFP X X
























LSBi12clk = 12 MHz









LSBi12clk = 12 MHz








































































Customer Support













SAM D5xE5x Family


Legal Notice


Trademarks








ISBN 978-1-5224-5227-0



SAM D5xE5x Family









Table of Contents







214 DMA Sequencing

215 DMA Sequencing


221 AC Hysteresis

222 Output








244 DAR Mode





26 Device




264 VBAT Mode




271 CRC32





284 LLAW






295 Reference








2121 Edge Detection















2172 COUNTSYNC




2176 Prescaler


















21817 Wakeup

21818 LENGTH









2213 ALOCK Feature



2221 X2 Mode







Customer Support


Legal Notice

Trademarks



WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X








Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X






Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundsNone




Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X







Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP X X

Non-EFP X X
























LSBi12clk = 12 MHz









LSBi12clk = 12 MHz








































































Customer Support













SAM D5xE5x Family


Legal Notice


Trademarks








ISBN 978-1-5224-5227-0



SAM D5xE5x Family









Table of Contents







214 DMA Sequencing

215 DMA Sequencing


221 AC Hysteresis

222 Output








244 DAR Mode





26 Device




264 VBAT Mode




271 CRC32





284 LLAW






295 Reference








2121 Edge Detection















2172 COUNTSYNC




2176 Prescaler


















21817 Wakeup

21818 LENGTH









2213 ALOCK Feature



2221 X2 Mode







Customer Support


Legal Notice

Trademarks








Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X






Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundsNone




Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X







Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP X X

Non-EFP X X
























LSBi12clk = 12 MHz









LSBi12clk = 12 MHz








































































Customer Support













SAM D5xE5x Family


Legal Notice


Trademarks








ISBN 978-1-5224-5227-0



SAM D5xE5x Family









Table of Contents







214 DMA Sequencing

215 DMA Sequencing


221 AC Hysteresis

222 Output








244 DAR Mode





26 Device




264 VBAT Mode




271 CRC32





284 LLAW






295 Reference








2121 Edge Detection















2172 COUNTSYNC




2176 Prescaler


















21817 Wakeup

21818 LENGTH









2213 ALOCK Feature



2221 X2 Mode







Customer Support


Legal Notice

Trademarks






Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundsNone




Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X







Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP X X

Non-EFP X X
























LSBi12clk = 12 MHz









LSBi12clk = 12 MHz








































































Customer Support













SAM D5xE5x Family


Legal Notice


Trademarks








ISBN 978-1-5224-5227-0



SAM D5xE5x Family









Table of Contents







214 DMA Sequencing

215 DMA Sequencing


221 AC Hysteresis

222 Output








244 DAR Mode





26 Device




264 VBAT Mode




271 CRC32





284 LLAW






295 Reference








2121 Edge Detection















2172 COUNTSYNC




2176 Prescaler


















21817 Wakeup

21818 LENGTH









2213 ALOCK Feature



2221 X2 Mode







Customer Support


Legal Notice

Trademarks




Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X







Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP X X

Non-EFP X X
























LSBi12clk = 12 MHz









LSBi12clk = 12 MHz








































































Customer Support













SAM D5xE5x Family


Legal Notice


Trademarks








ISBN 978-1-5224-5227-0



SAM D5xE5x Family









Table of Contents







214 DMA Sequencing

215 DMA Sequencing


221 AC Hysteresis

222 Output








244 DAR Mode





26 Device




264 VBAT Mode




271 CRC32





284 LLAW






295 Reference








2121 Edge Detection















2172 COUNTSYNC




2176 Prescaler


















21817 Wakeup

21818 LENGTH









2213 ALOCK Feature



2221 X2 Mode







Customer Support


Legal Notice

Trademarks




Device A D

EFP - X

Non-EFP X X





Device A D

EFP - X

Non-EFP X X




Device A D

EFP - X

Non-EFP X X


WorkaroundNone


Device A D

EFP - X

Non-EFP X X




WorkaroundNone


Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP X X

Non-EFP X X
























LSBi12clk = 12 MHz









LSBi12clk = 12 MHz








































































Customer Support













SAM D5xE5x Family


Legal Notice


Trademarks








ISBN 978-1-5224-5227-0



SAM D5xE5x Family









Table of Contents







214 DMA Sequencing

215 DMA Sequencing


221 AC Hysteresis

222 Output








244 DAR Mode





26 Device




264 VBAT Mode




271 CRC32





284 LLAW






295 Reference








2121 Edge Detection















2172 COUNTSYNC




2176 Prescaler


















21817 Wakeup

21818 LENGTH









2213 ALOCK Feature



2221 X2 Mode







Customer Support


Legal Notice

Trademarks



WorkaroundNone


Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP - X

Non-EFP X X



WorkaroundNone


Device A D

EFP X X

Non-EFP X X
























LSBi12clk = 12 MHz









LSBi12clk = 12 MHz








































































Customer Support













SAM D5xE5x Family


Legal Notice


Trademarks








ISBN 978-1-5224-5227-0



SAM D5xE5x Family









Table of Contents







214 DMA Sequencing

215 DMA Sequencing


221 AC Hysteresis

222 Output








244 DAR Mode





26 Device




264 VBAT Mode




271 CRC32





284 LLAW






295 Reference








2121 Edge Detection















2172 COUNTSYNC




2176 Prescaler


















21817 Wakeup

21818 LENGTH









2213 ALOCK Feature



2221 X2 Mode







Customer Support


Legal Notice

Trademarks
























LSBi12clk = 12 MHz









LSBi12clk = 12 MHz








































































Customer Support













SAM D5xE5x Family


Legal Notice


Trademarks








ISBN 978-1-5224-5227-0



SAM D5xE5x Family









Table of Contents







214 DMA Sequencing

215 DMA Sequencing


221 AC Hysteresis

222 Output








244 DAR Mode





26 Device




264 VBAT Mode




271 CRC32





284 LLAW






295 Reference








2121 Edge Detection















2172 COUNTSYNC




2176 Prescaler


















21817 Wakeup

21818 LENGTH









2213 ALOCK Feature



2221 X2 Mode







Customer Support


Legal Notice

Trademarks






































































Customer Support













SAM D5xE5x Family


Legal Notice


Trademarks








ISBN 978-1-5224-5227-0



SAM D5xE5x Family









Table of Contents







214 DMA Sequencing

215 DMA Sequencing


221 AC Hysteresis

222 Output








244 DAR Mode





26 Device




264 VBAT Mode




271 CRC32





284 LLAW






295 Reference








2121 Edge Detection















2172 COUNTSYNC




2176 Prescaler


















21817 Wakeup

21818 LENGTH









2213 ALOCK Feature



2221 X2 Mode







Customer Support


Legal Notice

Trademarks



Legal Notice


Trademarks








ISBN 978-1-5224-5227-0



SAM D5xE5x Family









Table of Contents







214 DMA Sequencing

215 DMA Sequencing


221 AC Hysteresis

222 Output








244 DAR Mode





26 Device




264 VBAT Mode




271 CRC32





284 LLAW






295 Reference








2121 Edge Detection















2172 COUNTSYNC




2176 Prescaler


















21817 Wakeup

21818 LENGTH









2213 ALOCK Feature



2221 X2 Mode







Customer Support


Legal Notice

Trademarks










Table of Contents







214 DMA Sequencing

215 DMA Sequencing


221 AC Hysteresis

222 Output








244 DAR Mode





26 Device




264 VBAT Mode




271 CRC32





284 LLAW






295 Reference








2121 Edge Detection















2172 COUNTSYNC




2176 Prescaler


















21817 Wakeup

21818 LENGTH









2213 ALOCK Feature



2221 X2 Mode







Customer Support


Legal Notice

Trademarks



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