Sample & Hold Circuits Sample & Hold Circuits

Insoo Kim, Kyusun ChoiMixed Signal CHIP Design Lab.Department of Computer Science & EngineeringThe Pennsylvania State University

CSE598A/EE597G Spring 2006

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Basic Sample and Hold Circuit ConfigurationBasic Sample and Hold Circuit Configuration Concept

MOSFET S&H Circuit

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Design Issues of CMOS S&HDesign Issues of CMOS S&H Sampling Moment Distortion

Finite Clock rising/falling time results in distortion

Clock Feed-through Overlap cap. of MOS Switch creates

an sampling error during clock transition time

MOS Switch Charge Injection Some charge in the MOS channel flow

to Source and Drain, then result in an error.

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HholdThGSox C

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Solutions for Reducing Sampling DistortionSolutions for Reducing Sampling Distortion Differential S&H Circuit

Sample Clock Bootstrapping Sampling distortion can be reduced by increasing clock

amplitude

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Sample Clock Bootstrap Circuits (I)Sample Clock Bootstrap Circuits (I) Basic clock bootstrap circuit

Simulation Result

Booted Clock

Clock

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Sample Clock Bootstrap Circuits (II)Sample Clock Bootstrap Circuits (II) Differential sampling clock bootstrap circuit

Simulation Result

Differential Sampling Booted Clock

Clock

Single sampling booted Clock

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Signal Dependent Clock Bootstrapping (I)Signal Dependent Clock Bootstrapping (I) The problem of clock bootstrap circuit

Vgs of MOS switch can vary according to the input voltage level Ron of MOS Switch also vary It can cause an error in holding voltage

Signal Dependent clock bootstrap circuit

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Signal Dependent Clock Bootstrapping (II)Signal Dependent Clock Bootstrapping (II) Modified Circuit

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Low Signal Feed-through SwitchLow Signal Feed-through Switch Schematic

Simulation Result

Offset: 30 mV

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Charge injection Compensation Switch (I)Charge injection Compensation Switch (I)

Vin Vout

Simulation Result

Offset: 2.5 mV

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Charge injection Compensation Switch (II)Charge injection Compensation Switch (II)

Vin Vout

Simulation Result

Offset: 0.72 mV

Actual Implementation S&H Actual Implementation S&H CircuitsCircuits

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Double Buffered S&H ConfigurationDouble Buffered S&H Configuration

Advantages:

- Obtain a low droop rate during holding mode

- Stability is determined by the stabilities of OP Amps

Disadvantages:

- OP Amps offset can constrain the accuracy of SHA

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Double Buffered S&H Circuit with CMOS SwitchDouble Buffered S&H Circuit with CMOS Switch Schematic

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Double Buffered S&H Circuit with CMOS SwitchDouble Buffered S&H Circuit with CMOS Switch Simulation Result

Input Output

VSS (-1.65V)

VDD (1.65V)

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Feedback Improved S&H CircuitFeedback Improved S&H Circuit

Advantages:

- Offset free More accurate than double buffered SHA

Disadvantages:

- Common Mode Rejection of the Input OP amp must be high

- Special Care must be taken to obtain stability of SHA

- Needs a special circuitry to stabilize the input amplifier during the holding mode

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(cont’d) Feedback Improved S&H Circuit(cont’d) Feedback Improved S&H Circuit

Simple stabilization circuit for input amplifier

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(cont’d) Feedback Improved S&H Circuit(cont’d) Feedback Improved S&H Circuit

Simulation Result

Feedback improved S&H w/o input amp stabilization

Feedback improved S&H with input amp stabilization

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Integrating S&H CircuitIntegrating S&H Circuit

Advantages:

- Switching moment and charge feed-through can be controlled very well

Disadvantages:

- Common Mode Rejection of the Input OP amp must be high

- Special Care must be taken to obtain stability of SHA

- Needs a special circuitry to stabilize the input amplifier during the holding mode

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S&H Circuit using Miller Cap.S&H Circuit using Miller Cap.

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Switched Capacitor S&H CircuitSwitched Capacitor S&H Circuit Basic Configuration

Common implementation for pipelined ADCs

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ReferencesReferences Rudy van de Plassche, “CMOS Integrated Analog-to-

Digital and Digital-to-Analog Converters- 2nd Edition,” Kluwer Academic Publishers, 2003.

B. Razavi, “Principles of Data Conversion System Design,” IEEE Press, 1995.