sbc312 hardware reference manual

GE Intelligent Platforms

Hardware Reference Manual SBC312 3U VPX Single Board Computer Edition 1 Publication No. SBC312-HRM/1

2 SBC312 3U VPX Single Board Computer Publication No. SBC312-HRM/1

Document History

Edition Date Board Artwork Revision

1 November 2010 Rev 1

Waste Electrical and Electronic Equipment (WEEE) Returns

GE Intelligent Platforms Limited is registered with an approved Producer Compliance Scheme (PCS) and, subject to suitable contractual arrangements being in place, will ensure WEEE is processed in accordance with the requirements of the WEEE Directive.

GE Intelligent Platforms Limited will evaluate requests to take back products purchased by our customers before August 13, 2005 on a case by case basis. A WEEE management fee may apply.

Publication No. SBC312-HRM/1 About this Manual 3

About this Manual

Conventions

Numbers Allnumbersareexpressedindecimal,exceptaddressesandmemoryorregisterdata,whichareexpressedinhexadecimal.Whereconfusionmayoccur,decimalnumbershaveaDsubscriptandbinarynumbershaveabsubscript.Theprefix0xshowsahexadecimalnumber,followingtheCprogramminglanguageconvention.Thus:

Onedozen=12D=0x0C=1100b

Themultipliersk,MandGhavetheirconventionalscientificandengineeringmeaningsof*103,*106and*109respectively.Theonlyexceptiontothisisinthedescriptionofthesizeofmemoryareas,whenK,MandGmean*210,*220and*230respectively.

NOTE When describing transfer rates, k, M and G mean *103, *106 and *109 not *210, *220 and *230.

InPowerPCterminology,multiplebitfieldsarenumberedfrom0tonwhere0istheMSBandntheLSB.PCIterminologyfollowsthemorefamiliarconventionthatbit0istheLSBandntheMSB.

Text Signalnamesendingwithatilde(~)ordenoteactivelowsignals;allothersignalsareactivehigh.NandPdenotethelowandhighcomponentsofadifferentialsignalrespectively.

Notices Thismanualusesthefollowingtypesofnotice:

NOTE Notes call attention to important features or instructions.

WARNING Warnings alert you to the risk of severe personal injury.

CAUTION Cautions alert you to system danger or loss of data.

TIP Tips give guidance on procedures that may be tackled in a number of ways.

LINK Links go to other documents or websites. The purple link color may also be used within a body of text or paragraph to indicate a link (or hyperlink) to a different part of the same document.


Further Information

GE Intelligent Platforms Documents ThisdocumentisdistributedviaCDROMandtheinternet.TheCDROMallowsprivilegedaccesstoanInternetresourcecontainingthelatestupdateddocuments.Alternatively,youmayregisterforaccesstoallmanualsviathewebsitewhoselinkisgivenbelow.

LINKS PMC Installation Application Note, publication number HN4/2-99.

VPX I/O Modules Hardware Reference Manual, publication number VPXIOM-0HH.

AXISFlow Programmers Guide, publication number AXISFLOW-0HU.

Radstone Signal Processing Library Manual, publication number RSPL-0HL.

Vector Signal and Image Processing Library Manual, publication number VSIPL-0HL.

AXISView Applications Software User Guide, publication number AXISVIEW-0HU.

Third Party Documents DuetothecomplexityofsomeofthepartsusedontheSBC312,itisnotpossibletoincludethedetaileddataonallsuchdevicesinthismanual.Alistofthespecificationsanddatasheetsthatprovideanyadditionalinformationrequiredfollows:

Specifications IEEE1101.11998 IEEEStandardforMechanicalCoreSpecificationsforMicrocomputers.

IEEE1101.21992 ConductioncooledVMEmechanics.

IEEE1101.101996 AdditionalMechanicalSpecifications.

IEEEP1386.12001 StandardPhysicalandEnvironmentalLayersforPCIMezzanineCards:PMC.

ANSI/VITA202001 ConductionCooledPMC.

ANSI/VITA322003 ProcessorPMC.

ANSI/VITA392003 PCIXforPMCandProcessorPMC.

ANSI/VITA42.02008 XMC.

ANSI/VITA42.32006 XMCPCIExpressProtocolLayerStandard.

ANSI/VITA46.02007 VPXBaseStandard.

VITA46.4(Draft) PCIExpressonVPX.

VITA46.9(Draft) XMCandPMCUserI/OMappingforVPX.

VITA46.11(Draft) SystemManagementonVPX.

ANSI/VITA652010 OpenVPXSystemSpecification.

PCILocalBusSpecificationRevision2.1,PCISpecialInterestGroup.

Publication No. SBC312-HRM/1 About this Manual 5

Thesearethelatestversionsattimeofwriting;checkassociatedwebsitesforlaterupdates.

NOTE Registration may be required for access to these specifications.

QorIQP4080IntegratedProcessorHardwareSpecifications,FreescaleSemiconductor.

Component Information

P4080QorIQIntegratedMulticoreCommunicationProcessorReferenceManual,FreescaleSemiconductor.

AnIntroductiontotheQorIQPlatformsTrustArchitecture,FreescaleSemiconductor.

StandardforPhysicalConnectionforHighSpeedSerialTrace,Power.org.

89HPES32NT24xG2PCIExpressSwitchUserManual,IDT.

LatticeSemiconductorReferenceDesign1011UniversalAsynchronousReceiver/Transmitter.

NOTE Access to these documents may require a Non-Disclosure Agreement to be in place with the component vendor. Contact the manufacturer for more information.

GE Web Site InformationregardingallGEIntelligentPlatformsproductscanbefoundonthefollowingwebsite:

LINK http://www.ge-ip.com/products/family/embedded-systems/

Third Party Web Sites ManufacturersofmanyofthedevicesusedontheSBC312maintainFTPorwebsites.Someusefulsitesare:

http://www.vita.com ForVITAandANSI/VITAstandards.http://www.ieee.com ForIEEEstandards.http://www.pcisig.org ForPCIBusstandards.http://www.freescale.com/ ForP4080processorinformation.http://www.idt.com/ ForPCIExpressinformation.

NOTE Registration may be required for access to standards.


Technical Support Contact Information

TechnicalassistancecontactdetailscanbefoundonthewebsiteSupportLocatorpage.TheappropriatelocationisheadedDSP,SBCs,MultiprocessorsandGraphics(formerlyRadstone).

LINK http://www.ge-ip.com/support/embeddedsupport/locator.

QuerieswillbeloggedontheTechnicalSupportdatabaseandallocatedauniqueServiceRequest(SR)numberforuseinfuturecorrespondence.

Alternatively,youmayalsocontactGEIntelligentPlatformsTechnicalSupportvia:

LINK [email protected]

TELEPHONE +44 (0) 1327 322760

Returns

Ifyouneedtoreturnaproduct,thereisaReturnMaterialsAuthorization(RMA)requestformthatcanbeprintedoutandfilledin,availableviathewebsiteRepairspage.

LINK http://www.ge-ip.com/support/embeddedsupport/rmalocator.

FollowtheDownloadRMA Request Form (Word Doc)hyperlinkunderDSP,SBCs,MultiprocessorsandGraphics(FormerlyRadstone).

Donotreturnproductswithoutfirstcontactingthefactory.

Publication No. SBC312-HRM/1 Contents 7

Contents

1 Introduction .............................................................................................................................................. 14 1.1 Safety Notices....................................................................................................................................................................................... 15

1.1.1 Flammability .....................................................................................................................................................................................................15 1.1.2 EMI/EMC Regulatory Compliance ...........................................................................................................................................................15 1.1.3 Cooling.................................................................................................................................................................................................................16 1.1.4 Handling..............................................................................................................................................................................................................16 1.1.5 Heatsink ..............................................................................................................................................................................................................16

2 Unpacking.................................................................................................................................................. 17 2.1 Box Contents Checklist .................................................................................................................................................................... 17 2.2 Identifying Your Board...................................................................................................................................................................... 18

3 Configuration ........................................................................................................................................... 19 3.1 Link Configuration .............................................................................................................................................................................. 19 3.2 Inspection............................................................................................................................................................................................... 20 3.3 Link Descriptions ................................................................................................................................................................................. 20

3.3.1 PMC 5V VIO Selection Link (P8) .................................................................................................................................................................20 3.3.2 Boot Area Selection (P9 Pins 1 to 4)........................................................................................................................................................20 3.3.3 MRAM Write Enable Link (P9 Pins 5 and 6) ..........................................................................................................................................21 3.3.4 Flash Protection Unlock Link (P9 Pins 7 and 8)..................................................................................................................................21 3.3.5 JTAG Scanbridge Output Enable Link (P9 Pins 9 and 10) .............................................................................................................21

3.4 Software Board Configuration ..................................................................................................................................................... 22 3.4.1 P4080 Cores 4 to 7 Disable ........................................................................................................................................................................22 3.4.2 P4080 UART Configuration.........................................................................................................................................................................22

3.5 Mezzanine Installation...................................................................................................................................................................... 23 3.5.1 PMC Installation...............................................................................................................................................................................................23 3.5.2 XMC Installation...............................................................................................................................................................................................24

4 Installation and Power Up/Reset .................................................................................................... 25 4.1 Power Supply Requirements ......................................................................................................................................................... 25 4.2 Board Keying......................................................................................................................................................................................... 25 4.3 Board Installation Notes.................................................................................................................................................................. 25 4.4 Connecting to SBC312 ..................................................................................................................................................................... 26 4.5 Reset & Power-up Sequence......................................................................................................................................................... 26

5 Functional Description......................................................................................................................... 27 5.1 Features .................................................................................................................................................................................................. 28 5.2 Integrated Host Processor ............................................................................................................................................................. 29

5.2.1 PowerPC Processing Cores ........................................................................................................................................................................29 5.2.2 Trust Architecture...........................................................................................................................................................................................30 5.2.3 Memory Map.....................................................................................................................................................................................................30 5.2.4 Reset Configuration Word ..........................................................................................................................................................................30 5.2.5 Local Bus.............................................................................................................................................................................................................31 5.2.6 Local Bus Memory Map ...............................................................................................................................................................................31 5.2.7 Processor Power Management................................................................................................................................................................31

5.3 RAM............................................................................................................................................................................................................ 32 5.4 NOR Flash ............................................................................................................................................................................................... 33

5.4.1 Boot Flash...........................................................................................................................................................................................................34 5.4.2 User Flash...........................................................................................................................................................................................................34 5.4.3 Paged Flash Mode..........................................................................................................................................................................................34 5.4.4 Flash Sector Protection................................................................................................................................................................................35


5 Functional Description (continued) 5.5 SPI Serial Flash ..................................................................................................................................................................................... 36 5.6 NAND Flash Solid State Drive........................................................................................................................................................ 36 5.7 MRAM........................................................................................................................................................................................................ 36 5.8 VPX Interface......................................................................................................................................................................................... 37

5.8.1 OpenVPX Compatibility ................................................................................................................................................................................37 5.8.2 PCI Express.........................................................................................................................................................................................................37 5.8.3 REF_CLK ..............................................................................................................................................................................................................38 5.8.4 AUX_CLK .............................................................................................................................................................................................................38 5.8.5 Module Maskable Reset...............................................................................................................................................................................38 5.8.6 Global Discrete.................................................................................................................................................................................................39

5.9 I/O............................................................................................................................................................................................................... 39 5.9.1 Serial Communication Ports......................................................................................................................................................................39

COM1 and COM2.......................................................................................................................................................................................................................... 39 COM3 and COM4.......................................................................................................................................................................................................................... 40 Host-to-BMM Serial Port........................................................................................................................................................................................................... 41

5.9.2 Ethernet...............................................................................................................................................................................................................41 5.9.3 USB ........................................................................................................................................................................................................................42 5.9.4 SATA ......................................................................................................................................................................................................................42 5.9.5 GPIO ......................................................................................................................................................................................................................42

5.10 Mezzanines.......................................................................................................................................................................................... 44 5.10.1 PMC/XMC Site.................................................................................................................................................................................................44 5.10.2 PCI Mezzanine Cards (PMCs) ...................................................................................................................................................................44 5.10.3 PCI Express Mezzanine Cards (XMCs)..................................................................................................................................................44 5.10.4 I/O Routing ......................................................................................................................................................................................................45

5.11 PCI Express Infrastructure ........................................................................................................................................................... 47 5.11.1 P4080.................................................................................................................................................................................................................47 5.11.2 PCI Express Switch.......................................................................................................................................................................................48

5.12 I2C Buses............................................................................................................................................................................................... 49 5.12.1 Addressing.......................................................................................................................................................................................................49 5.12.2 I2C Bus 1............................................................................................................................................................................................................50 5.12.3 I2C Bus 2............................................................................................................................................................................................................50 5.12.4 I2C Bus 3............................................................................................................................................................................................................50 5.12.5 I2C Bus 4............................................................................................................................................................................................................50 5.12.6 I2C Reset ...........................................................................................................................................................................................................50 5.12.7 P4080 Config EEPROM...............................................................................................................................................................................50 5.12.8 DIP Switch........................................................................................................................................................................................................51 5.12.9 Real Time Clock.............................................................................................................................................................................................51 5.12.10 Elapsed-Time Indicator...........................................................................................................................................................................51 5.12.11 Temperature Sensors ..............................................................................................................................................................................52 5.12.12 Power Manager..........................................................................................................................................................................................52 5.12.13 Board Management Microcontroller................................................................................................................................................53

5.13 Timers .................................................................................................................................................................................................... 54 5.13.1 Watchdog Timers.........................................................................................................................................................................................54

5.14 AXIS Support....................................................................................................................................................................................... 55 5.14.1 AXIS Timer........................................................................................................................................................................................................55 5.14.2 Mailboxes.........................................................................................................................................................................................................55 5.14.3 Semaphores ...................................................................................................................................................................................................55

5.15 Power Sequencing........................................................................................................................................................................... 56 5.15.1 On-board Sequencing................................................................................................................................................................................56 5.15.2 Inter-board Sequencing............................................................................................................................................................................56

5.16 Resets and Interrupts..................................................................................................................................................................... 57 5.16.1 Hard Reset.......................................................................................................................................................................................................57 5.16.2 External Interrupt .........................................................................................................................................................................................58

5.17 FPGA ....................................................................................................................................................................................................... 59

Publication No. SBC312-HRM/1 Contents 9

5 Functional Description (continued) 5.18 Control and Status Registers...................................................................................................................................................... 60

5.18.1 Board ID Register (Offset 0x0000) ........................................................................................................................................................61 5.18.2 Revision Register (Offset 0x0002) .........................................................................................................................................................61 5.18.3 Address Register (Offset 0x0006)..........................................................................................................................................................61 5.18.4 Power-On Configuration Register (Offset 0x0008) .......................................................................................................................61 5.18.5 Board Configuration Register 1 (Offset 0x000A)............................................................................................................................62 5.18.6 Board Configuration Register 2 (Offset 0x000C)............................................................................................................................62 5.18.7 RAM/Flash Configuration Register (Offset 0x000E) ......................................................................................................................63 5.18.8 Reset Cause Register (Offset 0x0010).................................................................................................................................................63 5.18.9 Link Status Register (Offset 0x0012)....................................................................................................................................................64 5.18.10 Control Register 1 (Offset 0x0014).....................................................................................................................................................64 5.18.11 Serial Control Register (Offset 0x0016)............................................................................................................................................65 5.18.12 Control Register 3 (Offset 0x001A).....................................................................................................................................................65 5.18.13 Test Pattern Registers 1 to 6 (Offsets 0x0020 to 0x002A) ......................................................................................................66 5.18.14 Scratchpad Registers (Offsets 0x0030 to 0x003E) .....................................................................................................................66 5.18.15 Board Semaphore Registers (Offsets 0x0040 to 0x007C) ......................................................................................................67 5.18.16 Watchdog 0 Control Register 1 (Offset 0x2000) and Watchdog 1 Control Register 1 (Offset 0x2010) .............67 5.18.17 Watchdog 0 Control Register 2 (Offset 0x2002) and Watchdog 1 Control Register 2 (Offset 0x2012) .............67 5.18.18 Watchdog 0 Interrupt Value Register 1 (Offset 0x2004) and Watchdog 1 Interrupt Value Register 1 (Offset 0x2014)........................................................................................................68 5.18.19 Watchdog 0 Interrupt Value Register 2 (Offset 0x2006) and Watchdog 1 Interrupt Value Register 2 (Offset 0x2016)........................................................................................................68 5.18.20 Board Interrupt Status Register (Offset 0x4002).........................................................................................................................68 5.18.21 P4080 Interrupt INT0 Mask Register (Offset 0x4012)................................................................................................................69 5.18.22 P4080 Interrupt INT4 Mask Register (Offset 0x4016)................................................................................................................69 5.18.23 P4080 Interrupt INT5 Mask Register (Offset 0x401A)................................................................................................................69 5.18.24 P4080 Interrupt INT6 Mask Register (Offset 0x401E)................................................................................................................69 5.18.25 P4080 Interrupt INT7 Mask Register (Offset 0x4022)................................................................................................................69 5.18.26 P4080 Interrupt INT8 Mask Register (Offset 0x4026)................................................................................................................70 5.18.27 REFCLK Counter High, Mid and Low Value Registers (Offsets 0x6000 to 0x6006)......................................................70 5.18.28 Counter Control Register (Offset 0x6008) ......................................................................................................................................70 5.18.29 REFCLK/AUXCLK Control Register (Offset 0x600A).....................................................................................................................70 5.18.30 AUXCLK Counter High and Low Value Registers (Offsets 0x600C & 0x600E)................................................................71 5.18.31 AXIS Semaphore Registers (Offsets 0x6020 to 0x603C)..........................................................................................................71 5.18.32 FIFO Data Registers (Offsets 0x6040 to 0x604C .........................................................................................................................71 5.18.33 FIFO Status Registers (Offsets 0x6050 to 0x605C).....................................................................................................................72 5.18.34 GPIO Registers ............................................................................................................................................................................................72

5.19 JTAG........................................................................................................................................................................................................ 73 5.19.1 Boundary Scan..............................................................................................................................................................................................73 5.19.2 Processor Debug Header .........................................................................................................................................................................74 5.19.3 FPGA Programming Header....................................................................................................................................................................74

5.20 LEDs ........................................................................................................................................................................................................ 75 5.20.1 Power Good LED (DS200)..........................................................................................................................................................................75 5.20.2 BIT LEDs (DS201 to DS204).......................................................................................................................................................................76 5.20.3 SATA Activity LEDs (DS205 and DS206)..............................................................................................................................................76 5.20.4 Reset Status LED (DS207) .........................................................................................................................................................................76 5.20.5 Ethernet PHY 1 Link Status LEDs (DS208 to DS211) .....................................................................................................................77 5.20.6 PCI Express Switch Link Status LEDs (DS212 to DS215) .............................................................................................................77

5.21 Front Panel .......................................................................................................................................................................................... 78 5.21.1 Air-cooled Versions (Build Levels 1 to 3) ............................................................................................................................................78 5.21.2 Conduction-cooled Versions (Build Levels 4 and 5) .....................................................................................................................78


6 Connectors ................................................................................................................................................ 79 6.1 Backplane Connectors ..................................................................................................................................................................... 81

6.1.1 P0 ..........................................................................................................................................................................................................................81 6.1.2 Backplane J0.....................................................................................................................................................................................................81 6.1.3 P1 ..........................................................................................................................................................................................................................82 6.1.4 Backplane J1.....................................................................................................................................................................................................82 6.1.5 P2 ..........................................................................................................................................................................................................................83 6.1.6 Backplane J2.....................................................................................................................................................................................................84 6.1.7 Signal Definitions ............................................................................................................................................................................................85

6.2 PMC Connectors.................................................................................................................................................................................. 87 6.2.1 J11 and J12 .......................................................................................................................................................................................................87 6.2.2 J13 and J14 .......................................................................................................................................................................................................88 6.2.3 Signal Descriptions.........................................................................................................................................................................................89

6.3 XMC Connectors.................................................................................................................................................................................. 90 6.3.1 J15 .........................................................................................................................................................................................................................90 6.3.2 J16 .........................................................................................................................................................................................................................91 6.3.3 Signal Descriptions.........................................................................................................................................................................................92

6.4 JTAG Pass Thru Header (P7)........................................................................................................................................................... 92 6.5 Aurora Debug Header (J3) .............................................................................................................................................................. 93 6.6 Test Access Card Connector (P4)................................................................................................................................................. 94

A Specifications........................................................................................................................................... 95 A.1 Mechanical Specification................................................................................................................................................................ 95 A.2 Technical Specification.................................................................................................................................................................... 95 A.3 Environmental Specifications ....................................................................................................................................................... 96 A.4 Electrical Specification..................................................................................................................................................................... 97 A.5 Reliability (MTBF).................................................................................................................................................................................. 98 A.6 Product Codes...................................................................................................................................................................................... 99 A.7 Software Support..............................................................................................................................................................................100

A.7.1 Boot Firmware .............................................................................................................................................................................................. 100 A.7.2 Built In Test ..................................................................................................................................................................................................... 100 A.7.3 Background Condition Screening........................................................................................................................................................ 101

A.8 I/O Modules .........................................................................................................................................................................................101 Glossary........................................................................................................................................................... 102 Index ................................................................................................................................................................. 103

Publication No. SBC312-HRM/1 List of Tables 11

List of Tables

Table 3-1 P8 Jumper Functions ................................................................................................................................................................ 20 Table 3-2 P9 Pins 1 to 4 Jumper Functions......................................................................................................................................... 20 Table 3-3 P9 Pins 5 and 6 Jumper Function ....................................................................................................................................... 21 Table 3-4 P9 Pins 7 and 8 Jumper Function ....................................................................................................................................... 21 Table 3-5 P9 Pins 9 and 10 Jumper Function..................................................................................................................................... 21 Table 5-1 Processor Specifications ......................................................................................................................................................... 29 Table 5-2 Local Bus Chip Select Targets............................................................................................................................................... 31 Table 5-3 SDRAM Configurations ............................................................................................................................................................. 32 Table 5-4 Flash Options ................................................................................................................................................................................ 33 Table 5-5 Boot Image Selection by Link................................................................................................................................................ 34 Table 5-6 Backplane PCI Express Port Configurations (Lanes 16 to 23)................................................................................ 37 Table 5-7 COM1/COM2 Signal Availability ........................................................................................................................................... 39 Table 5-8 SBC310-compatible COM2 Signal Availability .............................................................................................................. 40 Table 5-9 Baud Rates..................................................................................................................................................................................... 40 Table 5-10 COM3/COM4 Signal Availability......................................................................................................................................... 41 Table 5-11 P4080 Network Interface Mapping ................................................................................................................................. 41 Table 5-12 ETH0/ETH1 Pin Mapping....................................................................................................................................................... 41 Table 5-13 USB0/USB1 Signal Availability ........................................................................................................................................... 42 Table 5-14 SATA Signal Availability ......................................................................................................................................................... 42 Table 5-15 GPIO Line Routing .................................................................................................................................................................... 42 Table 5-16 PMC/XMC Site Signal Availability (X20d24s XMC I/O) .............................................................................................. 45 Table 5-17 PMC/XMC Site Signal Availability (Full PMC I/O) ......................................................................................................... 46 Table 5-18 PCI Bus........................................................................................................................................................................................... 47 Table 5-19 PCI Express Switch Connections....................................................................................................................................... 48 Table 5-20 I2C Bus Addresses .................................................................................................................................................................... 49 Table 5-21 PCA9560 Pin Allocation ......................................................................................................................................................... 51 Table 5-22 Power Manager Monitor Points......................................................................................................................................... 52 Table 5-23 BMM Address Allocation ....................................................................................................................................................... 53 Table 5-24 SMB Address Allocation ........................................................................................................................................................ 53 Table 5-25 External Interrupt Inputs to P4080 .................................................................................................................................. 57 Table 5-26 P4080 PCI INTx and External IRQ sharing .................................................................................................................... 58 Table 5-27 Control and Status Registers.............................................................................................................................................. 60 Table 5-28 Board ID Register ..................................................................................................................................................................... 61 Table 5-29 Revision Register ...................................................................................................................................................................... 61 Table 5-30 Address Register....................................................................................................................................................................... 61 Table 5-31 Power-On Configuration Register .................................................................................................................................... 61 Table 5-32 Board Configuration Register 1......................................................................................................................................... 62 Table 5-33 Board Configuration Register 2......................................................................................................................................... 62 Table 5-34 RAM/Flash Configuration Register................................................................................................................................... 63 Table 5-35 Reset Cause Register.............................................................................................................................................................. 63 Table 5-36 Link Status Register................................................................................................................................................................. 64 Table 5-37 Control Register 1 .................................................................................................................................................................... 64


Table 5-38 Serial Control Register ........................................................................................................................................................... 65 Table 5-39 Control Register 3 .................................................................................................................................................................... 65 Table 5-40 Test Pattern Registers............................................................................................................................................................ 66 Table 5-41 Board Semaphore Register Offsets................................................................................................................................. 67 Table 5-42 Watchdog Control Register 1............................................................................................................................................. 67 Table 5-43 Watchdog Interrupt Value Register 1 ............................................................................................................................ 68 Table 5-44 Watchdog Interrupt Value Register 2 ............................................................................................................................ 68 Table 5-45 Board Interrupt Status Register ........................................................................................................................................ 68 Table 5-46 P4080 Interrupt INT0 Mask Register ............................................................................................................................... 69 Table 5-47 Counter Control Register ...................................................................................................................................................... 70 Table 5-48 REFCLK Control Register ....................................................................................................................................................... 70 Table 5-49 AXIS Semaphore Register Offsets .................................................................................................................................... 71 Table 5-50 FIFO Data Register Offsets................................................................................................................................................... 71 Table 5-51 FIFO Status Register Offsets ............................................................................................................................................... 72 Table 5-52 FIFO Status Register................................................................................................................................................................ 72 Table 5-53 JTAG Chains ................................................................................................................................................................................ 74 Table 5-54 USR_STATUS_BYTE Register Format............................................................................................................................... 74 Table 5-55 BIT LEDs ........................................................................................................................................................................................ 76 Table 5-56 BIT Status LED Meanings...................................................................................................................................................... 76 Table 5-57 SATA Activity LEDs ................................................................................................................................................................... 76 Table 5-58 Ethernet Link Status LEDs .................................................................................................................................................... 77 Table 5-59 PCI Express Switch Link Status LEDs .............................................................................................................................. 77 Table 6-1 Connector Functions................................................................................................................................................................. 79 Table 6-2 P0 Pin Assignments.................................................................................................................................................................... 81 Table 6-3 J0 Pin Assignments .................................................................................................................................................................... 81 Table 6-4 P1 Pin Assignments.................................................................................................................................................................... 82 Table 6-5 J1 Pin Assignments .................................................................................................................................................................... 82 Table 6-6 P2 Pin Assignments.................................................................................................................................................................... 83 Table 6-7 J2 Pin Assignments .................................................................................................................................................................... 84 Table 6-8 Backplane Connector Signal Definitions ......................................................................................................................... 85 Table 6-9 J11 Pin Assignments ................................................................................................................................................................. 87 Table 6-10 J12 Pin Assignments............................................................................................................................................................... 87 Table 6-11 J13 Pin Assignments............................................................................................................................................................... 88 Table 6-12 J14 Pin Assignments............................................................................................................................................................... 88 Table 6-13 PMC Signal Descriptions ....................................................................................................................................................... 89 Table 6-14 J15 Pin Assignments............................................................................................................................................................... 90 Table 6-15 J16 Pin Assignments............................................................................................................................................................... 91 Table 6-16 XMC Signal Descriptions ....................................................................................................................................................... 92 Table 6-17 J3 Pin Assignments ................................................................................................................................................................. 93 Table 6-18 J3 Signal Descriptions............................................................................................................................................................ 93 Table 6-19 P4 Pin Assignments................................................................................................................................................................. 94 Table A-1 Mechanical Construction........................................................................................................................................................ 95 Table A-2 Technical Data ............................................................................................................................................................................. 95 Table A-3 Convection-cooled Environmental Specifications...................................................................................................... 96 Table A-4 Conduction-cooled Environmental Specifications ..................................................................................................... 96 Table A-5 Voltage Supply Requirements .............................................................................................................................................. 97 Table A-6 Current Consumption ............................................................................................................................................................... 97

Publication No. SBC312-HRM/1 List of Tables 13

Table A-7 Reliability (MTBF).......................................................................................................................................................................... 98 Table A-8 Product Options........................................................................................................................................................................... 99

List of Figures

Figure 1-1 SBC312 (Conduction-cooled) General View ................................................................................................................. 14 Figure 1-2 ESD Label (Present on Board Packaging) ...................................................................................................................... 16 Figure 2-1 Box Contents ............................................................................................................................................................................... 17 Figure 2-2 Product Label (Packaging) .................................................................................................................................................... 18 Figure 2-3 Product Label (Product).......................................................................................................................................................... 18 Figure 2-4 Product Label (Conduction-cooled Product)................................................................................................................ 18 Figure 3-1 Link Positions............................................................................................................................................................................... 19 Figure 3-2 PMC/XMC Site Location.......................................................................................................................................................... 23 Figure 5-1 Block Diagram ............................................................................................................................................................................ 27 Figure 5-2 Flash Memory Structure ........................................................................................................................................................ 33 Figure 5-3 User Flash Page Numbering................................................................................................................................................ 34 Figure 5-4 I2C Bus Structure ....................................................................................................................................................................... 49 Figure 5-5 JTAG Chains................................................................................................................................................................................. 73 Figure 5-6 LED Positions............................................................................................................................................................................... 75 Figure 5-7 Air-cooled Front Panel ............................................................................................................................................................ 78 Figure 5-8 Conduction-cooled Front Panel ......................................................................................................................................... 78 Figure 6-1 Connector Positions (Top)...................................................................................................................................................... 79 Figure 6-2 Connector Positions (Back) ................................................................................................................................................... 80


1 Introduction TheGEIntelligentPlatformsSBC312isamemberoftheVPXtreme3familyof3UVPXSingleBoardComputers.ItusestheFreescaleP4080QorIQprocessor,whichcontainseighte500mcPowerPCprocessingcoresrunningatupto1.5GHz,withdualmemorycontrollersandI/Ointerfaces.TheSBC312offersupto8GBytesofDDR3SDRAMwithECCandupto512MBytesofNORFlashmemory,alongwithtwoGigabitEthernetchannels,serial,USB2.0andSerialATAinterfaces.Flexibleconfigurationofserialfabricsisprovidedtosuitavarietyofsysteminterconnectrequirements,withuptoeightlanesofPCIExpressavailableonthebackplane.

TheP4080processorisconnectedtoallonboardPCIdevicesandthemezzaninesiteusingPCIExpressthroughanonblockingswitcharchitecture.One64bitPMCsiteisprovided,supportingPCIXoperationatupto133MHz,allowingforofftheshelforcustommezzaninestobefittedtoaddfurtherfunctionalitytotheboard.ThesitealsosupportsXMCmezzaninecards,supportingax8PCIExpresslinktothesite,forhigherbandwidthconnectivitytothehostandhighspeedrearI/O.

TheSBC312couplesfamiliarsoftwareinterfacesandreliabilitywithhighspeedfabricinterfaces,offeringsignificantincreasesininterboardbandwidth.

Figure 1-1 SBC312 (Conduction-cooled) General View

Publication No. SBC312-HRM/1 Introduction 15

1.1 Safety Notices

ThefollowinggeneralsafetyprecautionsrepresentwarningsofcertaindangersofwhichGEIntelligentPlatforms(GEIP)isaware.FailuretocomplywiththeseorwithspecificWarningsand/orCautionselsewhereinthismanualviolatessafetystandardsofdesign,manufactureandintendeduseoftheequipment.GEIPassumesnoliabilityfortheusersfailuretocomplywiththeserequirements.

Alsofollowallwarninginstructionscontainedinassociatedsystemequipmentmanuals.

WARNINGS Use extreme caution when handling, testing and adjusting this equipment. This device may operate in an environment containing potentially dangerous voltages.

Ensure that all power to the system is removed before installing any device.

To minimize shock hazard, connect the equipment chassis and rack/enclosure to an electrical ground. If AC power is supplied to the rack/enclosure, the power jack and mating plug of the power cable must meet IEC safety standards.

1.1.1 Flammability TheSBC312circuitboardismadebyaULrecognizedmanufacturerandhasaflammabilityratingofUL94V1.

1.1.2 EMI/EMC Regulatory Compliance

CAUTION This equipment generates, uses and can radiate electromagnetic energy. It may cause or be susceptible to EMI if not installed and used in a cabinet with adequate EMI protection

TheSBC312isdesignedusinggoodEMCpracticesand,whenusedinasuitablyEMCcompliantchassis,shouldmaintainthecomplianceofthetotalsystem.TheSBC312alsocomplieswithEN60950(productsafety),whichisessentiallytherequirementfortheLowVoltageDirective(73/23/EEC).

AircooledbuildlevelsoftheSBC312aredesignedforuseinsystemsmeetingVDEclassB,ENandFCCregulationsforEMCemissionsandsusceptibility.

ConductioncooledbuildlevelsoftheSBC312aredesignedforintegrationintoEMChardenedcabinets/boxes.


1.1.3 Cooling

CAUTION The SBC312 requires air-flow of at least 300 feet/minute for build levels 1 and 2, and at least 600 feet/minute for build level 3. If a conduction-cooled (level 4 or 5) SBC312 is operating on an extender card, it requires air-flow of at least 300 feet/minute across it.

1.1.4 Handling

CAUTION Only handle the SBC312 by the edges or front panel.

Figure 1-2 ESD Label (Present on Board Packaging)

1.1.5 Heatsink

CAUTIONS Do not remove the heatsink. There are no user-alterable components underneath the heatsink, so users should have no reason to remove it.

Users should not attempt reattachment of the heatsink, as this requires precise torque on the screws attaching the heatsink to the PCB. Over-tightening the screws may cause the heatsink to damage components beneath it. Removal and re-attachment of the heatsink should only be carried out by the factory.

Publication No. SBC312-HRM/1 Unpacking 17

2 Unpacking Onreceiptoftheshippingcontainer,ifthereisanyevidenceofphysicaldamage,theTermsandConditionsofSale(suppliedwithyourdelivery)provideinformationonwhattodo.Ifyouneedtoreturntheproduct,pleasecontactyourlocalGEIPsalesofficeoragent.

TheSBC312issealedintoanantistaticbagandhousedinapaddedcardboardbox.Failuretousethecorrectpackagingwhenstoringorshippingtheboardmayinvalidatethewarranty.

2.1 Box Contents Checklist

1. SBC312inantistaticpackaging.

2. ManualCDROM(designmayvary).

3. EmbeddedSoftwareLicenseAgreement(GFJ353).

Figure 2-1 Box Contents


2.2 Identifying Your Board

TheSBC312isidentifiedbylabelsatstrategicpositions.ThesecanbecrosscheckedagainsttheAdviceNoteprovidedwithyourdelivery.

Identificationlabels,similartotheexampleshowninFigure22,attachedtotheshippingboxandtheantistaticbaggiveidenticalinformation:productcode,productdescription,equipmentnumberandboardrevision.

Figure 2-2 Product Label (Packaging)

Ontheboardwithintheantistaticbag,thereisanidentifyinglabelsimilartotheexampleshowninFigure23,attachedtothePCB.

Figure 2-3 Product Label (Product)

Onconductioncooledversionsoftheboard(buildlevels4and5),thereisalsoalabelsimilartotheexampleshowninFigure24,attachedtothefrontpanel.

Figure 2-4 Product Label (Conduction-cooled Product)

SeetheProductCodeInformationsectioninAppendixAformoredetailsontheproductcode(SBC312xxxxxxxx).

Publication No. SBC312-HRM/1 Configuration 19

3 Configuration

3.1 Link Configuration

TheSBC312haspushonjumpersincludedinthestandardkitofparts;additionaljumpersmaybeobtainedonrequest.Thesearesuitableforlevel1to3lowvibrationapplications.

TIP For Level 4 and 5 products, make links by wire-wrapping between the pin posts and then cover these wire wrapped links with the same conformal coating as that used on the board. This will provide a reliable connection under heavy shock and vibration conditions and further prevent oxidation of the connection due to moisture ingress.

Figure 3-1 Link Positions

Figure31showsstandard2.54mmpitchheadersforgeneraluse.

ThismanualreferstojumpersettingsasInorOut.Meaningsareasfollows:In=jumperfitted Out=jumpernotfitted


3.2 Inspection

TheSBC312isshippedfromthefactorywithnojumpersfitted.

3.3 Link Descriptions

NOTES 1. Ordinary operation requires no jumpers to be fitted.

2. The states of most of the links can be read from the Link Status Register (register offset 0x0012).

TIP If you are about to install your board and power-up for the first time, leaving your board in the default configuration will enable board operation to be proven before tackling any further configuration issues.

3.3.1 PMC 5V VIO Selection Link (P8) PMCsmayuse+5Vor+3.3VfortheVIOsignalingvoltage.ThislinkcontrolstheVIOsignalingvoltageprovidedbytheSBC312atthePMCsite.ThislinkshouldonlybefittedwhenaPMCthatuses5Vsignalingisinstalled,andshouldbeleftnotfittedotherwise.

ThestateofthislinkisreflectedintheBoardConfigurationRegister1(registeroffset0x000A).

Table 3-1 P8 Jumper Functions Setting Meaning

Pin 4 to pin 3 VIO signaling voltage is 3.3 V

Pin 2 to pin 4 VIO signaling voltage is 5V

CAUTION Selection of the wrong VIO signaling voltage may cause damage to the PMC.

3.3.2 Boot Area Selection (P9 Pins 1 to 4) TheBootFlash(forallprocessingcores)isdividedintofoursections,allowingforthreedifferentbootimagestobeloadedintotheFlash.ThereisalsoafactoryprogrammedRecoverybootimage.Theselinksareusedtoselectwhichimageisusedatboottime.ThestateoftheselinksisreflectedintheLinkStatusRegister(registeroffset0x0012).

Table 3-2 P9 Pins 1 to 4 Jumper Functions Pins 1 & 2 Pins 3 & 4 Active Boot Image

Out Out Main boot image

In Out Alternate boot image

Out In Recovery boot image

In In Second Alternate boot image

Innormaloperation,theselinksarenotfittedandtheSBC312bootsfromtheMainbootimage.


3.3.3 MRAM Write Enable Link (P9 Pins 5 and 6) ThislinkcontrolsthewriteprotectionforthenonvolatileMRAMdeviceontheSBC312.Thisdeviceholdsfirmwarebootparametersaswellasuserdata.

ThestateofthislinkisreflectedintheLinkStatusRegister(registeroffset0x0012).

Table 3-3 P9 Pins 5 and 6 Jumper Function Setting Meaning

Out The MRAM is write protected

In The MRAM is write enabled

NOTE The VPX backplane Non-Volatile Memory Read Only (NVMRO) signal (on connector P0 pin A4) must also be set inactive low before the MRAM can be written.

3.3.4 Flash Protection Unlock Link (P9 Pins 7 and 8) ThislinkmustbefittedtoallowsoftwaretoaltertheFlashpersistentsectorprotection,whichremainsunchangedfollowingaresetorapowercycle.SeetheFlashSectorProtectionsectionforfurtherdetails.

Ifthelinkisnotfitted,thesoftwareispreventedfromalteringanypreviouslyconfiguredsectorprotection.ThestateofthislinkisreflectedintheLinkStatusRegister(registeroffset0x0012).


Out Persistent sector protection cannot be altered

In Persistent sector protection can be altered

NOTE The VPX backplane Non-Volatile Memory Read Only (NVMRO) signal (on connector P0 pin A4) must also be set inactive low before the persistent sector protection can be altered.

3.3.5 JTAG Scanbridge Output Enable Link (P9 Pins 9 and 10) TheSBC312usesaJTAGScanbridgedevicetoconnectalloftheJTAGcompliantdevicesontheboard.ThislinkisprovidedtoenabletheScanbridgeduringboundaryscan.ItshouldnotnormallybefittedindeployedsystemsandmustnotbefittedwhentheProcessorDebugHeader(J3)isinuse.


Out Scanbridge disabled

In Scanbridge enabled


3.4 Software Board Configuration

TheSBC312containsanI2CEEPROMDIPSwitchdevice(seetheI2CBusessection),whichmaybeusedtoconfigureadditionalboardoptionsundersoftwarecontrol.

TheVPXbackplaneNonVolatileMemoryReadOnly(NVMRO)signal(onconnectorP0pinA4)pulledlowbeforethesesettingscanbemodified.Fordetailsonhowtomonitororchangethesesettings,refertotheappropriateSoftwareReferenceManual.

3.4.1 P4080 Cores 4 to 7 Disable ThisconfigurationoptiondisablesfourcoresoftheP4080processorandtheirassociatedpowersupply,causingtheprocessortoappeartosoftwareasaP4040quadcoredevice.Thismaybeusedtoachievelowerpoweroperationwhentheapplicationdoesnotrequiremorethanfourprocessingcores.

ThissettingonlytakeseffectfollowingapowercycleoftheSBC612.TheactivestateofthissettingisreflectedinBoardConfigurationRegister1(registeroffset0x000A).

Thedefaultsettingofthisoptionisinactive,suchthatalleightprocessingcoresareenabled.

3.4.2 P4080 UART Configuration TheSBC312supportsoperatingtheUARTswithintheP4080inthefollowingmodes,whichmaybeselectedusingthisconfigurationoption:

COM1andCOM2withflowcontrol COM1,COM2,COM3andCOM4withoutflowcontrolSeetheSerialCommunicationPortssectionforcorrespondingpinoutchanges.

ThissettingonlytakeseffectfollowingaresetoftheSBC312.

ThedefaultsettingofthisoptionistousetwoUARTs(COM1andCOM2)withflowcontrol.


3.5 Mezzanine Installation

Asshowninthediagrambelow,theSBC312hasonemezzaninesitethatsupportsbothIEEEP1386.1compliantPMCsandANSI/VITA42.3compliantXMCs(includingsupportforfrontpanelI/O).ThesiteallowsforthefittingofonesinglewidthPMC/XMC.

3.5.1 PMC Installation

CAUTION Ensure that the PMC 5V VIO Selection Links (P8) is set according to the requirements of the corresponding PMC. Damage to the PMC may otherwise result.

PMCssuppliedbyGEIParedeliveredwithafullkitofpartsformountingthem,fittinginstructionsandamanual(onCDROM).APMCorderedwithanSBC312canbesuppliedfactoryfitted,ifrequired.

LINK PMC Installation Note, publication number HN4/3-99.

CAUTION Observe handling and anti-static precautions when fitting the PMC.

ItwillusuallybenecessarytoinstalldriversoftwareorimplementotherfirmwareconfigurationtoachievefullfunctionalityofaPMC(seethespecificPMCmanualfortheexactprocedure).

TIP Where a PMC is not pre-installed, prove operation of the SBC312 before installing the PMC.

Figure 3-2 PMC/XMC Site Location


3.5.2 XMC Installation XMCssuppliedbyGEIParedeliveredwithafullkitofpartsformountingthemandamanual(onCDROM).FittingissimilartoaPMC.AnXMCorderedwithanSBC312canbesuppliedfactoryfitted,ifrequired.

CAUTION Observe handling and anti-static precautions when fitting the XMC.

ItwillusuallybenecessarytoinstalldriversoftwareorimplementotherfirmwareconfigurationtoachievefullfunctionalityofaXMC(seethespecificXMCmanualfortheexactprocedure).

TIP Where an XMC is not pre-installed, prove operation of the SBC312 before installing the XMC.

Publication No. SBC312-HRM/1 Installation and Power Up/Reset 25

4 Installation and Power Up/Reset ReviewtheSafetyNoticessectionbeforeinstallingtheSBC312.Thefollowingnoticesalsoapply:

CAUTION Consult the enclosure documentation to ensure that the SBC312s power requirements are compatible with those supplied by the backplane.

4.1 Power Supply Requirements

TheSBC312sestimatedpowerrequirementis30Wmaximumwhenoperatingwitheightprocessingcoresat1.5GHz.NovoltageisrequiredtobesuppliedontheVs1supplyastheSBC312doesnotconnecttothesepins.

4.2 Board Keying

TheVPXSpecificationrequiresallbackplaneslotstohavetwoguidepins:oneabovetheJ0connectorandonebelowtheJ2connector.Aswellasprovidingcorrectalignment,thesepinsarekeyedtopreventcardsbeinginsertedintoincorrectbackplaneslot(s)toavoidelectricalincompatibility.

TheSBC320hasreceptaclesfortheseguidepins.Bydefault,thesearenotkeyed.Contactthefactorytodiscussanykeyingrequirements.

4.3 Board Installation Notes

1. Keyingmaydictatethebackplaneslot(s)intowhichtheSBC312canbeinserted.

2. AircooledversionsoftheSBC312haveinjector/ejectorhandlestoensurethatthebackplaneconnectorsmateproperlywiththebackplane.Thecaptivescrewsatthetopandbottomofthefrontpanelallowtheboardtobetightlysecuredinposition,whichprovidescontinuitywiththechassisgroundofthesystem.

3. ConductioncooledversionsoftheSBC312havescrewdrivenwedgelocksatthetopandbottomoftheboardtoprovidethenecessarymechanical/thermalinterface.Correctadjustmentrequiresacalibratedtorquewrenchwithahexagonalheadofsize3/32(2.38mm),settobetween0.6and0.8Nm.

4. Inanaircooleddevelopmentenclosure,whentakingI/Oconnectionsfromthebackplaneconnectors,useofGEIPI/Omodules(orsomeequivalentsystem)ensuresoptimumoperationoftheSBC312withregardtoEMI.SeetheVPXI/OModulesmanualformoredetails.

LINK VPX I/O Modules Hardware Reference Manual, publication number VPXIOM-0HH.


4.4 Connecting to SBC312

TointeractwithonboardfirmwarerequirestheSBC312tohave,asaminimum,aterminalconnectionpresentontheserialCOM1port.AnEthernetconnectionmayalsoberequiredforHost/Targetinteraction.Theseportsmaybeaccessedthroughthebackplanepins,usingareartransitionmodule.

COM1isconfiguredbydefaultasDTEwithsettingsof115200baud,8bits/character,1stopbit,paritydisabledandnoflowcontrol.

4.4.1 Rear Transition Module Fordevelopmentsystems,connectiontotheSerialandEthernetI/OcanbeachievedusingaRearTransitionModule(RTM).Thisconvertsthecondensedpinoutofthebackplaneconnectorstopinoutssuitableforusebyindustrystandardconnectors.

Thefollowingitemsarerequired:

TheSBC312 TheappropriateRTM(VPX3UX600rev3orlater) Anullmodem9wayDtypecableforconnectingCOM1toacontrolterminalor

PCrunningterminalemulationsoftware

FortheEthernetports,aCAT5(orbetter)straightthroughpatchcablefor10/100/1000BaseTX

TheVPXI/OModulesmanualcontainsmoredetailsonfittingRTMs.Similarantistaticandsafetyprecautionsapplywhenhandlingand/orinstallingRTMsasfortheSBC312.

LINK VPX I/O Modules Hardware Reference Manual, publication number VPXIOM-0HH.

4.5 Reset & Power-up Sequence

ApowersequencermonitorsthebackplanesupplyvoltagesandwillholdtheSBC312inresetorshutdowntheonboardpowersuppliesifthebackplanesuppliesarenotwithinspecifiedlimits.

ThegreenPowerGoodLEDislitwhenthebackplaneandallonboardsuppliesarewithinspecification.

The+5Vsupplytothemezzaninecardsisswitched,underthecontrolofthepowermanagerdevice,sothatthe5Vand3.3Vsuppliesareappliedtothemezzaninesatapproximatelythesametime.

Publication No. SBC312-HRM/1 Functional Description 27

5 Functional Description Figure 5-1 Block Diagram

NOTES Due to the increasingly short lifetimes of system components, the I/O devices used on the SBC312 are not guaranteed to remain fixed in the future.

Hardware should be accessed only through mechanisms provided by the Operating Systems Board Support Package, and not directly by application software.

If a standard operating system is not being used, then it is recommended that applications are written in such a way as to minimize direct access to hardware resources, bearing in mind that changes may be necessary to support future iterations of the hardware.

GEIP-supported Operating Systems guarantee compatibility at the application level through hardware independent mechanisms.


5.1 Features

FreescaleP4080QorIQIntegratedHostProcessorwitheighte500mcprocessingcoresatupto1.5GHz

Upto4GBytesdualchannelDDR3SDRAMwithECC(2GBytespercontroller) Upto256MBytesofNORFlashmemorywithenhancedwriteprotection

features

512KBytesNonVolatileRAM OnemezzaninesitesupportingPMCorXMCmodules.ThePMCinterfacehasa

64bitPCI/PCIXinterfaceandcanoperateatupto133MHz.TheXMCinterfacehasax8PCIExpresslink

PCIExpressboardinterconnectwithnonblockingswitcharchitecture Upto8lanesofPCIExpresstothebackplane,operatingat2.5or5GHz Two10/100/1000BaseTEthernetports UptofourserialCOMports TwoUSB2.0ports UptotwoSATAports Upto8bitsofGeneralPurposeI/Owithinterruptcapability Realtimeclock Elapsedtimeindicator Watchdogtimers Ambienttemperaturesensors CompatiblewithrequirementsofVITA65OpenVPXspecification

Capableofbeingusedasapayloadboardwithinsystemsdesignedaroundit

I/OConfigurationsthatarepincompatiblewiththeSBC310 Fiveenvironmentalbuildlevels


5.2 Integrated Host Processor

TheSBC312isbasedaroundtheFreescaleQorIQP4080Eoctalcoreintegratedhostprocessor.Thisprovides:

Eighte500mcPowerPCprocessingcoreswithprivateL1andL2caches Shared2MByteL3PlatformCache CoreNetfabricbasedinterconnectatupto800MHz DualDDR3SDRAMcontrollers 16bitlocalbusinterface TwoGigabitEthernetMACs PCIExpressinterfaces DMAcontrollers SecurityandPatternMatchingEngines Interruptcontroller SerialI/Ointerfaces I2Ccontrollers TimersTheSBC312alsosupportstheP4040quadcoreversionoftheprocessororcanruntheP4080processorasaP4040,tominimizepowerconsumption,byremovingpowertotheupperfourcores.TheBoardConfigurationRegister1(registeroffset0x000A)showsthephysicalCPUtypefitted.

5.2.1 PowerPC Processing Cores TheP4080containseighte500mchighperformance,32bit,superscalardualissueBookEcompliantPowerPCprocessingcores,clockedatupto1.5GHz.Eachcoreincludes:

32KByteLevel1instructionanddatacaches 128KByteLevel2backsidecachewithECC 36bitphysicaladdressing DoublePrecisionFloatingPointUnit MMUwithembeddedHypervisorprivilegelevelTable 5-1 Processor Specifications

Processor Type Core Frequency (MHz) Platform Frequency (MHz) Memory Bus Frequency (MHz)

P4080E 1500 800 650

P4080E 1200 600 600

Dependingontheapplication,itispossibleforsoftwaretodynamicallyconfigureprocessorstorunatlowerclockfrequenciestominimizepower.


5.2.2 Trust Architecture TheP4080containsasetofhardwarefeaturesthatsupportatrustedbootenvironmentwhereonlytrustedcodemaybeexecutedandhardwarefeaturesthatcouldbeusedtocompromisesecurityaredisabled.TheimplementationofthisarchitectureisfullydescribedintheFreescalewhitepaperAnIntroductiontotheQorIQPlatformsTrustArchitecture.

TheSBC312providestheabilitytoprogramfuseswithintheP4080toconfiguresecuritykeys,accesstowhichiscontrolledbythesecuritystateoftheprocessor.

Ifyouwishtousethisfeatureoftheplatform,contactyourlocalGEIPsalesofficeoragentformoreinformation.

5.2.3 Memory Map TheP4080supportsafullyprogrammablememorymap,sharedbetweeneachoftheprocessingcores.Memorywindowsaresoftwareconfiguredandthehardwaredoesnotcarryoutanyconfigurationofthememorymap.Forthisreason,nomemorymapsareprovidedinthismanual.

Whereaddressesareprovidedinthismanual,theyarestatedasafixedoffsetfromasoftwareprogrammablebaseaddress.

Refertoapplicablesoftwaremanualsformoreinformation.

5.2.4 Reset Configuration Word TheP4080processorisconfigured,duringreset,byloadingadatastructurecalledtheResetConfigurationWord(RCW)fromnonvolatilememory.Thisspecifiestheoperatingfrequencyandnumerousconfigurationoptionsoftheprocessor.

NormallytheRCWisloadedfromfactoryconfiguredsettingswithintheFPGAandnouserinteractionisrequired.Ifmoresophisticatedconfigurationisrequired,itispossibletoloadthedatastructurefromanI2CEEPROMinstead,bysettingtherelevantsoftwareconfigurationoptionintheI2CEEPROMDIPSwitch.

CAUTION Do not change the source of the RCW unless advised to do so by the factory. Incorrect or invalid settings may damage the processor or prevent the SBC612 from booting

WhenbootingfromtheRecoverybootarea,thefactoryconfiguredRCWsettingsarealwaysused.ThisallowstheboardtoberecoveredifthedataintheI2CEEPROMisinvalidorbecomescorrupted.


5.2.5 Local Bus TheP4080localbusisa16bitmultiplexedaddress/databus,whichisusedtoaccessthefollowingdevicesontheSBC312:

FPGA Flash MRAMToreducetheloadingonthelocalbus,theFlashandMRAMdevicesareconnectedtoseparatedataandaddressbusescreatedbytheFPGA.

5.2.6 Local Bus Memory Map Alleightdevicechipselectsforthelocalbusaremadeavailable,sharedbetweenthedevicesasdefinedinthetablebelow.Theminimumpossiblewindowsizeis32KBytes.

Table 5-2 Local Bus Chip Select Targets Chip Select Target Device Width Required Window Size

CS0 Boot Flash 16-bit 8 MBytes

CS1 User Flash 16-bit 128 MBytes in Paged mode up to 1 GByte otherwise

CS2 Unused

CS3 MRAM 8-bit 512 KBytes

CS4

Control/Status Registers, Interrupt Controller Watchdogs AXIS registers

32-bit 32 KBytes

CS5 Unused

CS6 FPGA - UARTs - External SRAM

8-bit 4 MBytes

CS7

FPGA - DMA engines - Internal dual-port SRAM - GPIO controller

16-bit 4 MBytes

5.2.7 Processor Power Management TheP4080deviceimplementsthefollowingpowermanagementfeatures:

IndependentcontrolofDoze/Napmodesforeachprocessingcore Devicesleepstate


5.3 RAM

TheP4080containsdual64bitDDR3memorycontrollersandhastheabilitytointerleaveaccessesbetweenthetwocontrollerstofurtherincreasetheavailableRAMbandwidth.ThecontrollershavefullECCerrorcorrectionsupport,withtheabilitytodetectmultibiterrorsandcorrectsinglebiterrorswithinanibble.

TheSBC312providesuptoatotalof4GBytesofSDRAMintwobanks,eachconnectedtoaseparatememorycontroller.TheRAMconfigurationsaredefinedbelow.Table 5-3 SDRAM Configurations

Total RAM (GBytes)

Number of Devices

Device Type Die Density

Number of Banks/ Controllers

2 10 1 Gbit monolithic 1 Gbit 1


8 10 4 Gbit die stack 2 Gbit 2


TheRAM/FlashConfigurationRegister(registeroffset0x000E)showstheconfigurationofRAMfittedtotheboard.

TheP4080processorcontrolsthefrequencyoftheRAMinterface.Table51showsthepossibleconfigurations.


5.4 NOR Fla