SC312 Computer Organization: Introduction and OverviewCourse ContentLectures M/W 4-6 PM, CAS 211Three Exams (no final exam) worth 35%Five Labs (VLSI Lab) worth 25%Final Project worth 25%Four or Five Homework Problems worth 15%Several unannounced quizes given in class worth 1 extra point eachLabs and Final Project Digital design problems leading towards Final Project design of a 16 bit processorUse of Cadence Verilog/XL Schematic capture (design of the digital circuit)Write the behavioral model (logically express what each circuit block does)Logic simulation in Verilog (given a set of input waveforms, what are the output waveforms)Labs to be demod to GTF and/or UTF before 5 PM on due dateFinal project to be demod to GTF/UTF/Prof during Finals Week (in lieu of final exam)ExamsProblems similar (but not identical) to those in textbook and those given as homeworkEach exam covers material from preceding book chapters and lecture notesClosed book/closed notesR. W. Knepper, SC312page O/V-1

Introduction and Overview (continued):HomeworkTaken from text problems or other sourcesDue at beginning of class on Due DateSolutions will be discussed in class after gradingGTF will discuss homework problems at weekly Discussion HoursGTF/UTF will grade homeworkObjective of course:To understand the basic organization and design of a digital processor (such as a PC)To understand the design of digital systems (CPLD, FPGA, FSM) other than a processorTo understand memory hierarchy and memory system designTo understand and contrast RISC versus CISC instruction set architecturesTo learn to use CAD tools (such as Cadence Verilog XL) to perform digital sys designProfRonald W. Knepper, Professor ECE, PHO 439, 3-0023GTFShameek Gupta, PHO 313, 3-0036UTF ? A word about course evaluations (at end of semester)R. W. Knepper, SC312page O/V-2

Some Base Logic DefinitionsCombinational LogicLogic circuit path which operates independent of any clockData flows through from input(s) to output(s) Depends on circuit delaysExample:NAND, AND, NOR, OR, Inverter, ripple bit adderAny combination of above logicSequential LogicLogic circuits which operate with a clock Utilize latches and/or registers (also called flip-flops)Data is valid only a certain phases of the clockTypically edge-triggered to pass data alongNegative-going edgePositive-going edgeExamples:RS Flip-Flop, JK Flip-Flop, D Flip-Flop, T Flip-FlopFinite State Machine (FSM)Pipelined Microprocessor CPUCombinational logic blocks interspersed between clocked registersR. W. Knepper, SC312page O/V-3

Some Basic Memory DefinitionsRAM = Random Access MemorySRAM (Static Random Access Memory)Dc powered maintains data as long as power is ONVolatileHigh performanceExpenseUsed for cache (L1 and L2) designDRAM (Dynamic Random Access Memory)Must be regenerated periodically (e.g. every 128 ms) or loses dataVolatileMedium performanceCheapUsed for main memory designMagnetic Storage (also called Virtual Memory)Partially serial accessNon-volatile maintains data when power is OFFLow performanceVery cheapUsed for disk drive and mass store devicesR. W. Knepper, SC312page O/V-4

Digital versus Analog Circuits: Which are they?Noise MarginThe NM for a 1 is the signal range between the worst case low UP level of a circuit output and the minimum allowable voltage for a 1 at a subsequent input stage.The larger the noise margin, the better the circuit is for combinatorial logicCMOS has very good noise marginsThe NM for a 0 is the signal range between the worst case high DOWN level of a circuit output and the maximum allowable voltage for a 0 at a subsequent input stage.John Wakerly, Digital Design: Principles & Practices, Chaps 1,2,3R. W. Knepper, SC312page O/V-5All digital circuits are really analog circuits designed to have outputs within the proper windows for definition of a logic 1 or a logic 0 (see below)Inputs must also be within the prescribed range(s) for a logic 1 or logic 0For example, if the circuit is an inverter and the input is within logic 1 range below, the output will be within the logic 0 shown.

CMOS Inverter Input/Output Transfer CharacteristicCMOS inverter circuit operation:Q1 is an N-channel FETON when Vin is high (Vgs > Vtn)The source is at GND; drain is at VoutQ2 is a P-channel FETON when Vin is low (|Vgs| > |Vtp|)The source is at Vdd; drain is at VoutCMOS inverter acts like a simple switchWhen Vin is near GND, Q1 is OFF and Q2 is ON pulling Vout to VddWhen Vin is near Vdd, Q1 is ON and Q2 is OFF pulling Vout to GNDDC Transfer Characteristic:If Vin is slowly varied from GND to Vdd, Vout switches from Vdd to GNDBut, Vout stays in the 1 state (near Vdd) until Vin gets close to Vdd, and then switches quickly to the 0 state (near GND) for Vin greater than VddR. W. Knepper, SC312page O/V-6

CMOS Inverter Modeled as a Simple SwitchA very simple model for the CMOS inverter would treat the NFET and PFET transistors as simple SPST switches.When Vin = low, NFET switch is open and PFET switch is closedImplies that Vout = VddWhen Vin = high, NFET switch is closed and PFET switch is openImplies that Vout = GNDR. W. Knepper, SC312page O/V-7

2-input NAND Modeled as a Simple Set of SwitchesWe can apply the simple SPST switch idea to build a logic model for a 2-NANDQ1 and Q3 are two NFET transistors in series which are ON when A and/or B are high A high Q1 closedB high Q3 closedQ2 and Q4 are two PFET transistors in parallel which are ON when A and/or B are lowA low Q2 is closedB low Q4 is closedLogically, Z is low only if A and B are both high; if either A or B is low, Z is pulled high to Vdd by either Q2 or Q4, respectively.R. W. Knepper, SC312page O/V-8

2-Input CMOS NOR Circuit2-input CMOS NOR circuit operation:Q1 and Q3 are NFET transistors with sources at GND and drains at ZIf either A or B is high, Q1 or Q3 are ON and pull Z to GNDQ2 and Q4 are PFET transistors with sources at Vdd (Q2) and Q2/Q4 internal node (Q4)If both A and B are low, Q2 and Q4 are both ON and pull Z high to VddA simple SPST switch analogy can be used for the 2-input NOR, also.R. W. Knepper, SC312page O/V-9

The CMOS Transmission GateA CMOS transmission gate is a very popular circuit used in MUX design and in pass-gate logicCircuit Description:The gate is comprised of an NFET transistor in parallel with a PFET transistorThe NFET transistor gate is connected to some control voltage (Vg) while the PFET gate is connected to the complement of VgCircuit Operation:When Vg is high (and Vg is low), both the NFET and the PFET are ONOne is on harder than the other depending on whether Vin or Vout is at the higher potentialWhen Vg is low (and Vg is high), both the NFET and PFET are OFF since each transistor has its gate-to-source voltage Vgs less than its threshold magnitude |Vt|R. W. Knepper, SC312page O/V-10X-gateSymbol

The SRAM Memory CellCircuit Schematic:4 NFETs and 2 PFETs: T1 & T2 called active devices; T3 & T4 called the I/O devices; T5 & T6 sometimes called loads.The cell is comprised of two cross-coupled inverters (positive feedback).2 vertical lines (bit lines B0 & B1) are used for sensing state of cell and writing data in the cell1 horizontal line (word line WL) is used to select a row of cells for writing or reading and to prevent the unselected rows of cells from being disturbed.Circuit Operation:The cell has two stable states: 0 and 10 State = Node X0 high and Node X1 low; T2 & T5 are ON, T1 & T6 are OFF.1 State = Node X1 high and Node X0 low; T1 & T6 are ON; T2 & T5 are OFF.No dc current flows in either state. Write: raise WL to Vdd; pull one bit line high & pull the other bit line lowRead: raise WL to Vdd; precharge bit lines to Vdd

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SRAM Memory Array OrganizationREAD Operation:Word Decode circuitry selects one of n word lines and drives high to Vdd (say WL2); other word lines held at gnd.Bit Lines all precharged to half VddSelected cells I/O devices turned ON and apply a DV to bit line pairSense amp triggers on bit line DV and stores read data 0 or 1WRITE Operation:Selected WL is driven high to Vdd by word decode circuitry turning ON I/O devices in selected cellsSelected bit column has one BL pulled high to Vdd and the other pulled low to gnd, thus writing the selected cell.Unselected bit columns merely perform a READ operation.R. W. Knepper, SC312page O/V-12

The CMOS D Register (D Flip-Flop)Circuit Schematic:Comprised of two D latches tied in series with input D, output Q, and CLK control line Each D latch is simply constructed out of two inverters cross coupled with a X-gate in the feedback loop and having a second X-gate in series with the inputEach X-gate switch C is closed if its control input is high (Vdd) and open if its control is lowSingle clock fed directly (true) to 2nd latch (slave) and inverted to 1st latch (master).Operation: (positive edge triggered)When CLK goes to zero, master latch is opened to input D (feedback loop is disabled), while slave latch holds previous data and is closed to signal at node QM When CLK goes to Vdd, master latch is isolated from input D (& feedback loop enabled) to hold data, while slave latch opens to receive data from master giving valid Q outputR. W. Knepper, SC312page O/V-13

Design Practicality: Try to minimize the # of transistorsConsider the design of a simple 2 input multiplexor (MUX)Logically it can be described with four CMOS circuits (14 transistors)Two 2-input ANDs (4 transistors each)One 2-input OR (4 transistors)One inverter (2 transistors)In practice it is more likely to be built with only six CMOS transistors by using two complementary transmission gates and a CMOS inverter (as shown at left below)If S is low, the upper transmission gate is closed (both transistors) and Z = AIf S is high, the lower transmission gate is closed (both transistors) and Z = B

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Design Precision: Circuit Timing DelayShown at the left is the logic circuit schematic for the function F=(XY) + (XYZ) using basic CMOS ANDs, an OR, and two invertersEach circuit has some intrinsic delay which depends on the CMOS technology and the circuit designOutputs switch some time after the inputs switch by an amount of time equal to the basic gate delayAny circuit design of several combinational logic stages tied together in serial fashion must take into account the delay through each circuit in order to prevent false (unexpected) logic levelsSee waveforms at leftR. W. Knepper, SC312page O/V-15

Programmable Logic DevicesPLD (generic) An IC where the logic function can be programmed into it after manufactureIn some cases, it can be reprogrammed if a bug in the design is discoveredPLA (programmable logic array)The first PLD on the marketTwo level AND/OR array structure with user programmable connectionsPAL (programmable array logic)Appeared on the scene after PLAsLower costThe MSI of the programmable industry; sometimes simply called PLDROM (read-only memory)Originally not thought of as a programmable device at all simply a memory for holding machine specific information, such as the control store operationCPLD (complex programmable logic device)A collection of PLDs on a chip with programmable on-chip interconnectionsFPGA (field programmable gate array)Another scheme developed same time as CPLDLarge number of basic logic blocks (simple gates) with prog X/Y interconnection R. W. Knepper, SC312page O/V-16

Programmable Logic Devices: CPLD vs FPGAComplex Programmable Logic Device (CPLD): see (a) belowMost of todays CPLDs are simply a collection of PLDs on a chip with interconnected by programmable interconnect (wiring)Field Programmable Gate Array (FPGA): see (b) belowFPGAs are comprised of basic logic blocks interconnected by X and Y wiring channelsR. W. Knepper, SC312page O/V-17

Integrated Circuit DesignIC design:Chip WaferModuleBoardLevel of integration:SSI 1-20 gates/chipMSI 20-200 gates/chip LSI 200-200,000 gates/chipVLSI over 1,000,000 transistors/chipIn 2001 processor chips with over 100M transistors are being designedDesign StylesStandard cellGate arrayFull customLogic design toolsSchematic capture (Cadence Composer)Logic behavioral description (Verilog or VHDL)Logic simulation (Verilog XL)R. W. Knepper, SC312page O/V-18

Technology Scaling and the Semiconductor IC IndustryOver the past 25-30 years the semiconductor industry has been improving technology by making continual advances in lithography and tooling, as well as, basic silicon device technology improvements and reduced power supply voltage.A factor of 0.5X improvement in linear scale dimension roughly every 3 years has allowed a 4X increase in density (memory bits/mm2 or logic ckts/mm2) every 3 year generationNamed Moores Law for Gordon Moore of Intel who was the first to identify this expontial improvement and quantify itAlong with a 4X improvement in density every generation has come typically a 2X improvement in raw performance (device switching speed)A continuation of Moores Law has allowed reductions in cost (per bit or per transistor) in an expontial fashion for the past 25-30 yearsResulted in low cost digital electronics and processor chipsWill Moores Law run out of gas?Due to fundamental limits in IC technology physics, Moores Law is starting to slowGate oxide tunneling leakage current for Tox < 15-20 ATransistor Ioff leakage becomes too high for Leff < 50 nmWide variation in device parameters (Vt, mobility) due to discrete doping atom effectsResearchers are looking for alternative materials to replace silicon, SiO2, etc.R. W. Knepper, SC312page O/V-19

Processor Design versus Digital Logic DesignSC312 deals primarily with the design of processorsALU/CPU/RegistersMemory and Virtual StoreSequential logic designControl unitPipeliningInstructions/microcode programmabilityRISC vs CISC instruction set architecture (ISA)We will touch briefly on other types of digital logic ICsFSM (finite state machine)FPGA (field programmable gate array)ASIC (application specific IC)CPLD (complex programmable logic device)Digital design is becoming pervasive in all areas of electronics:Processors, controllers, and coresConsumer electronicsTelecommunications/wirelessAutomotiveWired networking (routers, etc.)R. W. Knepper, SC312page O/V-20