Scaling of MOSFET Transconductance with Gate Oxide Thickness and Effect of Remote Charge Scattering

Khaled Ahmed, Philip Kraus, Chris Olsen and Faran Nouri Gate & Capacitor Module, Applied Materials, Inc., Santa Clara, California, USA

khaled_ahmed@amat.com

Abstract

In this work, MOSFET maximum transconductance (gmmax) scaling with gate oxide thickness is discussed. It is shown that gmmax scales with capacitance-extracted-thickness (CET) in inversion as α−CET , where 0.7 <α<1.0, which is less than αideal = 1.0. It is demonstrated that this may be partly explained by the non-universality of effective mobility due to effects such as remote-charge-scattering that become significant for tox,physical < 15Å. The implication of this result for benchmarking new gate dielectric materials is demonstrated.

1. Introduction

Scaling of CMOS devices beyond 0.1-µm node requires scaling of the gate dielectric thickness below 15Ă. The scaling of SiO2 will be limited by high gate leakage current and boron penetration [1]. A global search for medium- and/or high-κ materials for gate dielectric is underway. The use of high-κ materials makes the dielectric film physically thicker resulting in reduced gate leakage with respect to pure SiO2 film with same electrical thickness. The successful material candidate will have to meet target inversion capacitance-extracted-thickness (CET or Tox.inv), lifetime, and other process integration requirements. The use of new materials such as nitrided oxides with large amount of nitrogen incorporated into a starting thin SiO2 film may result in oxide charge and traps that may affect transistor parameters such as carrier mobility, drive current and threshold voltage. Degradation of these parameters with respect to values obtained on pure (or lightly nitrided) oxide with same electrical thickness need to be constantly monitored in the course of developing the new dielectric materials. Physics-based scaling models of device parameters may be used for benchmarking a given dielectric with given CET versus SiO2.

In this paper, the scaling of gm with electrical thickness is investigated using both experimental data and theoretical models that consider mobility dependence on gate voltage and physical oxide thickness.

2. Theory

The MOSFET transcondutance (gm = ∂Id/∂Vg) is typically measured in the linear regime (Vd ≈ 50-100mV) and used as indirect monitor of inversion carrier mobility. In the linear regime, the drain current can be expressed as [2]:

deffid VQLWI µ)/(≈ (1) Where W ≡ channel width, L ≡ channel length, Qi ≡

inversion charge density (C/cm2), µeff ≡ effective mobility, and Vd ≡ drain voltage. The transconductance can be expressed as:

∂∂

+∂∂=

g

effi

g

ieffdm V

QVQVLWg

µµ)/( (2)

Conventionally, the following assumptions have been made for simplification:

g

ieff

g

effi V

QV

Q∂∂<<

∂∂

µµ

(3.a)

g

iinvg V

QC∂∂≈, (3.b)

)(CETfeff ≠µ (3.c) When (3) is valid, the scaling of transconductance with electrical thickness in inversion (including quantum and polydepletion effects) may be described by:

1)/( −≈ CETVLWg effoxdm µε (4)

Where CET

C oxinvg

ε≡, is the gate capacitance in

inversion. It should be emphasized that Cg,inv appearing in (3.b)

is the slope of the integrated gate capacitance from Vfb to any gate voltage in inversion (i.e. the average of inversion gate capacitance over a range of gate voltages). This can result in a slightly different CET than when the capacitance at one inversion bias is used to estimate CET.

Deviation from (3) will result in a slower gm dependence on CET, i.e. α−∝ CETgm with α < 1.0.

In order to check the validity of assumption (3.a), theoretical Id-Vg curves were generated for different oxide thicknesses using a Equation (1). The inversion

charge density was calculated versus Vg using models that include quantum mechanical and polydepletion effects. A universal field-dependent model is used for effective electron mobility.

In Figure 1, both gm,max and

maxmax, )/(

g

ieffdm V

QVLWf∂∂

= µ (which is the

approximation for gm,max when condition (3.a) is satisfied) are plotted versus CET. It is seen that the non-negligible mobility dependence on Vg results in a slightly smaller exponent.

Figure 1. Theoretical dependence of gm,max on CET with and without taking into account Vg dependence of effective mobility.

Fitting gm,max versus CET or CET @ maximum Cg,inv

to a power law results in different exponents as shown in Table 1.

Table 1. Extracted exponent of gm,max dependence on CET with (gm,max) and without (fm,max) taking into account Vg dependence of effective mobility. Versus CET Versus CET @ max Cg,inv

gm,max 0.98 0.94 fm,max 1.03 0.98

3. Experimental

Dual-gate CMOS devices were fabricated using standard 0.18µm process with three RTO gate oxides with physical thicknesses of 13, 16.5 and 20 Å. Capacitance-Voltage measurements were done on 15×4 µm2 n-channel devices in order to extract CET from maximum capacitance in inversion. An Agilent 4284 LCR meter with a frequency of 1 MHz was used to minimize measurement errors due to high gate leakage. Drain current versus gate voltage (Id-Vg) was measured using Agilent 4156 Parameter Analyzer using Vd = 100mV on n-channel devices with W = 15 um and L = 4, and 0.5 um. The maximum transconductance is plotted versus CET in Figure 2 for L = 0.5um. A power law is

used to fit the data. The maximum transconductance is proportional to CET -α (α = 0.73).

Figure 2. Experimental of gm,max on CET measured on nmos devices with RTO gate oxides with different thickness.

The exponent α was extracted from Id-Vg data

measured on devices with different channel lengths and using different Vd in the linear regime (20 mV to 200 mV). The results are shown in Figure 3. For L = 4.0 µm, the dependence of α on Vd may be explained by the effect of gate tunnelling current which is not small enough compared to drain current for long channel lengths and small Vd. For L = 0.5 µm, a is approximately independent of Vd as the gate current is now much smaller than the drain current (Id/Ig ∝ L2). As indicated from Figure 3, smaller channel length and/or higher Vd are needed for Id-Vg measurements on MOSFETs with high gate tunnelling current.

Figure 3. Extracted exponent of gm,max dependence on CET from data shown in Figure 2. For thin oxides, gate tunnelling current may affect measurements if the channel length is too long or the drain voltage is too small for Id >> Ig.

In order to explain the observed slower scaling of

maximum transconductance with CET (i.e. α < 1.0), the effective mobility must be a function of oxide thickness. That is, condition (3.c) is not satisfied. While it is not guaranteed that the surface roughness and/or fixed charge density are maintained when the oxide thickness

is scaled down by changing oxidation process variables, remote charge scattering (RCS) due to charge impurities in the gate material can result in larger mobility degradation for thinner oxides [3,4].

4. Effect of Remote-Charge-Scattering on gm Scaling with Oxide Thickness

Mobility degradation due to remote charge scattering (RCS) has been recently calculated as function of gate oxide thickness, channel and polygate doping densities [3,4]. These models are used here to estimate the degradation and scaling of transconductance with gate oxide thickness. The effect of RCS on effective mobility is calculated using Matthiessen’s rule:

RCSphononcoulombsr.

11111µµµµµ

+++=eff

(5)

Where surface roughness scattering, Coulombic scattering, and phonon scattering mobility components are calculated using The University of Texas universal mobility model [5]. The RCS mobility component is calculated using two models shown in [3] and [4]. The inversion charge density as function of gate voltage is calculated including both quantum mechanical and polydepletion effects. Equation (1) is then used to calculate theoretical Id-Vg for a given oxide thickness.

The transconductance is calculated using: g

dm V

Ig∂∂= . In

Figure 4 the transconductance as a function of vertical gate field is plotted for different gate oxide thickness (7, 10, 15, and 20Å) with and without taking the effect of RCS into account. The RCS mobility component was calculated using the methodology shown in Ref. 3. The RCS effect results in degradation of gm,max that is not a function of the gate oxide quality, but its physical thickness.

Figure 4. Theoretical gm versus field with and without taking the RCS effect into account.

The percentage degradation of gm,max due to RCS is

plotted versus oxide thickness in Figure 5. For oxide

thickness of 10Å, the estimated degradation in gm,max is 3-20%. The percentage degradation of gm,max due RCS increases as the gate oxide thickness decreases.

Figure 5. Theoretical estimation of gm,max degradation due to RCS as a function of gate oxide thickness.

The scaling of gm,max with gate oxide thickness is

shown in Figure 6 with and without taking the RCS effect into account. Depending on the model used to estimate the RCS mobility, the gm,max scales with CET as:

am CETAg −×=max, (6)

with α ranging from ~0.45-0.88 when gm,max is plotted versus CET @ maximum Cg,inv, and from 0.47-0.92 when gm,max is plotted versus CET from average Cg,inv. The experimentally obtained value of α = 0.73 shown in Figure 2 may be very well explained by the RCS effect.

Figure 6. Theoretical dependence of gm,max on CET with and without taking into account the RCS effect.

5. Application

Benchmarking new gate dielectric materials such as heavily nitrided oxides and/or high-κ materials versus reference pure oxide with physical thickness 7-12Å requires normaliztion of device parameters such as gm,max to dielectric thickness. For a given gate dielectric, the percentage degradation in gm,max that is calculated using

conventional scaling law of gm,max (gm,max ∝ CET -1) of SiO2 is overestimated. A significant portion of this degradation results from “imaginary” higher gm,max of a pure gate oxide with thickness of 7-12Å where remote-charge-scattering would have resulted in large mobility degradation (3-20% for a 10Å oxide).

6. Conclusion

The scaling of MOSFET transconductance with gate oxide thickness is discussed. For ultra-thin oxides (10-20Å), the maximum transconductance gm,max scales with electrical oxide thickness as α−CET with α < 1.0. If the channel length used for measurement of gm,max is too large, or the drain voltage is too small to maintain Id >> Ig, α can be underestimated. The use of ideal scaling law with α = 1.0 in normalizing gm,max when benchmarking gate dielectric materials (such as high-κ or nitrided oxides) to reference pure oxides may lead to overestimation of gm,max degradation. Remote-charge-scattering from impurities in the gate material was shown to be partly responsible for the deviation from gm,max standard scaling with oxide thickness.

7. References

[1] D. A. Buchanan, “Scaling the dielectric thickness: Materials, Integration and Reliability,” IBM J. Res. Develop., vol. 43 no. 3 May 1999.

[2] Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices. New York, NY: Cambridge University Press, 1998.

[3] S. Saito et al., “Quantitative Understanding of Mobility Degradation due to Remote Charge Scattering,” IWGI, Tokyo, Japan, 2001.

[4] M. Krishnan et al., “Remote Charge Scattering in MOSFETs with Ultra-Thin Gate Dielectrics,” in IEDM tech. Dig., p. 571, 1998.

[5] H. Shin et al., “Physically-based Models for Effective Mobility and Local-Field Mobility of Electrons in MOS Inversion Layers,” Solid State Electron., vol 34, p. 545, 1991.