SCAN Shift Register/Parallel Load

RegisterLaboratory 3

Objectives• Build upon the understanding of

CMOS circuits and systems• Build upon the experience gained in

lab2 ( Use of place and route)

Design• Size=20 bits ( Based on your Full Adder

design)• Should have Serial and Parallel Load

capability• Should use 2 Clocks and their

complements.– CLKA, CLKAbar, CLKB and CLKBbar

• Build using the standard cells of ECE 4/525 and ECE 4/526

Design

Design

Design

Design

Lab Reports• Should contain the Schematic, Physical

Layout (from Silicon Ensemble)• All the Functional Data: Flush delay

tables, Maximum Frequency of operation,

• Mention the input pattern for the Scan Capture

• Mention the pattern for Parallel Load

Lab Report• Show waveforms with the different

corner model for the nominal load and nominal input slew

• Perform Verilog simulation on the extracted layout (Physical Layout out of Place and Route)