schematic - analog.com · schematic drawing no. scale code id no. sheet of rev. d a a e n vc l g es...

C 23MAY13

D.SMITH10JAN13B

D.SMITH

A D.SMITH18SEP12

18SEP12

18SEP12

CHANGES PER ECR-040673

INITIAL RELEASE

D 07AUG13 D.SMITH

E 02JUL14 D.SMITHCHANGES PER ECR-046413

D.SMITH08AUG14F CHANGES PER ECR-046972



1 8

Package: 24-lead SOIC_W

AD37913HW TYPE: Customer Evaluation Board

-

F-1:1

02-033799

G CELEDONIO

R MACDONALD

D SMITH

M LABRANCHE

G CELEDONIO

D SMITH

N/A

N/A

N/A

J KEANE

REV

2REVISIONS

1

OWNED OR CONTROLLED BY ANALOG DEVICES.THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTSPURPOSE DETRIMENTAL TO THE INTERESTS OF ANALOG DEVICES. JP#USED IN FURNISHING INFORMATION TO OTHERS, OR FOR ANY OTHER

8

CONNECTORFUNCTIONCODE DEVICE

2

2

6JUMPER TABLE

4

7

5

A

3

DATE APPROVED

D

B

DESCRIPTION

34

OFFON

5

57

OEM PART# HANDLER

6

C

B

8

SOCKET OEMBK/BD SPEC.P.O SPEC.

A

1

RELAY CONTROL CHART

3 14

C

NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR IN PART, ORTHIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC. IT IS

CHECKER

DESIGNER

PTD ENGINEER

TEST ENGINEER

DECIMALS

X.XXX +-0.005X.XX +-0.010

MASTER PROJECT TEMPLATE

TOLERANCES

+-1/32FRACTIONS

+-2SIZE

DDDD

SCHEMATIC

DRAWING NO.

SCALE CODE ID NO.SHEET OF

REV.

DA AENV CL GSE

ODATE

ANGLES

UNLESS OTHERWISE SPECIFIED DIMENSIONS ARE IN INCHES

TESTER TEMPLATE

TEMPLATE ENGINEER

HARDWARE SERVICES

HARDWARE SYSTEMS

COMPONENT ENGINEER

TEST PROCESS

HARDWARE RELEASE

* SEE ASSEMBLY INSTRUCTIONS

CONTROL

D

EEPROM

CF OPTO

12V

RS485

12V

FOOT PRINT ONLY

2 8

<DESIGN_VIEW>


1:1

F02-033799

D SMITH

DNI

1/2 AA

DNI

0

10K

DNI

10K

DNI

10K

DNI

10K

DNI 10K

DNI

2K

2KDNI DN

I

470U

F

120OHM

DNI

DNI

47UF

DNI

LM1117MP-3.3/NOPB

DNILM1117MP-3.3/NOPB

DL4001-TP

DNI

ADM487EARZ DNI

DNI

SFH6186-3TDNI

SFH6186-3T

DNI SFH6186-3T

SFH6186-3T

DNI

DNI

SMA6J5.0A-TR WHT DNI

WHT

ORG

DNI

DNI

WHT

WHT

WHT

WHT

WHT

DNI

WHT

DNI

DNI

DNI

DNI

DNISFH6186-3T

LNJ2

08R8

ARA

(RED

)

LNJ2

08R8

ARA

(RED

)

DNI

LNJ2

08R8

ARA

(RED

)

DNI DNI

DNI

DNIDL4001-TP

DL40

01-T

P

DNI

DNI

47UF

DNI

DNI

DL4001-TP

DNI

470U

F

RED

AT24C64D-SSHM-T

4.096MEGHZ

WHT

WHT

RED

VIOLET

GRN

BLU

WHT

GRN

RED

BLU

VIOLET

GRN

RED

BLU

VIOLET

DNI

15UF

22PF

WHT

22PF

C

B

A

BLK

1K

DNI

DNI

1K

1K

DNI

1K

DNI

1K

DNI

0

0

DNI 0

DNI

80.6

DNI

80.6

DNI

80.6

0.1U

F

DNI

0.1U

F

DNI

0.1U

F

DNI

0.1U

F

DNI

0.1U

F

DNI

0.1U

F

DNI

0.1U

F

DNI

0.1U

F

DNI

0.1U

FDNI

0.1U

FDNI

0.1U

F

DNI

0.1U

F

10UF

10UF

DNI

DNI

10UF

C1 C2

VR1

VR2

U2

U3

U4

U1

R6

R7

R8

C3C4

C5

C20

C13

C9C8

C12

C15

C7

C6 C10

R10

U6

R18

R19

R16

R14

U5

R13

R15

TP26

TP27

CR1

C22

D1

D2

D3

D4

C16

E1

C11BT1

R12

C17

U7C21

DGND

+V

TP25

TP24

R9

R2

R3

TP18

TP19

TP20

TP21

TP22

TP23

Y1

DS3

DS2DS

1

R4 R5R1

R17

GND

TP3

TP2

TP5

TP4

TP1

TP10

TP6

TP7

TP8

TP9

TP11

TP12

TP13

TP14

TP15

R11

C18

C14

C19

V_CORE

V_ADE

V3P3_RS485

V3P3_RS485

CLKORDYB_B

V_EXT

V_EXT

EXLVL

V3P3_RS485

V_EXT

V3P3_RS485

V_CORE

V3P3_RS485

+V_MTR

WPSCL

SDA

MOSI

RXD6

CLKORDYB_A

SCLK

V_EXTV_CORE

MISO

V_EXT

V_EXT

CSB_A

V_ADE

CSB_B

V_ADE

CLKORDYB_CCSB_C

V_EXT

CF3CF2

CF1

V_ADE

CF1

CF2

CF3

TXD6

CLKORDYB_A

CLKORDYB_B

VDD_MCU

1

3 24

1

3 24

1

2 3

4

1

2 3

4

1

23

4

1

2 3

4

PN

PN

PN

PN

673

4

5

2 1

81

2 3

4

11

CA

P N

CA

CA

CA

CA

1 2

PN

123

4

65

8

71

1

1

1

11

11

11

1 2

CA

CA

CA

1

DGND1

C

A

DGND

DGND1DGND1

VCC

BA

GND

DIDE

RE_NRO

DGND

DGNDDGND

DGND1DGND1 DGND1 DGND1DGND1

DGNDDGND

C

A

C

A

C

A

C

A

DGND

OUT1IN

OUTADJ

AGND_C

OUT1IN

OUTADJ

AGND_B

ADE7913DUT_REF

IMINIPIN

V1PIN

V2PIN

CLKODRDYBCSB

MISOMOSISCLKVDD

XTAL1XTAL2

AGND_ADC1

ADE7913DUT_REF

IMINIPIN

V1PIN

V2PIN

CLKODRDYBCSB

MISOMOSISCLKVDD

XTAL1XTAL2

AGND_ADC1

ADE7913DUT_REF

IMINIPIN

V1PIN

V2PIN

CLKODRDYBCSB

MISOMOSISCLKVDD

XTAL1XTAL2

AGND_ADC1

DGND

AGND_A

DGND

DGND1

DGND

DGND

DGND

VCC

WPGND

A2A1A0

SCLSDA

DGND DGND

DGND DGND DGND

DGNDDGND

D

THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.

IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,

OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS

THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS

AC

IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.

2

SCALE

DDDSIZE

D

REV

SHEET

1

1

A

234

35

8

D

7

678

A

B

C C

D

5

4

APPROVED

B

6

DESCRIPTION

REVISIONS

OF

OL GE

OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.

EAN

V

OF ANALOG DEVICES.

SCHEMATICS

PTD ENGINEER

DESIGN VIEW

REV DATE

BOOT PIN

JTAG PORT LCD CONNECTOR

NEED TO VERIFY PIN OUT

SERIAL DOWNLOAD PORT

ADE7913 EVAL PORT

3 8

<DESIGN_VIEW>


1:1

F02-033799

D SMITH

0.1U

F

0.1U

F

DNI

0.1U

FDNI

0.1U

F

DNI

0.1UF

DNI

0.1U

F

DNI

0.1U

F

DNI

DNI

1K

DNI 1K

DNI

DNI

DNI

DNI

DNIDNI

DNI

DNI

0.47

UF

FDV301N

ADUC7026BSTZ

FDV301N

K24A

FDV301N

0.47

UF

K24A

K24A

TSW-110-08-G-D

TSW-106-08-G-D

MOLEX22-03-2031

DNI

DNI

DNI

DNI

DNI

DNI

DNIDNI

DNI

TSW-104-08-G-S

DNI B3S1

000

DNIB3S1

000

DNI

K24A

DNI

K24A

DNIK24A

DNI

DNI

DNI

DNI

K24A

K24AK24A

K24A

K24A

K24A

K24A

K24A

DNI

K24A

K24A

DNI

K24A

DNI DNI

K24A

DNI

32.7

68KH

Z

67996-416HLF

10K

DNI

10K

DNI

10K

DNI

DNI

10K

10K

DNI

10K

DNI

10K

DNI 10K

DNI 10

K

DNI

DNI

100K

DNI

100K

100K

DNI

0

0

0

0

0

0

0

0

00

TP50

C31

R35R40

P5

R43

R30

R29

C29

R28

TP44TP43TP42TP35

TP38

TP36

TP32 TP33

TP31

TP30

TP41

TP40

TP39

TP37

TP34

TP28

TP29

C28

C30

C25

C23

C24

Q2Q1Q3

Y2

C27

R24

R23

P2

C26

R25

R26

R27

R36

R37

R38

R31

R32

R33

R39

R34

R42

R41

S2S1

U8

P4

P3

R22

R21

R20 P1

V_CORE

EXLVL

38KHZCOMM

V_CORE

TDO

TCK

V_CORE

TRST

RESET

TDI

RXD6

TCK

TDI

TMS

CF3_BSCLKMISOCF1_B

CLKORDYB_C

CF2_BCF1_B

CF1

V_CORE

V_CORE

CF2_B

KEYWAKE

ALARM

KEYPRG KEYWAKE

V_CORE

V_CORE

V_CORE

V_CORE

SCL

MOSI

CSB_A

TXD6

TMS

RXD_IRTXD_IR

TEST

TRST

TDO

CF2

SCLSDACOMM38KHZ

V_EXT

TXD_IRALARM

CF1RXD_IR

V_CORE

RESET

WP

V_CORE

V_CORE

CF3_B

CSB_C

CSB_B

SDA

KEYPRG

CF3

MISO

CSB_B

CLKORDYB_C

MOSI

CSB_C

CSB_A

SCLK

RESET

TEST

VDD_MCU

1

16151413121110987654321

111

1

1

1

1

1

11

1

1

1

1

1

1

1

2

1

3

2

1

3

2

1

3

21

4321

3 421

3 421

4445

68

14

23

15

22 37

67

1918

66 65 64 63

5655

4746

393832313029

48

363533

17

5049

42

5152

57585960

6162

43

21 3424

16

27

41

40

54

26

53

25

8

28

75 6970

13121110

20

74 73 72 71

9

76

7654321

80 79 78 77

321

121110987654321

2019181716151413121110987654321

DGND

DGND

DGND

DGND

DGND

DGNDDGNDDGND

S

D

G

S

D

GS

D

G

DGND

DGND

DGND

DGND

DGND

DGND

DGND

DGND

DGND

DGNDDGND

DGND

DGNDDGND

DGND

ADC3

/CM

P1AD

C2/C

MP0

ADC1

ADC0

ADC1

1DA

CVDD

AVDD

2AV

DD1

AGND

2AG

ND1

DACG

NDDA

CREF

VREF

REFG

NDP4

.5/A

D13/

PLAO

[13]

P4.4

/AD1

2/PL

AO[1

2]P4

.3/A

D11/

PLAO

[11]

P4.2

/AD1

0/PL

AO[1

0]P1

.0/T

1/SP

M0/

PLAI

[0]

P1.1

/SPM

1/PL

AI[1

]

P1.2/SPM2/PLAI[2]P1.3/SPM3/PLAI[3]

P1.4/SPM4/PLAI[4]/IRQ2P1.5/SPM5/PLAI[5]/IRQ3

P4.1/AD9/PLAO[9]P4.0/AD8/PLAO[8]

IOVDD2IOGND2

P1.6/SPM6/PLAI[6]P1.7/SPM7/PLAO[0]

P2.2/RS/PWM0L/PLAO[7]P2.1/WS/PWM0H/PLAO[6]

P2.7/PWM1L/MS3P3.7/AD7/PWMSYNC/PLAI[15]P3.6/AD6/PWMTRIP/PLAI[14]

XCLKIXCLKO

P0.7/ECLK/XCLK/SPM8/ PLAO[4]P2.0/SPM9/PLAO[5]/CONVSTART

IRQ1/P0.5/ADCBUSY/PLAO[2]/MS0

IRQ

0/P0

.4/P

WM

TRIP

/PLA

O[1

]/MS1

P3.5

/AD5

/PW

M2L

/PLA

I[13]

P3.4

/AD4

/PW

M2H

/PLA

I[12]

RST

P2.6

/PW

M1H

/MS2

P2.5

/PW

M0L

/MS1

P0.3

/TRS

T/A1

6/AD

CBUS

YP2

.4/P

WM

0H/M

S0P3

.3/A

D3/P

WM

1L/P

LAI[1

1]P3

.2/A

D2/P

WM

1H/P

LAI[1

0]P3

.1/A

D1/P

WM

0L/P

LAI[9

]P3

.0/A

D0/P

WM

0H/P

LAI[8

]DG

NDLV

DDIO

VDD1

IOG

ND1

P0.2

/ PW

M2L

/BHE

TDO

TCK

P0.6

/T1/

MRS

T/PL

AO[3

]/AE

BM/P0.0/CMPOUT/PLAI[7]/MS2P4.7/AD15/PLAO[15]P4.6/AD14/PLAO[14]P2.3/AEP0.1/PWM2H/BLETDITMSDAC3/ADC15DAC2/ADC14DAC1/ADC13DAC0/ADC12ADCNEGGNDREFADC10ADC9ADC8ADC7ADC6ADC5ADC4

DGND

D





AC


2

SCALE

DDDSIZE

D

REV

SHEET

1

1

A

234

35

8

D

7

678

A

B

C C

D

5

4

APPROVED

B

6

DESCRIPTION

REVISIONS

OF

OL GE


EAN

V

OF ANALOG DEVICES.

SCHEMATICS

PTD ENGINEER

DESIGN VIEW

REV DATE

THIS ADAPTS THE METROLOGY BD TO THE SDP AS AN EVAL BD

3.3V

THIS IS THE SDP INTERFACE BD

SDP INTERFACE

5V ID EEPROM

12V

SDPINTERFACE

4 8

<DESIGN_VIEW>


1:1

F02-033799

D SMITH

100K

100K

100K

100K

DNI

10K

120OHM

RED

LM1117MP-3.3/NOPB

470UF

24LC32A-I/MC

FX8-120S-SV(21) FX8-120S-SV(21)

BLK

RED

47UF

0

DNI

0

DNIDNI

0

0.1U

F

0.1U

F

PPTC082LFBN-RC

R45

P8

DGND2

+V2

C34 C35

VR3

R46 R48

R47

C32 C33

E2

TP45

R52

R50

R49 R51U9

P8

P6

RESETB_SDP

MISO_SDP

VDD_SDP_ADE

VDD_SDP_ADE

USB_VBUS

VDD_SDP_ADEVDD_SDP_ADE

VDD_SDP_ADE

SDA_SDPSCL_SDP

EEPROM_A0

EEPROM_A0

CSB_B_SDPCSB_C_SDP

CLKORDYB_C_SDP

SCLK_SDPMISO_SDPMOSI_SDP

RESETB_SDP

SCL_SDP

CSB_A_SDP

SDA_SDP

USB_VBUS

VDD_SDP_ADEVDD_SDP_ADEVDD_SDP_ADE

SCLK_SDP

CLKORDYB_C_SDPCSB_A_SDP

CSB_C_SDP

CSB_B_SDP

MOSI_SDP

123456789

101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960

1

1

PN

1

3 24

PN

1 2

1

123

PAD

65

8

4

7

1201191181171161151141131121111101091081071061051041031021011009998

96

9493929190

8685848382818079787776757473727170696867666564636261

95

97

16

98

654321

7

1112

10

15

1314

898887

GNDGND

GND

GND

GND

PAD

VCCWP

SCLSDAVSS

A2A1A0

GND

GND

GND

GNDGND

OUT1IN

OUTADJ

GND

D





AC


2

SCALE

DDDSIZE

D

REV

SHEET

1

1

A

234

35

8

D

7

678

A

B

C C

D

5

4

APPROVED

B

6

DESCRIPTION

REVISIONS

OF

OL GE


EAN

V

OF ANALOG DEVICES.

SCHEMATICS

PTD ENGINEER

DESIGN VIEW

REV DATE

THIS IS A SECTION OF THE BOARD TO BE SNAPPED OFF

5 8

<DESIGN_VIEW>


1:1

F02-033799

D SMITH

DNI0

DNI DNIK24AK24AK24AK24A

DNI

DNI

DNI

K24A

DNI

K24A

DNI

DNI

104352-8

LEODB25PLURL2

P9

R44

TP16 TP46 TP47

TP48

TP51 TP49

P7

RESET_A

CSB_B_A

CLKORDYB_C_A

VDD_MCU_A

SCLK_A

VDD_MCU_A

MISO_ACLKORDYB_C_ACLKORDYB_C_A

MOSI_A

CSB_B_A

CSB_C_A

CLKORDYB_C_A

CSB_A_A

SCLK_A

CSB_N_A

CLKORDYB_C_A

CSB_A_A

CSB_C_A

MISO_A

MOSI_A

VDD_MCU_A

VDD_MCU_A

16151413121110987654321

1 1 1 1 1 1

25242322212019181716151413121110987654321

D





AC


2

SCALE

DDDSIZE

D

REV

SHEET

1

1

A

234

35

8

D

7

678

A

B

C C

D

5

4

APPROVED

B

6

DESCRIPTION

REVISIONS

OF

OL GE


EAN

V

OF ANALOG DEVICES.

SCHEMATICS

PTD ENGINEER

DESIGN VIEW

REV DATE

CLOSE TO PIN 1 CLOSE TO PIN 8 CLOSE TO PIN 9

SUPPLY BYPASS

V1P AND VM

NOTE:KEEP THE HIGH FREQ BYPASS CAP(0.1UF) CLOSE TO THE DUT PINKEEP THE VDD BYPASS CAP CLOSE TO DUT PIN19LAYOUT NOTE:

SUPPLY BYPASS

LAYOUT NOTE:

PRIMARY SIDESECONDARY(ISO)SIDE

TEST PROBE POINTS FOR PRIMARY GROUND

1. KEEP THE BYPASS CAP CIRCUITS CLOSE TO THE DUT PINS IN THE FOLLOWING ORDERA.) REF B)LDO C.)VDDISO AND WITH HIGH FREQ. CAPS(0.1UF) CLOSEST

NET NAME SWAP TO REFLECT THE NEW SYMBOL YET TO BE CREATED.

ANALOG INPUT PER PHASE

6 8

<DESIGN_VIEW>


1:1

F02-033799

D SMITH

0

DNI

51DNI

51

1K

1K

1K1K

1K

DNI

DNI

DNI

DNI

DNI

DNI

DNI

DNI

DNI

DNI

.033

UF

TS4148 RZ

TS4148 RZ

150OHM

.033

UF

150OHM

150OHM

150OHM

150OHM

.033

UF

TS4148 RZ

4.7U

F

0.1U

F

.033

UF

TS41

48 R

Z

DNI

ADE7913

DNI

.033

UF

0.1U

F

4.7U

F

10UF

0.1U

F

TS41

48 R

Z

.033

UF

TS41

48 R

Z

10UF

0.1U

F

TS41

48 R

Z.0

33UF

TS4148 RZ

TS41

48 R

Z

TS4148 RZ

0

0

00

0

330K

330K 330K 330K

330K 330K

0

D8_A

D10_A

D7_A

D9_AC1

A_A

C2A_

A

C14A

_A

C13A

_A

C6A_

A

C5A_

A

C4A_

A

C3A_

AR7_A

R22_A

R10_AR5_AR1_A

R11_AR6_AR2_A

R16_A

R15_A

R13_

AR1

2_A

R14_

A

C15_

AC1

2_A

C9_A

C10_

AC1

1_A

C8_A

C7_A

R4_A

R3_A

R20_A

R21_A

U1_A

R19_A

R9_A

R8_A

E2_A

E1_A

E3_A

E5_A

E4_A

D4_AD5_AD2

_AD1

_A

D6_A

D3_A

VDDAGND_ADC

LDO

V2PIN

V1PIN

IMIN

AGND_ADC1 AGND_ADC

IPIN

AGND_ADC

AGND_ADC

V2P

VDDISO

CLKODRDYB

CSBV2P

MOSIIM

SCLK

XTAL1

VDDISO

REF

AGND_ADC

LDOREF

XTAL2

MISOIP

VM

VM

AGND_ADC

V1P

AGND_ADC

V1P

IM

IP

AGND_ADC

AC A

C

AC A

C

21

21

21

21

21

AC

ACA

CA

C

A

CAC

1413

5

119

34 17

9

1615

876

10

220

11

18

12OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

DGND

DGND

CS_N

CLKOUT_DREADY_N

V2P

VMV1P

IMIP

GNDVDD

SCLKMOSIMISO

XTAL2XTAL1

GNDREFGNDISO

LDO

GNDISOVDDISO

D





AC


2

SCALE

DDDSIZE

D

REV

SHEET

1

1

A

234

35

8

D

7

678

A

B

C C

D

5

4

APPROVED

B

6

DESCRIPTION

REVISIONS

OF

OL GE


EAN

V

OF ANALOG DEVICES.

SCHEMATICS

PTD ENGINEER

DESIGN VIEW

REV DATE


SUPPLY BYPASS

V1P AND VM


SUPPLY BYPASS

LAYOUT NOTE:






7 8

<DESIGN_VIEW>


1:1

F02-033799

D SMITH

0

DNI

51DNI

51

1K

1K

1K1K

1K

DNI

DNI

DNI

DNI

DNI

DNI

DNI

DNI

DNI

DNI

.033

UF

TS4148 RZ

TS4148 RZ

150OHM

.033

UF

150OHM

150OHM

150OHM

150OHM

.033

UF

TS4148 RZ

4.7U

F

0.1U

F

.033

UF

TS41

48 R

Z

DNI

ADE7913

DNI

.033

UF

0.1U

F

4.7U

F

10UF

0.1U

F

TS41

48 R

Z

.033

UF

TS41

48 R

Z

10UF

0.1U

F

TS41

48 R

Z.0

33UF

TS4148 RZ

TS41

48 R

Z

TS4148 RZ

0

0

00

0

330K

330K 330K 330K

330K 330K

0

D8_B

D10_B

D7_B

D9_BC1

A_B

C2A_

B

C14A

_B

C13A

_B

C6A_

B

C5A_

B

C4A_

B

C3A_

BR7_B

R22_B

R10_BR5_BR1_B

R11_BR6_BR2_B

R16_B

R15_B

R13_

BR1

2_B

R14_

B

C15_

BC1

2_B

C9_B

C10_

BC1

1_B

C8_B

C7_B

R4_B

R3_B

R20_B

R21_B

U1_B

R19_B

R9_B

R8_B

E2_B

E1_B

E3_B

E5_B

E4_B

D4_BD5_BD2

_BD1

_B

D6_B

D3_B

VDDAGND_ADC

LDO

V2PIN

V1PIN

IMIN

AGND_ADC1 AGND_ADC

IPIN

AGND_ADC

AGND_ADC

V2P

VDDISO

CLKODRDYB

CSBV2P

MOSIIM

SCLK

XTAL1

VDDISO

REF

AGND_ADC

LDOREF

XTAL2

MISOIP

VM

VM

AGND_ADC

V1P

AGND_ADC

V1P

IM

IP

AGND_ADC

AC A

C

AC A

C

21

21

21

21

21

AC

ACA

CA

C

A

CAC

1413

5

119

34 17

9

1615

876

10

220

11

18

12OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

DGND

DGND

CS_N

CLKOUT_DREADY_N

V2P

VMV1P

IMIP

GNDVDD

SCLKMOSIMISO

XTAL2XTAL1

GNDREFGNDISO

LDO

GNDISOVDDISO

D





AC


2

SCALE

DDDSIZE

D

REV

SHEET

1

1

A

234

35

8

D

7

678

A

B

C C

D

5

4

APPROVED

B

6

DESCRIPTION

REVISIONS

OF

OL GE


EAN

V

OF ANALOG DEVICES.

SCHEMATICS

PTD ENGINEER

DESIGN VIEW

REV DATE


SUPPLY BYPASS

V1P AND VM


SUPPLY BYPASS

LAYOUT NOTE:






8 8

<DESIGN_VIEW>


1:1

F02-033799

D SMITH

0

DNI

51DNI

51

1K

1K

1K1K

1K

DNI

DNI

DNI

DNI

DNI

DNI

DNI

DNI

DNI

DNI

.033

UF

TS4148 RZ

TS4148 RZ

150OHM

.033

UF

150OHM

150OHM

150OHM

150OHM

.033

UF

TS4148 RZ

4.7U

F

0.1U

F

.033

UF

TS41

48 R

Z

DNI

ADE7913

DNI

.033

UF

0.1U

F

4.7U

F

10UF

0.1U

F

TS41

48 R

Z

.033

UF

TS41

48 R

Z

10UF

0.1U

F

TS41

48 R

Z.0

33UF

TS4148 RZ

TS41

48 R

Z

TS4148 RZ

0

0

00

0

330K

330K 330K 330K

330K 330K

0

D8_C

D10_C

D7_C

D9_CC1

A_C

C2A_

C

C14A

_C

C13A

_C

C6A_

C

C5A_

C

C4A_

C

C3A_

CR7_C

R22_C

R10_CR5_CR1_C

R11_CR6_CR2_C

R16_C

R15_C

R13_

CR1

2_C

R14_

C

C15_

CC1

2_C

C9_C

C10_

CC1

1_C

C8_C

C7_C

R4_C

R3_C

R20_C

R21_C

U1_C

R19_C

R9_C

R8_C

E2_C

E1_C

E3_C

E5_C

E4_C

D4_CD5_CD2

_CD1

_C

D6_C

D3_C

VDDAGND_ADC

LDO

V2PIN

V1PIN

IMIN

AGND_ADC1 AGND_ADC

IPIN

AGND_ADC

AGND_ADC

V2P

VDDISO

CLKODRDYB

CSBV2P

MOSIIM

SCLK

XTAL1

VDDISO

REF

AGND_ADC

LDOREF

XTAL2

MISOIP

VM

VM

AGND_ADC

V1P

AGND_ADC

V1P

IM

IP

AGND_ADC

AC A

C

AC A

C

21

21

21

21

21

AC

ACA

CA

C

A

CAC

1413

5

119

34 17

9

1615

876

10

220

11

18

12OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

DGND

DGND

CS_N

CLKOUT_DREADY_N

V2P

VMV1P

IMIP

GNDVDD

SCLKMOSIMISO

XTAL2XTAL1

GNDREFGNDISO

LDO

GNDISOVDDISO

D





AC


2

SCALE

DDDSIZE

D

REV

SHEET

1

1

A

234

35

8

D

7

678

A

B

C C

D

5

4

APPROVED

B

6

DESCRIPTION

REVISIONS

OF

OL GE


EAN

V

OF ANALOG DEVICES.

SCHEMATICS

PTD ENGINEER

DESIGN VIEW

REV DATE

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