1. Chapter 8 : Serial Communication Interface C28xDigital Signal ControllerTMS320F2812Technology beyond the Dreams Copyright 2006 Pantech Solutions Pvt

2. SCI Pin Connections TX FIFO_0(Full Duplex Shown)TX FIFO_0 TX FIFO_15TX FIFO_15 Transmitter-dataTransmitter-data buffer register buffer register 88 TransmitterSCITXD SCITXD Transmitter shift register shift register Receiver SCIRXD SCIRXD Receiver shift register shift register 88Receiver-dataReceiver-databuffer registerbuffer register RX FIFO_0 RX FIFO_0 RX FIFO_15RX FIFO_15TechnologySCI Device #1beyond the Dreams SCI Device #2Copyright 2006 Pantech Solutions Pvt 3. SCI-A Programmable Data FormatNRZ (nonreturn to zero) format Addr/ Start LSB2 3 4 5 6 7MSB Parity Stop 1 Stop 2 Data This bit present only in Address-bit mode Majority VoteSCICLK(Internal)1 2 3 4 5 6 7 8 12 3 45 6 7 8 1 2SCIRXD Start Bit LSB of Data Falling Edge DetectedNote: 8 SCICLK periods per data bitTechnology beyond the DreamsCopyright 2006 Pantech Solutions Pvt 4. Multiprocessor Wake-Up Modes Allows numerous processors to be hooked up to the bus, but transmission occurs between only two of them Idle-line or Address-bit modes Sequence of Operation1. Potential receivers set SLEEP = 1, which disables RXINT except when anaddress frame is received2. All transmissions begin with an address frame3. Incoming address frame temporarily wakes up all SCIs on bus4. CPUs compare incoming SCI address to their SCI address5. Process following data frames only if address matchesTechnology beyond the Dreams Copyright 2006 Pantech Solutions Pvt 5. Idle-Line Wake-Up Mode Idle time separates blocks of frames Receiver wakes up with falling edge after SCIRXD was high for 10 or morebit periods Two transmit address methods deliberate software delay of 10 or more bits set TXWAKE bit to automatically leave exactly 11 idle bitsIdle periodsof less thanBlock of Frames10 bitsSCIRXD/Last DataSPST AddrSP STData SP ST Last DataSPST Addr SPSCITXD Idle Address frame 1st data frame Idle Period follows 10 bit Period 10 bits 10 bits or greater or greater idleor greaterTechnology beyond the DreamsCopyright 2006 Pantech Solutions Pvt 6. Address-Bit Wake-Up Mode All frames contain an extra address bit Receiver wakes up when address bit detected Automatic setting of Addr/Data bit in frame by setting TXWAKE = 1prior to writing address to SCITXBUFBlock of FramesSCIRXD/ Last Data 0 SP ST Addr1 SP STData 0 SP ST Last Data 0 SP STAddr 1 SPSCITXD First frame within 1st data frame no additional Idle Period block is Address. idle bits needed length of noADDR/DATA beyond stop bits significancebit set to 1Technology beyond the Dreams Copyright 2006 Pantech Solutions Pvt 7. SCI Summary Asynchronous communications format 65,000+ different programmable baud rates Two wake-up multiprocessor modes Idle-line wake-up & Address-bit wake-up Programmable data word format 1 to 8 bit data word length 1 or 2 stop bits even/odd/no parity Error Detection Flags Parity error; Framing error; Overrun error; Break detection FIFO-buffered transmit and receive Individual interrupts for transmit and receiveTechnology beyond the DreamsCopyright 2006 Pantech Solutions Pvt 8. SCI-A Registers AddressRegisterName 0x007050 SCICCRSCI-A commun. control register 0x007051 SCICTL1 SCI-A control register 1 0x007052 SCIHBAUDSCI-A baud register, high byte 0x007053 SCILBAUDSCI-A baud register, low byte 0x007054 SCICTL2 SCI-A control register 2 register 0x007055 SCIRXST SCI-A receive status register 0x007056 SCIRXEMUSCI-A receive emulation databuffer 0x007057 SCIRXBUFSCI-A receive data buffer register 0x007059 SCITXBUFSCI-A transmit data buffer register 0x00705A SCIFFTX SCI-A FIFO transmit register 0x00705B SCIFFRX SCI-A FIFO receive register 0x00705C SCIFFCT SCI-A FIFO control register 0x00705F SCIPRISCI-A priority control registerTechnology beyond the DreamsCopyright 2006 Pantech Solutions Pvt 9. SCI-A Communication Control Register Communications Control Register (SCICCR) 0x007050 76 5 4 3 2 1 0STOPEVEN/ODD PARITY LOOP BACK ADDR/IDLESCI SCISCIBITSPARITY ENABLE ENABLEMODE CHAR2 CHAR1CHAR00 = 1 Stop bit0 = Disabled 0 = Idle-line mode # of data bits = (binary + 1)1 = 2 Stop bits 1 = Enabled1 = Addr-bit modee.g. 110b gives 7 data bits 0 = Odd0 = Disabled 1 = Even 1 = EnabledTechnology beyond the Dreams Control Register (SCICCR) 0x007750] [SCI-B CommunicationsCopyright 2006 Pantech Solutions Pvt 10. SCI-A Control Register 1Control Register 1 (SCICTL1) 0x007051 7 6 5 4 32 1 0reservedRX ERR SW reservedTXWAKESLEEP TXENARXENAINT ENARESET 0 = receiver disabled 1 = receiver enabled 0 = transmitter disabled 1 = transmitter enabled 0 = sleep mode disabled 1 = sleep mode enabled Transmitter wakeup method select 1 = wakeup mode depends on SCICCR.3 0 = no wakeup modeWrite 0 = Reset SCIWrite 1 = release from Reset 0 = Receive Error Interrupt disabled 1 = Receive Error Interrupt enabledTechnology beyond the Dreams 0x007751] [SCI-B Control Register 1 (SCICTL1) Copyright 2006 Pantech Solutions Pvt 11. 16SCI-A Baud RateBRR = 0,LSPCLK SCI baud rate = (BRR + 1) x 8 BRR = 1 to 65535, LSPCLKBaud-Select MSbyte Register (SCIHBAUD) 0x0070527 65 4 3 2 10 BAUD15BAUD14 BAUD13 BAUD12 BAUD11 BAUD10 BAUD9BAUD8 (MSB)Baud-Select LSbyte Register (SCILBAUD) 0x0070537 65 4 3 2 10BAUD7BAUD6 BAUD5 BAUD4BAUD3BAUD2BAUD1BAUD0 (LSB) [SCI-B Baud-Select MSbyte Register (SCIHBAUD) 0x007752] [SCI-B Baud-Select LSbyte Register (SCILBAUD) 0x007753]Technology beyond the Dreams Copyright 2006 Pantech Solutions Pvt 12. SCI-A Control Register 2 SCICTL2 @ 0x00705415 - 8 7 6 5-210reserved TXreservedRX/BKTXTXRDY EMPTY INT ENAINT ENA SCI RX/BK INT ENA0 = Disable RXRDY/BRKDT interrupt1 = Enable RXRDY/BRKDT interrupt SCI TX EMPTY 0 = TXBUF or shift register are loaded with data 1 = Transmit buffer and shift register both emptySCI TX READYSCI TX INT ENA 0 = SCITXBUF is full 0 = Disable TXRDY interrupt 1 = SCITXBUF is empty 1 = Enable TXRDY interruptTechnology beyond the Dreams 0x007754] [SCI-B Control Register 2(SCICTL2) Copyright 2006 Pantech Solutions Pvt 13. SCI-A Receiver Status Register SCIRXST @ 0x007055 765 4 3210RXRXRDY BRKDTFEOE PE RXWAKEreservedERROR 1 = Receiver wakeup condition detected 1 = Parity Error detected1 = Overrun Error detected 1 = Framing Error detected1 = Break condition occurred0 = no break condition0 = no new character in SCIRXBUF1 = new character in SCIRXBUF 0 = No error flags set 1 = Error flag(s) set [SCI-B Receiver Status Register (SCIRXST) 0x007755]Technology beyond the DreamsCopyright 2006 Pantech Solutions Pvt 14. SCI-A FIFO Transmit Register SCIFFTX @ 0x00705A SCI FIFOTX FIFO Status (read-only) Enhancements00000 TX FIFO empty0 = disable TX FIFO Reset00001TX FIFO has 1 word1 = enable 0 = reset (pointer to 0) 00010 TX FIFO has 2 words 1 = enable operation00011 . TX FIFO.has 3 words.SCI Reset. . . . . . 0 = reset 10000 TX FIFO has 16 words 1 = enable operation15 14 131211 10 98 TXFIFOSCIRSTSCIFFENA TXFFST4 TXFFST3 TXFFST2TXFFST1TXFFST0 RESET765 4 3210TXFFINTTXFFINT TXFFIENA TXFFIL4 TXFFIL3 TXFFIL2TXFFIL1TXFFIL0CLRTX FIFOTX FIFOTX FIFOTX FIFO Interrupt LevelInterruptInterruptInterruptFlag (read-only) Flag Clear (on match) Interrupt when TXFFST4-0 0 = not occurred 0 = no effect Enable and TXFFIL4-0 match 1 = occurred 1 = clear0 = disable 1 = enableTechnology beyond the DreamsCopyright 2006 Pantech Solutions Pvt 15. SCI-A FIFO Receive Register SCIFFRX @ 0x00705B RX FIFO Status (read-only) RX FIFORX FIFO 00000 RX FIFO empty Overflow OverflowRX FIFO Reset00001RX FIFO has 1 word Flag (read-only) Flag Clear0 = reset (pointer to000100)RX FIFO has 2 words0 = no overflow 0 = no effect 1 = enable operation 00011. RX FIFO.has 3 words.1 = overflow1 = clear ... ...10000 RX FIFO has 16 words15 1413 1211109 8RXFF- RXFF- RXFIFO RXFFST4 RXFFST3 RXFFST2 RXFFST1 RXFFST0OVF OVF CLR RESET 76 5 4 3 2 1 0 RXFFINT RXFFINT RXFFIEN RXFFIL4 RXFFIL3 RXFFIL2 RXFFIL1 RXFFIL0 CLRRX FIFO RX FIFORX FIFORX FIFO Interrupt LevelInterrupt InterruptInterruptFlag (read-only)Flag Clear (on match)Interrupt when RXFFST4-0 0 = not occurred 0 = no effectEnableand RXFFIL4-0 match 1 = occurred 1 = clear 0 = disable1 = enableTechnology beyond the Dreams Copyright 2006 Pantech Solutions Pvt 16. SCI-A FIFO Control Register SCIFFCT @ 0x00705C Auto BaudAuto Baud detectiondetectionCDC calibrate A Flag (read-only) Flag Clear 0 = disabled auto-baud alignment0 = not complete 0 = no effect1 = enables auto-baud alignment1 = complete 1 = clear 151413 12 11 10 98 ABDABD CDC reserved CLR 76543210FFTXDLYTime delay between every transfer from FIFOto transmit shift registerin number of SCI baud clock cycles( 0 to 255 )Technology beyond the Dreams Copyright 2006 Pantech Solutions Pvt 17. SCI Example 1: transmit a text - string Lab 8: Basic SCI Communication Send a string from DSP to a PCs COM-port. Connect the RS232 - Connector of the board with a standard DB9 - cable( 1:1 ) to a serial port of the PC (COM1or COM2). DSP shall transmit a string from the DSP to the PC periodically. No SCI interrupt services in this lab After transmission of the first character we just poll the transmission readyflag (TXEMPTY) before loading the next character into the transmit buffer -and wait again. The Windows-Hyper Terminal program is used as the counterpart from thePCs-side and must be initialized properly for correct function(Baud rate,Parity, no protocol).Technology beyond the Dreams Copyright 2006 Pantech Solutions Pvt