Scintillator Hardware Overview

John Kelley24 September 2016Scintillator Workshop

Mainz Meeting

Goals and Scope of M&O Program• Maintain & expand IceTop physics

• Gain operating experience with scintillators at pole

• Testbed for Gen2 components / concepts

• 2017–18 season: deploy up to 10 stations

• 2018–20: TBD, under discussion with NSF

• WBS Level 3: Delia Tosi

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ScintillatoratIceTop Station12

Limits of Gen1 Strategy• Reminder: current scintillators are Gen1-based

– DOM mainboard in the scintillator box– IceTop freeze control cable for power+comms– standard DOMHub + DAQ

• Only 60% of tank comms cables were located in 2015 (~98/162 tanks)

• We have slots on ithub08 for 14 more panels

• Could “borrow” other hubs but space and hardware are tight– also looking into Gen2 mainboards talking to Gen1 hardware

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Components of New Design

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panels+sensor(+readout)

FieldInterfaceBoxfor2to32panels

surfacecabling

ICLhardware+DAQsoftware

Wehavemanygoodideas,butinterfacesaredifferent…Goingtofocusonthecommoncomponentsinthistalk

DAQmicroDAQ

TAXIGen2MB?

panelsAugerKaskadeUW

ICL Components

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GPSantenna

masterclock

WRgrandmaster

hitspool server(s)

• allnewbutoff-theshelf• 7Urackspacetostart• scalabletoGen2

networkswitch

powersupply

FieldInterfaceBoxes

power

…• Fiber+power “spokes”from ICL

(exacttopology stillTBD;upto17“spokes”)

• FIBscanbedaisy-chained;loopback forredundancy

• Shallowtrenchingneeded

fiber

IceCube timestamp

copper,96VDCor208VAC

singlemodeG.652.D

New ICL Hardware (II)

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GPSantenna

masterclock

WRgrandmaster

hitspool server(s)

networkswitch

powersupply

IceCube timestamp

Spectracom SecureSync

TBD,mustberemote-switchable

sameasIceCube

SevenSolutions WRswitch

SevenSolutions WR-ZENorWR-SPEC

WRpartsof thissetuparerunning alreadyatUW(IceCube +HAWC)Cost:~$15k+spares

DAQ Options

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Moredetails:CR-WRcall19Sept.2016

TAXIμDAQ Gen2MB

5VDCetc.

Field Interface Box (microDAQ)

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WR-LEN DC-DC/AC-DCDataInterface

4xUART10MHz+PPS/IRIGI2C

Ethernet

SFP SFP96VDC

RS-485/LVDS

clockfanout

powercontrol

Fanout Board

microDAQ

opticalfiber

Cat610–100m

serialx210MHzx2PPSx2pwr/gnd

microDAQ…~200kbps/panel

upto8panels/serialbus

upto32

• Data interface is under discussion– basically a serial-to-

ethernet box

• Option A– ARM Stamp or

BeagleBone Black embedded Linux module

– provides option for some local DAQ functions (slow control, LC?)

• Option B– serial device server (e.g.

Moxa Nport)– higher power– faster to develop?

10Wpowertarget

Fanout Board• Fanout board is relatively

simple but still requires some work

• Serial transceivers being prototyped for CHIPS @UW

• Timing fanout exists from HAWC, will scale up

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WR-LENfanout (I.Wisher)

Ethernet

Field Interface Box (TAXI)

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5VDCetc.

WR-LEN DC-DC/AC-DC

TAXI 10MHz+PPS/IRIG

SFP SFP

TAXISiPMinterface

opticalfiber

Cat610–100m

analogreadoutx2I2Cpwr/gnd

TAXISiPMinterface…upto?

10Wpowertarget

• TAXI as data interface

• Panel interface– suggest we keep

sensors with panel

– implies new I2C interface

• Timing currently via GPS– WR integration

should be straightforward

WR-LEN

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• WR-LEN is a commercial plug-and-play White Rabbit node – Ethernet + precision timing over

fiber– 10 MHz and PPS+timestring out

• Can be daisy-chained or configured in a star topology– nodes are synchronized to better

than 1 ns (UW lab: 200 ps)

• Current version is not low-temp rated– in contact with vendor, they are

supportive

IceCube Integration• White Rabbit system is separate from IceCube timing

network– use a dedicated node to timestamp IceCube’s PPS signal

• Scintillators supply timestamped ”hits” to a server in ICL– ICL: modified version of pDAQ StringHub hitspooler– new configuration / slow control interface needed

• Proposed multi-step integration– phase 1: hitspool only – phase 2: dedicated trigger + event builder– phase 3: connect to to IC data stream

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Timeline

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Backup

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Fiber Redundancy

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WR-LEN Time String• PPS output can be configured

for IRIG-B instead– ”IRIG-B” has 120 variants– fortunately ours is the simplest

unmodulated version– width-encoded BCD time string

• Prototype IRIG-B firmware decoder written– provides PPS edge +

decoded time string– simulation only so far

• Interface to DAQ– PPS resets a clock counter– time string provides absolute

time info for the previous second

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Gen2 Mainboard+WR-LEN

• Direct link from Gen2 mainboard to WR node– provides ns-scale timing directly to mainboard without

copper + RAPCal– Ethernet interface for comms

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WR-LEN

SMASMA

10MHzIRIG-B

EthernetSPI-to-Ethmodule

oscillator

toclk gen

FPGA

IRIG-Bdecoder

PPS

time fiber