scipp r&d on long shaping-time electronics
DESCRIPTION
SCIPP R&D on Long Shaping-Time Electronics. 4 th SiLC Meeting Barcelona, Spain (by remote connection) December 19 2006 Bruce Schumm. The SCIPP/UCSC ILC HARDWARE GROUP. Faculty/Senior Vitaliy Fadeyev Alex Grillo Bruce Schumm Abe Seiden. Post-Docs Jurgen Kroseberg Lei Wang. Students - PowerPoint PPT PresentationTRANSCRIPT
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SCIPP R&D on Long Shaping-Time Electronics
4th SiLC MeetingBarcelona, Spain (by remote connection)December 19 2006
Bruce Schumm
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Faculty/Senior
Vitaliy FadeyevAlex Grillo
Bruce SchummAbe Seiden
Post-Docs
Jurgen KrosebergLei Wang
Students
Greg HornGabe Saffier-
Ewing
The SCIPP/UCSC ILC HARDWARE GROUP
Lead Engineer: Ned Spencer
Technical Staff: Max Wilder, Forest Martinez-McKinney
(Students are undergraduates from physics and engineering)
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Silicon Microstrip Readout R&D
Initial Motivation
Exploit long shaping time (low noise) and power cycling to:• Remove electronics and cabling from active area (long ladders)• Eliminate need for active cooling
SiD Tracker
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c
The Gossamer Tracker
Ideas:• Low noise readout Long ladders substantially limit electronics readout and support
• Thin inner detector layers
• Exploit duty cycle eliminate need for active cooling
Competitive with gaseous tracking over full range of momentum (also: forward region)
Alternative: shorter ladders, but better point resolution
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Alternative: shorter ladders, but better point resolution
The LSTFE approach would be well suited to use in short-strip applications, and would offer several potential advantages relative to other approaches
• Optimized for LC tracking (less complex)
• More efficient data flow
• No need for buffering
Would require development of2000 channel chip w/ bump bonding (should be solved by KPiX development)
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Pulse Development Simulation
Long Shaping-Time Limit: strip sees signal if and only if hole is collected onto strip (no electrostatic coupling to neighboring strips)
Include: Landau deposition (SSSimSide; Gerry Lynch LBNL), variable geometry, Lorentz angle, carrier diffusion, electronic noise and digitization effects
Christian Flacco & Michael Young (Grads); John Mikelich (Undergrad)
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Result: S/N for 167cm Ladder
Simulation suggests that long-ladder operation is feasible
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1 s shaping time; analog readout it Time-Over-Thres-hold with 400 nsec clock
Process: TSMC 0.25 m CMOS
The LSTFE-2 ASIC
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1/4 mip
1 mip
128 mip
Operating point threshold
Readout threshold
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Electronics SimulationDetector Noise:
From SPICE simulation, normalized to bench tests with GLAST electronicsAnalog Measurement:
Employs time-over-threshold with variable clock speed; lookup table provides conversions back into analog pulse height (as for actual data)
RMS
Gaussian Fit
Detector Resolution (units of 10m)Essential tool for design of front-end ASIC
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FIF
O (L
eadin
g and
trailin
g transition
s)Low Comparator Leading-Edge-Enable Domain
Li
Hi
Hi+4
Hi+1
Hi+2
Hi+3
Hi+5
Hi+6
Li+1
Li+2
Li+3
Li+4
Li+5
Li+6
Proposed LSTFE Back-End Architecture
Clock Period = 400 nsec
EventTime
8:1 Multi-
plexing (clock = 50 ns)
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DIGITAL ARCHITECTURE: FPGADEVELOPMENT
Digital logic should perform basic zero suppression (intrinsic data rate for entire tracker would be approximately 50 GHz), but must retain nearest-neighbor information for accurate centroid.
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DIGITAL ARCHITECTURE VERIFICATION
ModelSim package permits realistic simulation of FPGA code (signal propagation not yet simulated)
Simulate detector background and noise rates for 500 GeV running, as a function of read-out threshold.
Per 128 channel chip ~ 7 kbit per spill 35 kbit/second
For entire long shaping-time tracker ~ 0.5 GHz data rate (x100 data rate suppression)
NominalReadoutThreshold
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Note on LSTFE Digital Architecture
Use of time-over-threshold (vs. analog-to-digital conversion) permits real-time storage of pulse-height information.
No concern about buffering
LSTFE system can operate in arbitrarily high-rate environment; is ideal for (short ladder) forward tracking systems.
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FPGA-based control and data-acquisition system
INITIAL RESULTS
LSTFE chip mounted on readout board
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Note About LSTFE Shaping Time
Original target: shape = 3 sec, with some controlled variability (“ISHAPR”)Appropriate for long (2m) ladders
In actuality, shape ~ 1.5 sec; tests done at 1.2 sec, closer to optimum for SLAC short-ladder approach
Difference between target and actual shaping time understood in terms of simulation (full layout)
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Comparator S Curves
Vary threshold for given input charge
Read out system with FPG-based DAQ
Get
1-erf(threshold)
with 50% point giving response, and width giving noise
Stable behavior toVthresh < 10% of min-i
Qin= 0.5 fC
Qin= 3.0 fCQin= 2.5 fC
Qin= 2.0 fCQin= 1.5 fC
Qin= 1.0 fC
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Noise vs. Capacitance (at shape = 1.2 s)
Measured dependence is roughly(noise in equivalent electrons)
noise = 375 + 8.9*C
with C in pF.
Experience at 0.5 m had suggested that model noise parameters needed to be boosted by 20% or so; these results suggest 0.25 m model parameters are accurate
Noise performance somewhat better than anticipated.
Observed
Expected
1 meter
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Channel-to-Channel Matching
Offset: 10 mV rms
Gain: 150 mV/fC <1% rms
Occupancy threshold of 1.2 fC (1875 e-) 180 mV
± 2 mV (20 e-) from gain variation± 10 mV (100 e-) from offset variation
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Power Cycling
Idea (roughly): Latch operating bias points and isolate chip from outside world.
• Per-channel power consumption reduces from ~1 mW to ~10 W.
• Restoration to operating point should take ~ 1 msec.
Current status:
• Internal leakage (protection diodes + ?)degrades latched operating point
• Restoration takes ~40 msec (x5 power savings)
• Injection of small current (< 1 nA) to counter leakage allows for 1 msec restoration.
• Current focus of bench tests.
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Preamp Response
Power Control
Shaper Response
Power Cycling with Small Injected Current
Need to determine whether leakage problem is fun-damental (to sub-strate) or not (protection diode leakage) to understand if we can design around the leakage. Another (vastly inferior) approach would be to design in an injected current (process/temp variation?
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LONG LADDER CONSTRUCTION
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LONG LADDER EXPERIENCE
LSTFE-2 DESIGN
LSTFE-1 gain rolls off at ~10 mip; are instituting log-amp design (50 mip dynamic range)
Power cycling sol’n that cancels (on-chip) leakage currents
Improved environmental isolation
Additional amplification stage (noise, shaping time, matching
Improved control of return-to-baseline for < 4 mip signals
Multi-channel (64? 128? 256?) w/ 8:1 multiplexing of output
Must still establish pad geometry (sensor choice!)
A current focus of SCIPP activity
With 40cm ladder (50pF load) are seeing ~30% greater noise than expected
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LSTFE SUMMARY
The LSTFE readout system is:
• Universally applicable (long strips, short strips, central, forward, SiD, LDC, GLD)
• Specifically and carfully optimized for ILC tracking
• Relative simple (reliability, yield)
• In a relatively advanced stage of development
• Amplifier/comparator looks functional• Headway being made on fast power cycling• Digital architecture soon available on FPGA
• Hoping to join SiLC testbeam run in late 2007