sdip asic update tensilica day hannover 2018 · cadence genus/modus/innovus backend tool chain....
TRANSCRIPT
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SDIP ASIC UpdateTensilica Day Hannover 2018
Martin Zeller (DCT)
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Dream Chip Technologies GmbH
Dream Chip Technologies 2
DCT Company Profile
Dream Chip Technologies …
• Positioned as a Fabless Microelectronic Engineering Company for medium to large SoC designs covering the whole range from Architecture, Specification, Design, Verification to GDSII
• Technologies: 130nm, 40nm, 28nm, 22nm FDX, 14/16nm FF
• > 70 Employees/ 62 Engineers with 10 … 20 years SoC design experience
• Based in Hanover (HQ) and Hamburg, Germany
• Member of Silicon Saxony/ Germany
Cadence Design Center Partner for Tensilica
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Dream Chip Technologies GmbH
Dream Chip Technologies
Target Applications
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Dream Chip Technologies GmbH
Dream Chip Technologies
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Dream Chip Technologies GmbH
Dream Chip Technologies
MPSoC Chip Architecture
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Dream Chip Technologies GmbH
Dream Chip Technologies 6
DMA DMADMA
DSPTensili
ca
Vision
P6
Low
Level
Pixel
Vector
Proc.
E
T
HAVB
MII
AXI
tp
PVCI
APARM A53
High
Level
Object
Proc.
FlexNOC Network on Chip
AXI128 AXI128
DMA
LMEM
U
S
B
PARMIPI
APB
P
C
I
E
(2x)
SP ARM R5
Host
CTRL
AXI
32
L1$
U
A
R
T
G
P
I
O
TCMB
TCMA
Connection Matrix (SCU.IAC) Module & GPIO Out => CPU Interrupt Inputs
DMAARM
PL330
AXI128
IRQ
ICache
Data
Buffer
I$/D$
CT
RL
-IO
IMEM
DMEM
C
B
O
XDMEM
DMEM
DMEM
TIE
CTRL-IO
S
C
U
.
P
L
L
PVCI
Reg
LPDDR4
Controll
32bit
AXI
128+64
LPDDR4
PHY
S
C
U
.
C
R
G
S
C
U
.
P
M
M AHB
32
Hard-
ware
Engines
HE4
(DEC)
4x AXI
64
DMA
Hardware
Engines
Group 1
(4xISP)
MIPI
PHY
STD
I/O
USB
PHY
PCIe
PHY
STD
I/O
STD
I/O
STD
I/O
AXI
64
AXI
64
AXI
64APB APB
Clock
Int .
GPIO
P P
P P PP P
c
P
PVCI
Other Interrupt
Sources
Internal
Clocks
andEnabling
C
O
R
E
C
O
R
E
C
O
R
E
C
O
R
E
L2 Cache
I$/D$ I$/D$ I$/D$
AXI
64
Hard-
ware
Engines
HE3
(FE)
P
AXI
64
Hard-
ware
Engines
HE2
(MD)
P
I2C
(4x)
STD
I/O
APB
P
S
P
I
S
APB
P
S
P
I
M(6x)
APB
PLPDDR4
Controll
32bit
c
AXI
128+64
LPDDR4
PHY
L1$
TCMB
TCMA
Lockstep
Lockstep
SPARM R5
Host
CTRL
C
A
N
STD
I/O
APB
P
V
D
U
MIPI
PHY
AXI
64
P
DSI
Tx
V
D
U
STD
I/O
AXI
64
P
4xiDMA
AXI128 OCP128
4x
AXI128
I/O IFHEs: Pixel Level
Memory IF
Lock-Step A53: Object Level
VP6: Pixel Level
Low Power CNN Architecture
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Dream Chip Technologies GmbH
Dream Chip Technologies
SDIP ASIC Design Flow
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Dream Chip Technologies GmbH
Dream Chip Technologies 88
Verification Concept
Cadence Incisive Verification Tool Chain
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Dream Chip Technologies GmbH
Dream Chip Technologies 9
SDIP Verification Concept
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• Chip-level and sub-system verification
• UVM SystemVerilog based verification environments
• Verification environment are configurable to select between usage of
– IP “simulation models” or
– IP RTL
• For environments hosting a processor this flexibility allows simulation running real program code or generating “directed” bus transactions.
Cadence Incisive Verification Tool Chain
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Dream Chip Technologies GmbH
Dream Chip Technologies 10
SDIP Verification Concept
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• Sub-system environments available for
– Application processor unit (APU, including ARM A53)
– Safety processor unit (SPU, including ARM Cortex R5 lockstep)
– Digital signal processor unit (DSP, including Xtensa VP6)
– Memory control unit (DDRC, including DDR controller and PHY model)
Cadence Incisive Verification Tool Chain
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Dream Chip Technologies GmbH
Dream Chip Technologies 11
APU Verification Environment (Flavour A)
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APU
apu_ca53_smod(replaces apu_ca53)
APB IF(dbg)
AXI IF(ddr)
AXI IF(acp)
SidebandInterface
SidebandInterfaces
DMA-330 GIG-400
APU_NOC
AXIMaster
UVC
AXISlave UVC
APBSlave UVC
APU Sideband EnvAPU Env
Config : use_smod == true tb_level == chip
SB UVCSB
UVC
APB IF(cfg)
APBSlave UVC
p p p p
p
p
• Environment configured to be used on chip-level using the A53 simulation model
• A53 APB and AXI transfers driven by according UVC sequences
• Remaining sideband port are driven by sideband UVCs
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Dream Chip Technologies GmbH
Dream Chip Technologies 12
APU Verification Environment (Flavour B))
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• Environment configured to be used on subsystem-level using the A53 RTL
• A53 APB and AXI transfers driven C program code
• Remaining sideband port are driven by IP itself
APU
apu_ca53
DMA-330 GIG-400
APU_NOC
AXISlave UVC
APBMaster
UVC
APU Sideband Env APU Env
Config : use_smod == false tb_level == block
AXI IF (ddr)
APB IF (dbg)
apu_tb / sdip_tb
SB UVCSB
UVC
SidebandInterfaces
SidebandInterfaces
AXISlave UVC
AXI IF (acp)
Optional monitor(passive)
AXISlave UVC
AXIMaster
UVC
AXI (mst)
APB (slv) Sidebands
nsp2axi
AXI IF
APBMaster
UVC
APB IF (cfg)
APB (slv)
p p p p
p
pp p
axi2nsp
AXI IF
NSP (mst) NSP (slv)
uvm_testClock & ResetEnv
Clock & Reset Interfaces
p
Virtual Sequencer
System Scoreboard
Reg Model(optinal)
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Dream Chip Technologies GmbH
Dream Chip Technologies 13
SDIP Chip-Level Verification Environment
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LPIO Stream IOCamera IF
APUSPU
VDU
DDRMem
Model
BootFlash(SPIM)
BootFlash
(SPIM)
FlashMem
Model
LPIOEnv
LPIO Interfaces(GPIO, UART, I2C, SPI, JTAG)
Clock & ResetEnv
Clock & Reset Interfaces
Virtual Sequencer
System Scoreboard
Reg Model(optinal)
SDIP_CHIP Env (UVM)
SDIP_CHIP Testbench
SPISUARTGPIO I2C
FlashMem
Model
JTAG
NOC
PLL
uvm_test
A53RTL
APU Env (passive)
A53interfaces
CR5RTL
SPU Env (passive)
CR5interfaces
CR5 SMOD
SPU Env (active)
APU Env (active)
A53 SMOD
CR5 IFs A53 IFs
DDR Env (active)
DDR
DDRRTL
DDR SMOD
DDR IFs
DSP
DSPRTL
DSP Env (passive)
DSPinterfaces
DSP Env (active)
DSP SMOD
DSP IFs
FrameGen
VideoInClock Env
IFs
Eth
Pin Check
SDIP_CHIP
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Dream Chip Technologies GmbH
Dream Chip Technologies 1414
Dft and Backend Cadence Genus/Modus/Innovus Backend Tool Chain
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Dream Chip Technologies GmbH
Dream Chip Technologies 15
SDIP Chip: Layout Overview
• GF 22FDX technology
• PDK v0.5_0.1
• 12 track library
• 7885,3µm x 8001,3µm
• 10LM
• Flipchip
– 1292 bumps
– 405 signal IOs
– 150um/200um pitch
• LVT/SLVT + FBB
• up to 1 GHz
• 0.8V core / 1.8V IO
Cadence Innovus Backend Tool Chain
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Dream Chip Technologies GmbH
Dream Chip Technologies 16
SDIP Chip: Design Info
• ~15.6M Instances
• ~11.6mm² RAM
– 489 insts / 7426 kBytes
– only 9 different RAM cells
• Prepared for FBB
• Timing Optimization
– One SDC only
– 4 setup analysis views
– 9 hold analysis views
DSP4 x IVP6
A53
R5
LPDDR0
LPDDR1
PLL
Cadence Innovus Backend Tool Chain
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Dream Chip Technologies GmbH
Dream Chip Technologies 17
SDIP Chip: Hierarchical Layout with Innovus
sdip_chip
– ARM A53
• 4 x A53 CPU
– ARM R5
– DSP
• 4 x Tensilica VP6
– 2 x 32bit LPDDR4
– 5 x PLL
DSP4 x VP6
A53 Quad4x A53 + L2
R5
LPDDR0
LPDDR1
PLLs
Cadence Innovus Backend Tool Chain
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Dream Chip Technologies GmbH
Dream Chip Technologies 18
Layout Runtime Info
• A53 CPU 12h
• A53 Quad 12h
• VP6 60h
• DSP 30h
• R5 lockstep 17h
• SDIP chip 70h
• total 160h
Cadence Innovus Backend Tool Chain
• 3 x Intel(R) Xeon(R) CPU E5-2643 v2 @ 3.50GHz (12 Cores / 256GB RAM)
• 5 x Intel(R) Core(TM) i7-6700K CPU @ 4.00GHz (8 Cores / 128GB RAM)
• multiple”small” machines
• organized as SunGridEngine
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Dream Chip Technologies GmbH
Dream Chip Technologies 19
Static Timing Analyses
• Hierarchical Approach
– A53 Quad
– DSP
– R5 lockstep
– SDIP chip
• 34 Scenarios
• 6h runtime / 4 DMMC Jobs (8 CPUs each)
Cadence Tempus
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Dream Chip Technologies GmbH
Dream Chip Technologies 20
Layout Verification
• Cadence PVS was not qualified for signoff at TO time
• Hierarchical Approach not possible for sign-off
• high run time
– DRC 72h (3 x 12 CPUs / > 1TB RAM)
– LVS 3h
– FILL 89h (runset not prepared for massive parallel computing)
3rd Party Toolchain
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Dream Chip Technologies GmbH
Dream Chip Technologies
Power Analyses
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Dream Chip Technologies GmbH
Dream Chip Technologies 22
Differential power analysis / Processors
• Heavy computing on one A53 at 500MHz adds +90mW P(core)
• Each additional heavy computing A53 at 500MHz core adds +25mW P(core)
• Heavy computing on VP6 RISC at 500MHz adds +290mW P(core)
• Heavy computing on VP6 SIMD at 500MHz adds +975mW P(core)
• A53/VP6 RISC computing: Mersenne Twister pseudo-random number generator
• VP6 SIMD computing: Vector multiplication
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Dream Chip Technologies GmbH
Dream Chip Technologies 23
Differential power analysis DDR
• One LPDDR at 1066MHz adds +715mW P(total)
• Second LPDDR at 1066MHz adds +300mW P(total)
• Using LPDDR at 1333MHz adds +150mW P(total) per controller
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Dream Chip Technologies GmbH
Dream Chip Technologies 24
Differential power analysis / Demos
• Multiview application runs at +300mW P(total), +190mW P(core)
• Topview application runs at +450mW P(total), +350mW P(core)
• Topview computing consumes 165mW P(core)
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Dream Chip Technologies GmbH
Dream Chip Technologies
SDIP ES 3.0 -> 2018
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Dream Chip Technologies GmbH
Dream Chip Technologies 26
Roadmap / Technology Improvements
• GF 22 nm FDSOI PDK 1.2
– better PPA
– use 8-track libraries
– fix DDR phy weaknesses
• Power Management Optimization
– restrict use of LVDS cells
• Flow
– use new Cadence LBIST flow
– use Cadence PVS for DRC / LVS sign-off
– use hierarchical sign-off and fill flow
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Dream Chip Technologies GmbH
Dream Chip Technologies 27
Roadmap / Features
• Replace two Vision P6 by Vision C5 Processors
• Add USB interface
• Add 2D GPU
• Minor bug fixes / improvements
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Dream Chip Technologies GmbH
Dream Chip Technologies
Demos
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Dream Chip Technologies GmbH
Dream Chip Technologies
Demo (Tensilica Day LUH)
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Dream Chip Technologies GmbH
Dream Chip Technologies
Demo (In Work @ Dreamchip)
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Dream Chip Technologies GmbH
Dream Chip Technologies
Thank You!
martin.zellerdreamchip.de
Dream Chip Technologies GmbHSteinriede 10
D-30827 Garbsen/HannoverGermany
+49-5131-90805-167
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Dream Chip Technologies GmbH
Dream Chip Technologies
MPSoC Chip / Starter Kit
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Dream Chip Technologies GmbH
Dream Chip Technologies
The SIP
System-on-Module features• 4GB LP-DDR4 3200 RAM
Interfaces• Four 300MB/s video inputs• One 300MB/s video output• Gigabit Ethernet
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Dream Chip Technologies GmbH
Dream Chip Technologies
Assembling the SOM...
Overview• Power management and
measurement• Chip power supplies included
Benefits• Reduced application-specific
baseboard complexity• Interfaces customizable to
application requirements
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Dream Chip Technologies GmbH
Dream Chip Technologies 35
4xHDMI Application Board
Overview• DCT ADAS Quad-HDMI Base Board• Four HDMI 1.4b inputs• One HDMI 1.4 output• Custom high-speed headers available
Base board features• Video data rates up to 1080p60• Two Intel MAX10 10M08DC FPGAs• Four high-speed interface headers• Video input synchronization• True output genlock possible
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Dream Chip Technologies GmbH
Dream Chip Technologies 36
Software Development Kit
Overview• DCT ADAS Software
Development Kit• LEDE distribution with stable
Linux 4.4.42• 32-bit and 64-bit flavors available• Tensilica LX7-IVP6 development
support• Kernel API drivers
SDK features• video framework• Tensilica LX7-VP6 support
ARM Cortex-A53Multi-Core User Application
Tensilica LX7-VP6Multi-Core User Application
Linux Kernel
Video4Linux API Mailbox APIKernel Drivers
Secure TrustZone
PSCI API
Video InputInterfaces
Video OutputInterface
CommunicationInterfaces
Debug Access
ARM Cortex-R5Lock-step CPU