s/dms transportnode oc-3/oc-12 ne—tbm

NT7E65DJ 323-1111-192

SONET Transmission Products

S/DMS TransportNodeOC-3/OC-12 NE—TBM

Timing and Synchronization Description

Standard Rel 14 February 2001

What’s inside...

Network synchronizationSynchronization status messagingSetting up timing and synchronization

Copyright

1992–2001 Nortel Networks, All Rights Reserved

The information contained herein is the property of Nortel Networks and is strictly confidential. Except as expressly authorized in writing by Nortel Networks, the holder shall keep all information contained herein confidential, shall disclose it only to its employees with a need to know, and shall protect it, in whole or in part, from disclosure and dissemination to third parties with the same degree of care it uses to protect its own confidential information, but with no less than reasonable care. Except as expressly authorized in writing by Nortel Networks, the holder is granted no rights to use the information contained herein.

Nortel Networks and S/DMS TransportNode are trademarks of Nortel Networks. VT100 is a trademark of Digital Equipment Corporation. UNIX is a trademark of X/Open Company Ltd.

Printed in Canada

iii

ContentsAbout this document vReferences in this document v

Network synchronization 1-1Introduction to network synchronization 1-1

Timing sources 1-1Stratum clocks 1-2Synchronization hierarchy 1-3Building-integrated timing supply (BITS) 1-5

Shelf timing modes 1-6Freerun timing 1-6Loop timing 1-8Throughtiming 1-8Line timing 1-8External timing 1-9Upgrading considerations 1-11

External synchronization interface 1-11ESI clock modes 1-13Audits of ESI clock modes 1-17

Shelf timing features of OC-12 VTM circuit packs 1-17VTM clock modes 1-18Automatic control of the current timing mode 1-19

Timing distribution 1-20System synchronization applications 1-21

Asynchronous point-to-point system 1-22Asynchronous OC-12 diverse route regenerator system 1-22Synchronous linear ADM system with 336-DS1 terminals 1-23Synchronous linear ADM systems with optical tributaries 1-23Synchronous OC-12 linear system as an OC-48 tributary 1-24Timing distribution between point-to-point systems 1-25Synchronous NWK ring system 1-25Synchronous VTM ring system 1-27

Additional information on shelf timing and ESI 1-29

Synchronization status messaging 2-1Introduction to synchronization status messaging 2-1

Requirements to support synchronization status messaging 2-3Defining clock quality levels 2-4

Timing and Synchronization Description 323-1111-192 Rel 14 Standard Feb 2001

iv

Contents

OC-3 tributary synchronization status messaging 2-4Synchronization status messaging for timing distribution 2-5

Synchronization status messaging applications 2-7Applications for various shelf timing modes 2-7DUS for ST3 2-9Pseudo-line timing 2-10

Benefits of synchronization status messaging 2-12Timing synchronization islands 2-13Preventing timing synchronization islands 2-16Timing loops 2-18Preventing timing loops 2-18Hierarchy violation 2-21Preventing hierarchy violations 2-21

Setting up timing and synchronization 3-1Introduction to shelf timing 3-1Network elements that require ESI 3-4

Linear systems 3-4NWK ring systems 3-4VTM ring system 3-4Timing distribution 3-4

Shelf timing parameters 3-4Timing inputs 3-5Timing distribution 3-6

Tools for provisioning shelf timing and ESI 3-7SHELF_CLOCK_CI tool 3-8SYNCMSGCI tool 3-9

Mix mode provisioning 3-9

S/DMS TransportNode OC-3/OC-12 NE—TBM Vol 1 323-1111-192 Rel 14 Standard Feb 2001

v

About this documentThis document describes network synchronization and the functional capabilities of the S/DMS TransportNode OC-3/OC-12 that support synchronization.

AudienceThis document is for the following members of the operating company:

• strategic planners

• current planners

• provisioners

• transmission standards engineers

• network administrators

Although this document is intended primarily for those listed above, it serves as a concise introduction to the equipment and is recommended reading for anyone working with an OC-3/OC-12 network element.

References in this documentThis document refers to the following documents:

• Commissioning Procedures, 323-1111-220

• System Expansion Procedures I, 323-1111-224

• Circuit Pack Descriptions, 323-1111-102

• System Testing Procedures, 323-1111-222

• Protection Switching Procedures 323-1111-311

• Module Replacement Procedures, 323-1111-547

• System Description, 323-1111-100

• Signal Flow and Protection Switching Description, 323-1111-103


vi

About this document


1-1

Network synchronization 1-This chapter introduces network synchronization and the functional capabilities provided by the S/DMS TransportNode OC-3/OC-12 equipment that support synchronization. It provides an introduction to:

• building-integrated timing supply (BITS)

• stratum clocks

• synchronization hierarchy

• synchronization modes within a network element

Introduction to network synchronizationSONET-based equipment derives many of its basic attributes from synchronous operation. Although some networks can operate adequately in an asynchronous manner, synchronization is required in networks that contain add-drop multiplexers (ADM), networks that carry synchronous tributaries, and in certain network configurations, such as rings. These configurations require synchronization of timing among the network elements (NE) to avoid the effects of SONET STS (synchronous transport signal) pointer repositioning within the frame, in signals travelling around the loop. Once a network element is synchronized, all synchronous tributaries and high speed signals generated by the network element are synchronized to its timing source.

Timing sourcesThe OC-3/OC-12 TBM network element can produce timing signals from an internal, freerunning clock. This timing source is adequate for asynchronous operation.

Synchronous operations requires at least one terminal or ADM node to be connected to an external synchronization source, such as a building-integrated timing supply (BITS).


1-2

Network synchronization

To directly access the external timing source, the TBM requires interfacing hardware called the external synchronization interface (ESI). The ESI equipment consists of one or two ESI circuit packs, which are mounted in a standard-sized circuit pack called an ESI carrier. The ESI carrier is installed in one of the common equipment slots of the TBM shelf (slot 23).

The network elements access and process a timing signal that is made available:

• directly by equipping the network element with ESI and connecting the ESI to a BITS

• indirectly from an incoming SONET signal, that is connected to an external clock at an upstream network element

Deriving timing from an incoming SONET signal is called line timing. The OC-3/OC-12 TBM supports line timing with and without ESI equipment, depending on the network element type. At terminal network elements without ESI equipment, deriving timing from an incoming SONET signal is called loop timing. At ADM network elements without ESI, deriving timing from an incoming SONET signal is called primary optics timing.

Stratum clocksThe synchronization of a SONET network is derived from timing sources called stratum clocks.

Stratum clocks are stable timing reference signals that are graded according to their accuracy. American National Standards Institute (ANSI) standards have been developed to define four levels of stratum clocks. These stratum clocks are arranged in a hiearchy in which Stratum 1 is the most accurate clock and Stratum 4 is the least accurate.

The accuracy requirements of these stratum levels are shown in Table 1-1.

Table 1-1ANSI required standard clock strata

Stratum Minimum accuracy Minimum holdover stability

1

2

3

4

+1.0 x 10-11

+1.6 x 10-8

+4.6 parts per million (ppm)

+32 ppm

not applicable

1 x 10-10 per day

+0.37 ppm during first 24 hours

not required



1-3

Synchronization hierarchyA synchronization hierarchy is a network of stratum clocks, containing one stratum level 1 clock and several clocks of lower stratum levels, as shown in Table 1-2. The Stratum 1 clock sends a frequency reference signal to several Stratum 2 clocks. These, in turn, transmit synchronization signals to other Stratum 2 and Stratum 3 entities. Similarly, Stratum 3 clocks synchronize other Stratum 3 and Stratum 4 entities.

Reliable operation is an important consideration for all the parts of a telecommunications network. For this reason, the synchronization network includes primary and secondary (backup) synchronization facilities to each Stratum 2 and 3 node, and to many Stratum 4 nodes. In addition, each Stratum 2 and 3 digital node is equipped with an internal clock that can bridge short synchronization reference disruptions. This operational mode is called Holdover.

Hierarchy violationsA hierarchy violation is created when a clock of one stratum level is used to synchronize a clock of a higher stratum level, for example, if a Stratum 3 clock were synchronizing a Stratum 2 clock. The synchronization network must be carefully planned so that no hierarchy violations are created.

Timing loopsA timing loop is created when a clock is synchronizing itself, either directly or through intermediate equipment. A timing loop causes excessive jitter and might result in loss of traffic.

Timing loops can be caused by a hierarchy violation, or by having peer-level clocks synchronize each other. In a digital network, timing loops can be caused during the failure of a primary reference source, if the secondary reference source is configured to receive timing from a derived transport signal within the network. The provisioning of shelf timing is a local operation, and timing loops must be avoided by examining timing signal flow from a network perspective. In general, timing loops can be avoided, if the same timing reference sources are used for all network elements, or if totally independent reference sources are used.

Synchronization status messaging helps to prevent timing loops. (For information on synchronization status messaging, refer to “Synchronization status messaging” on page 2-1.)


1-4


Table 1-2Hierarchical network synchronization

FW-2173 (OC192)

Stratum 1

Stratum 2

2C2A 2B

Stratum 1

3A 3B 3C

3D

4A 4B 4C

Stratum 3

Stratum 4

Note: Each box represents an office using the building-integrated timing supply (BITS) concept.



1-5

Building-integrated timing supply (BITS)The external synchronization interface feature requires a timing reference signal that ultimately has its origin outside the OC-3/OC-12 system. This means that at least one network element is connected to a timing source such as a BITS.

Although you can use a BITS to time each network element individually, typically there is a network synchronization plan that distributes the timing reference from one network element to others over the OC-12 or OC-3 transport signal. A number of possible synchronization modes exist, to suit the specific network applications. (See “Shelf timing modes” on page 1-6.)

The building-integrated timing supply (BITS) concept stipulates that all digital equipment in a physical structure must receive timing from the same master clock. This master clock is the most accurate and stable clock in the structure.

The BITS is driven by a Stratum 3 or better reference signal. This signal can come from the following sources:

• a timing signal derived from a SONET signal, such as the output of an ESI circuit pack in a TBM shelf

• an external stratum clock

The BITS distributes a DS1 signal, or a composite clock (CC) timing signal at the DS0 rate, to all equipment in the physical location. The S/DMS TransportNode equipment can be used to distribute a BITS signal to other network locations, using ESI.

The implementation of BITS has the following advantages:Performance The designation of a master timing supply for each structure simplifies and enhances the reliability of the timing distribution. The BITS concept minimizes the number of synchronization links entering a building, since each piece of equipment no longer has its own external timing source.

Utilization of resources Since BITS provides a large number of signals for distribution, a single, high-quality reference timing source can be shared among many services within the office.

OperationsThe BITS is location-dependent, not service-dependent. This makes record keeping for provisioning and maintenance purposes considerably easier when new digital services are introduced.

Note: If the timing signal feeding a BITS is derived from a DS1 signal, the DS1 should be derived from a SONET optical carrier signal (such as OC-12), rather than directly from an asynchronous DS1 tributary. The


1-6


short-term stability of DS1 signals carried within the SONET payload is affected by SONET mapping jitter and pointer processing that can be introduced by deriving timing directly from asynchronous tributaries. These signals are therefore not recommended for use in network synchronization. DS1 signals derived from a SONET optical carrier signal do not have this problem.

Shelf timing modesThere are a number of different shelf timing modes that you can apply on a network element basis. (Shelf timing mode is also referred to as network element synchronization mode.)

Freerun timingFreerun timing is shown in Figure 1-1, example (a).

When the TBM clock source is set to Freerun, the system clock generator in the transport interface circuit pack produces shelf timing without external control. This timing is referred to as SONET freerun or Shelf freerun. No ESI equipment is required.

The freerunning clock in the ESI equipment can also drive shelf timing. However, this is not a normal mode of operation. ESI freerun timing takes effect only if the shelf clock source is set to ESI and all timing references become unavailable, or if the ESI is set to freerun using the user interface. The timing references must also remain for a length of time that exceeds the time during which the ESI can provide holdover timing. Important differences exist between the operating characteristics of shelf freerun (provided by the transport interface circuit pack) and ESI freerun. ESI freerun is more accurate than shelf freerun, as shown in Table 1-4 on page 1-19.



1-7

Figure 1-1Flow of synchronization timing signals for various shelf timing modes

FW-2330 (TBM R11)

NE

NE

NE

(b) External timing(Terminal, ADM)

(c) Loop timing(Terminal)

Clock

(a) Freerun timing(Point-to-point terminal)

NE

BITS Stratum-3or better

(e) Primary optics line timing(Linear ADM)

ESI

NE

(d) ESI line timing(Terminal, linear ADM,

ring ADM)

ESI

Regenerator

(g) Throughtiming(Regenerator)

Legend:= Primary Data flow

FW-2330 (TBM R9)

= Synchronization Timing

= External Synchronization Reference

P S

NE

(f) VTM line timing(VTM-based ring ADM)

OC-12 VT MgrWest-to-east

East-to-west


1-8


Loop timingLoop timing is shown in Figure 1-1, example (c).

Loop timing is a method of deriving timing from a received transport signal, without ESI equipment. This method is used in terminal shelves. The timing signal synchronizes the outgoing transport signal in the return direction, and all synchronous tributary signals terminated by the terminal.

ThroughtimingThroughtiming is shown in Figure 1-1, example (g).

Throughtiming is a form of line timing that applies to regenerators. In throughtiming mode, the input optical signal is used to synchronize the output optical signal in the same direction. The synchronization of signals travelling in opposite directions through a regenerator is independent; therefore, a timing source is required for each direction. ESI units are not required.

Line timingESI line timingESI linetiming is shown in Figure 1-1, example (d).

ESI line timing is a method of filtering the timing derived from a received transport signal through ESI. Any of the transport interfaces can be selected as the timing sources (that is, OC-3 or OC-12 G1, G2, G1S or OC-12 G2S). Selection of a transport-derived timing signal as a secondary timing source is permitted.

Primary optics line timing Primary optics line timing is only used in linear ADMs without ESI equipment, as shown in Figure 1-1, example (e).

With this timing method, a linear ADM derives timing from a received transport signal, without filtering by ESI. Only the primary (G1/G2) transport signals are used as the reference signal. The derived signal is used in linear ADM shelves to synchronize outgoing transport signals in both directions, and all synchronous tributary signals terminated by the ADM. The quality of synchronization depends on the stability of the transport signal received from the remote end.

VTM line timing VTM line timing is only used in VTM ADMs without ESI equipment, as shown in Figure 1-1, example (f).

With this timing method, a VTM ring ADM derives timing from a received transport signal, without filtering by ESI. The VTM ADM is equipped with OC-12 VTM circuit packs, and at any given instant, any one of them is



1-9

responsible for shelf timing. In example (f) in Figure 1-1, the OC-12 VTM circuit pack that handles the west-to-east direction of traffic is responsible for timing.

The OC-12 VTM circuit pack derives timing signals from the incoming OC-12 signal. The system clock generator in the circuit pack locks to the derived timing signal. The network element can use the timing signals derived from either the eastbound or westbound OC-12 signal.

If one of the timing signals degrades or becomes unavailable, the network element can automatically switch to the other and, if both timing signals are lost, the OC-12 VTM circuit pack can provide holdover timing that maintains the frequency to within 4.6 ppm for a period of 24 hours. The system clock generator in the OC-12 VTM circuit pack provides the clocks to synchronize outgoing transport signals in both directions, and all synchronous tributary signals terminated by the ring ADM.

Note 1: To improve network performance in the event of failure of the externally timed node, it is recommended that two nodes in the ring be externally timed from BITS. If only one node is externally timed, it is recommended that one other node be ESI line timed.

Note 2: When using line timing in a VTM ring ADM, synchronization status messaging must be used to ensure network robustness.

Note 3: To avoid potential traffic loss, do not equip an ESI carrier (NT7E19) in a shelf on a network element set to operate in VTMLinetimed mode.

External timingExternal timing is shown in Figure 1-1, example (b). External timing uses a timing source independent of any internal clock or received transport signal. The external timing source is a highly accurate stratum clock. If the external source is lost, ESI provides shelf timing internally, for short periods, based on the last received reference (a function called holdover).

Note: When NE Clock Source for the TBM shelf is set to ESI on the Shelf Equipment screen and is externally timed, Target Clock Mode on the OC-12 Equipment screen is set to Normal by default. If Target Clock Mode on the OC-12 Equipment screen shows another setting, such as Freerun or Holdover, you can disregard the setting because it is not being used. The setting may have been made manually if the clock source had been VTMlinetimed or Freerun previously and not changed.

A network element can use external timing if it contains one or more ESI circuit packs, if the ESI circuit packs are connected to an external timing source such as a BITS, and if the shelf timing source is set to “ESI”.


1-10


Table 1-3 summarizes the shelf timing modes supported by the S/DMS TransportNode TBM shelf. The entry for each synchronization mode indicates the following information:

• the applicability of each synchronization mode to network element shelf types

• the type of primary transport interface required in the shelf:

— OC-3 networking interface circuit pack (NT7E01)

— OC-12 networking interface circuit pack (NT7E02)

— OC-12 VTM circuit pack (NT7E05)

• ESI circuit packs required in the shelf

• the timing source

• the value to which the clock source parameter for the shelf must be set

Table 1-3Network element synchronization modes

Shelf timing mode

Applicable shelf function

Primary transport interface

ESI Timing source Clock source setting (see Note)

(a) Freerun timing Terminal, linear ADM, or ring ADM

NT7E02 or NT7E01

no Transport interface internal clock

freerun

(b) External timing Terminal, linear ADM, or ring ADM

NT7E02 or NT7E05 or

NT7E01

yes External clock esi

(c) Loop timing Terminal NT7E02 or NT7E01

no Received primary transport

looptimed

(d) ESI line timing Terminal, linear ADM, or ring ADM

NT7E02 orNT7E05 or NT7E01

yes Received primary and secondary transport

esi

(e) Primary optics line timing

Linear ADM NT7E02 or NT7E01

no Received primary and secondary transport

primaryoptics

(f) VTM line timing Ring ADM (VTM) NT7E05 no Received primary transport

vtmlinetimed

(h) Throughtiming Regenerator NT7E02 no Received signal to be regenerated

throughtimed

The value of the clock source parameter controls the shelf timing mode. For information on how to change the shelf timing mode, see the chapter on provisioning shelf timing and ESI in Commissioning Procedures, 323-1111-220.



1-11

Upgrading considerationsA network element can be upgraded from asynchronous operation to synchronous operation. ESI is installed and the shelf clock source is changed. A small traffic hit might be experienced with this upgrade, depending on the clock phase alignment of the two sources during change-over. For information on upgrading to ESI, see the chapter on adding or removing ESI in System Expansion Procedures I, 323-1111-224.

External synchronization interface The ESI hardware and software in S/DMS TransportNode products allows them to be integrated into the network synchronization timing architecture. This architecture is a timing reference hierarchy that allows all network element timing to reference a common, highly accurate timing source (see Table 1-2, “Hierarchical network synchronization” on page 1-4).

The interface between an external timing source and the shelf timing equipment is provided by the ESI equipment, which consists of an ESI carrier circuit pack and one or two ESI units (depending on whether redundancy is used). The active ESI unit receives the external reference signal and provides an accurate timing source to the shelf.

If the reference signal is interrupted, the ESI enters an operational mode called holdover and continues to provide an accurate timing source for 24 hours following the interruption in the reference signal.

The ESI accepts a bit stream from an external stratum clock (a BITS) or from framing embedded in the incoming transport optics.

The S/DMS TransportNode TBM shelf supports the following external ESI connections:

• two timing reference input facilities, called BITSA and BITSB

Note: It is recommended that two unique BITS sources be used to provide redundancy.

• two timing reference output facilities, called G1OUT and G2OUT

The BITSA and BITSB timing reference input signals are DS1 or Composite Clock signals. When they are DS1 signals, they can have a line code of either AMI or B8ZS, and a frame format of either superframe (SF) or extended superframe (ESF). The signals received from the external stratum clock or BITS are applied to both ESI units. Switching between BITSA and BITSB provides 1+1 reference protection.


1-12


The G1OUT timing reference output signal is generated by the G1 ESI unit. The G2OUT signal is generated by the G2 ESI unit. Each signal is an all-1s DS1 with superframe (SF) or extended superframe (ESF) frame format, with short, medium, or long line build-out (LBO). They provide the external access to TBM shelf timing that supports the timing distribution function.

When the TBM shelf clock source is set to ESI, shelf timing is driven from a signal selected by the active ESI unit from one of four timing references (two external and two internal). This signal can be either of the external reference input signals (BITSA or BITSB), or either of the two internal timing references (OCA or OCB) that are taken from the shelf backplane. The OCA and OCB signals are generated by the transport interface circuit packs and are derived from received SONET frames. Switching between OCA and OCB provides 1+1 reference protection.

ESI unit The NT7E27AA version of the ESI unit supports the detection of hard failures associated with the timing signal (such as loss of signal or loss of frame). Timing deviation detection is supported through the detection of these hard failures.

The NT7E27BA and NT7E27DA versions support enhanced timing deviation detection and recovery. In addition to hard failures, these versions of the ESI detect signal failures resulting from deviations in frequency which render the signal unsuitable as a timing reference. Mixing the NT7E27AA and NT7E27BA (or NT7E27DA) versions of the ESI unit within a shelf is permitted by the software. However, enhanced timing deviation detection and recovery is not supported in such a configuration.

The NT7E27CA and NT7E27EA versions support DS1 ESF synchronization status messaging, as well as all the capabilities of the NT7E27BA and NT7E27DA. Mixing the NT7E27CA and NT7E27EA versions of the ESI unit within a shelf is permitted by the software.The DS1 ESF synchronization status messaging enables:

• network elements that have external timing references, to extract a synchronization status message from the DS1 input signal (that is, BITSA or BITSB)

• network elements that provide timing distribution, to insert a synchronization status message in the DS1 output signal (that is G1OUT or G2OUT)



1-13

Refer to “Synchronization status messaging” on page 2-1 for information on synchronization status messaging.

ESI clock modes When the shelf clock source is set to ESI and the references are configured, the synchronization behavior of a TBM network element is determined by the ESI’s current clock mode. The current clock mode is the current mode of operation of the ESI unit. It depends on the selected ESI target clock mode, the availability of the shelf timing references, and on the status of the ESI unit.

The following target clock modes can be provisioned:

• Freerun

• Normal

• Holdover

The target mode Normal is selected during normal operating conditions and represents the intended clock mode. The ESI Freerun and Holdover modes are used mainly for testing and maintenance purposes, or when the timing reference is changed.

The current clock mode Normal matches the target clock mode. However, the following modes of operation are defined to support initialization and failure states:

• Freerun

• Acquire

• Fast

• Normal

• Holdover

Freerun modeIn this mode, the ESI unit provides a Stratum 3 freerunning clock timing signal (at an accuracy of ±4.6 ppm). The Freerun mode of operation is selected in the following conditions:

• the ESI target clock mode has been set to Freerun

• a valid timing reference has never been present

• all configured reference signals fail while ESI is in the Acquire mode

• a shelf reboot is in progress (OC-48 only)

Note: During a reboot, the ESI is forced into Freerun mode to ensure the quality of the timing reference. This causes a transient Timing Generation Entry to Freerun alarm, which should be ignored.


1-14


The clock contained in the transport interface circuit pack has an accuracy of ±20 ppm for temperatures between -40°C and 65°C. The ESI freerunning clock therefore provides better synchronization performance, even in the Freerun mode, over the timing generated when the shelf clock source is set to Freerun.

Acquire modeIn the ESI versions NT7E27AA/BA/CA, the acquire mode brings the output clock of the ESI unit into frequency alignment with the selected timing reference input. Large changes in frequency are made, until frequency alignment is within a certain range; then the Fast mode is entered.

In the ESI version NT7E27DA/EA , the acquire mode brings the output clock of the ESI unit into frequency alignment with the selected timing reference input; then the Normal mode is entered.

The Acquire mode is entered in the following conditions:

• the ESI target mode is changed from Freerun to Normal

• an ESI unit has just been inserted in the shelf, and target mode is Normal

Fast modeIn ESI versions NT7E27AA/BA/CA, the fast mode makes small changes in frequency to bring its clock into close alignment with the selected timing reference input. The Fast mode is entered in the following conditions:

• after the Acquire mode, when the output clock is close to frequency alignment with the reference signal

• when an interrupted reference signal is restored and the current clock mode is Holdover

• when the current clock mode is Normal and an adjustment to the frequency alignment is required (this could be due to temperature changes that affect the internal clock)

ESI version NT7E27DA/EA does not include the Fast mode. Instead, this version changes from the Acquire mode directly to the Normal mode.

Normal modeWhen the target clock mode has been specified as Normal, and the internal clock of the ESI unit is aligned with the reference signal, the Normal mode is entered. Frequency alignment is checked continuously. On ESI versions NT7E27AA/BA/CA the ESI unit enters the Fast mode to realign, if necessary. On ESI versions NT7E27DA/EA the ESI unit enters the Acquire mode to realign, if necessary.

Holdover modeWhen the current clock mode is Normal and all configured reference inputs are lost, the ESI unit enters the Holdover mode. Alternatively, the target mode can be set to Holdover. In this mode, the ESI output clock is guaranteed to maintain


Network synchronization 1-15

an accuracy of within ±0.37 ppm with the previous reference input for temperatures between 0°C and 50°C for a period of 24 hours, and within ±4.6 ppm of that reference thereafter. The ESI clock is guaranteed to maintain an accuracy of within ±2.0 ppm for temperatures over the range of -40°C and 65°C for a period of 24 hours after entering the Holdover mode. This provides accurate synchronization timing during a total reference signal failure of short duration.

The transitions of the current clock are shown in:

• Figure 1-2 on page 1-15 for ESI versions NT7E27AA/BA/CA

• Figure 1-3 on page 1-16 for ESI versions NT7E27DA/EA

Figure 1-2ESI version NT7E27AA/BA/CA timing mode transitions (target mode = Normal)

FW-2326

Power up Free running

Acquire

Fast

Normal

Allreferences fail

Referenceavailable

Clock alignmenterror greater than

fast criteria

Fast clockalignment

criteria met


normal criteria

Normal clockalignment

criteria met Holdover

All references fail(except for static deviation)

All references fail

At least one reference recovers

Static deviation


1-16 Network synchronization

Figure 1-3ESI version NT7E27DA/EA timing mode transitions (target mode = Normal)

FW-2326 (R13)

Power up Free running

Acquire

Normal

Allreferences fail

Referenceavailable


normal criteria

Normal clockalignment

criteria met Holdover

All references fail(except for static deviation)

At least one reference recovers

Static deviation



Audits of ESI clock modesAn audit is performed by software every 5 minutes to ensure a consistent clock mode operation within the ESI units. This audit corrects the situations such as the following:

• If the shelf clock source is set to ESI before circuit pack initialization (using the Approve command during commissioning), the ESI units continue to operate in Freerun mode until the audit detects the change in clock source.

• After a loss of reference signal, an ESI unit can be left in Holdover mode. The audit detects this difference between operating and provisioned states, and updates the data in the ESI unit.

• After a shelf reboot, the ESI units can reset to states that are different from the provisioned states. The audit aligns the ESI units to their proper state.

The target mode of the ESI circuit pack is one factor that determines shelf timing. For other factors that determine the shelf timing mode, refer to “Setting up timing and synchronization” on page 3-1 in this document, or to the chapter on provisioning shelf timing and ESI in Commissioning Procedures, 323-1111-220.

Shelf timing features of OC-12 VTM circuit packsThe OC-12 VTM circuit packs provide timing features that enable network elements in VTM rings to operate without ESI, provided that there is at least one network element with ESI to derive timing from an external source. (In contrast, all network elements in an NWK ring must be equipped with ESI.)

If a network element contains OC-12 VTM circuit packs in the primary transport slots, then the system clock generator in each of those circuit packs produces system clocks at the following rates: 51.84 MHz, 38.88 MHz, and 2 kHz. The timing reference used as the basis for those clocks depends on whether the network element uses timing provided by ESI equipment or timing provided by the OC-12 VTM circuit pack.

The network element uses ESI timing if the shelf contains one or two ESI circuit packs and the value of the shelf clock source parameter is set to ESI. In this case, the system clock generator in each OC-12 VTM circuit pack receives a stable timing reference frequency of 51.84 MHz from the ESI. That reference provides the basis for the system clocks.

The network element uses OC-12 VTM line timing if the value of the shelf clock source parameter is set to vtmlinetimed. In this case, the system clock generator in each OC-12 VTM circuit pack derives an 8 kHz reference frequency from a received SONET signal. That reference frequency provides the basis for the system clocks.



VTM clock modes OC-12 VTM circuit packs have both a current clock mode and a target clock mode.

Target clock modeThe target clock mode is the mode in which the OC-12 VTM circuit pack tries to operate. For the OC-12 VTM circuit pack, the following target modes of operation can be provisioned:

• Freerun

• Normal

• Holdover

Current clock modeThe current clock mode is the mode that the OC-12 VTM circuit pack is actually in. The current mode normally matches the target mode. However, the following modes of operation are defined to support initialization and failure states:

• Freerun

• Acquire

• Normal

• Holdover

Freerun mode Freerun mode is a target mode that can be provisioned by the user. In Freerun mode, the voltage-controller crystal oscillator (VCXO) clock in the circuit pack is not locked to a timing reference and runs at its natural frequency.

Acquire mode Acquire mode is not a user-provisionable target mode. Acquire mode is the current mode when the VCXO clock in the circuit pack tracks a timing reference. Acquire mode is also the current mode when the timing-mode-maintenance software quickly brings the clock frequency into approximate agreement with the timing reference frequency. That reference is the 8-KHz timing signal derived from an incoming SONET signal.

Normal mode Normal mode is a target mode that can be provisioned by the user. It is the default target mode. When this is the current mode, the VCXO clock in the circuit pack locks to a timing reference. That reference is the 8-KHz timing signal derived from an incoming SONET signal. Normal mode is used during trouble-free operations.



Holdover mode Holdover mode is a target mode that can be provisioned by the user. The circuit pack enters Holdover mode automatically if the target mode is Normal but all timing references are unavailable. If the circuit pack enters Holdover mode automatically, the VCXO clock in the circuit pack holds within a certain frequency range of the last locked-in timing reference. After 24 hours in Holdover timing mode, a log is generated indicating that the circuit pack has been in Holdover for 24 hours. When a timing reference becomes available again, the circuit pack enters Acquire mode.

Table 1-4 summarizes the holdover and freerun shelf timing modes for network elements with ESI equipment, and for VTM network elements without ESI equipment.

Automatic control of the current timing modeIn certain conditions, the current timing mode changes automatically. Each of the following examples assumes that the target timing mode is Normal:

• At start-up, the current timing mode usually goes to Acquire and then to Normal. This is true regardless of whether the network element is set to use ESI timing or OC-12 VTM line timing.

• If the network element is set to use ESI timing, and if all ESI cards on the shelf fail, the current mode goes from ESI Normal to Shelf Freerun.

• If the network element is set to use ESI timing, and if you use a forced switch command or lockout command that causes the network element to use a failed ESI circuit pack that does not provide a valid timing reference signal, the current mode goes from ESI Normal to Shelf Freerun.

Table 1-4Holdover and freerun shelf timing modes

Shelf timing mode

Equipped with ESI

Shelf clock source

Current clock mode

Clock stability

ESI holdover yes ESI holdover ±0.37 ppm over 24 hours (0 to +50°C); ±2.0 ppm over 24 hours (-40 to +65°C)

VTM holdover no VTM line timed holdover ±4.6 ppm over 24 hours (maximum temperature variation of 17°C)

ESI freerun yes ESI freerun ±4.6 ppm (-40 to +65°C)

VTM freerun no VTM line timed freerun ±20 ppm (-40 to +65°C)

Shelf freerun no freerun freerun ±20 ppm (-40 to +65°C)



• If the network element is set to use ESI timing, and if the current timing mode is Holdover, and if a reference is recovered, the current timing mode goes to Acquire and then to Normal.

• If the network element is set to use OC-12 VTM timing, and if all available timing references are invalid, then it goes to Holdover if the current timing mode is Normal, and it goes to Freerun if the current timing mode is Acquire. (A timing reference can become invalid for a variety of reasons which are listed in the next section.)

• If the network element is set to use OC-12 VTM timing, and if the current timing mode is Holdover or Freerun, the current timing mode goes to Acquire and then to Normal if a valid timing reference becomes available.

Invalid timing referencesIf a network element is set to use OC-12 VTM timing, the shelf clock source is set to vtmlinetimed. The OC-12 VTM circuit packs must derive 8-kHz timing references from the received SONET signals. This type of timing reference becomes invalid if any of the following occurs:

• problems with the SONET signal

— loss of signal (LOS)

— loss of frame (LOF)

— line alarm indication signal (line AIS)

— synchronization status message is set to DUS (Do not use for synchronization)

• problems with the OC-12 VTM circuit pack that receives the SONET signal

— hardware failure

— circuit pack placed out of service (OOS)

If an OC-12 VTM circuit pack is in Holdover or Freerun mode, it inserts the code “1100” (SMC) into the S1 byte in the SONET line overhead. This synchronization status message is for the next network element in the system. The message indicates that the quality of the line timing is SONET minimum clock. For more information on synchronization status messages, see the next section.

Timing distribution Timing distribution is the process of making a single timing reference signal available to a large number of systems within many physical locations. The ESI equipment in the S/DMS TransportNode TBM shelf provides external access to synchronization timing signals derived from accurate sources (BITS or SONET). As a result, the S/DMS TransportNode system is capable of distributing a timing source from one physical location to another. This timing distribution is illustrated in Figure 1-4.



Figure 1-4Timing distribution in a point-to-point system

FW-2539

System synchronization applicationsThe selection of a timing mode in an S/DMS TransportNode TBM shelf depends on the configuration of the shelf within the network. Various combinations of shelf timing modes are possible to ensure proper synchronization of the network. The following configurations are considered in this section:

• asynchronous point-to-point system

• asynchronous OC-12 diverse route regenerator system

• synchronous linear ADM system with 336 DS1 terminals

• synchronous linear ADM system with optical tributaries

• synchronous OC-12 linear system as an OC-48 tributary

• timing distribution between point-to-point systems

• synchronous NWK ring systems

• synchronous VTM ring systems

Note: This section shows applications without synchronization status messaging. For applications that use synchronization status messaging, refer to “Synchronization status messaging” on page 2-1.

FW-2539

BITSproviding

timingto TBM

Building A

ESI NE ESI

OC-3/OC-12 Terminal(external timing)

BITStiming

providedby TBM

Building B

OC-3/OC-12 Terminal(line timing)



Asynchronous point-to-point systemIn an asynchronous OC-3/OC-12 point-to-point system, as shown in Figure 1-5, the clock source in one of the terminal network elements is set to freerun timing. The clock source in the other terminal network element is set to loop timing. ESI units are not required.

Figure 1-5Timing scheme in an asynchronous point-to-point system

FW-2537

Asynchronous OC-12 diverse route regenerator systemIn an asynchronous OC-12 diverse route regenerator system, as shown in Figure 1-6, the clock source in one of the terminal network elements is set to freerun timing. The clock source in the other terminal network element is set to loop timing. The OC-12 regenerator shelves are throughtimed for all applications and cannot be modified. ESI units are not required.

Note: A maximum of four regenerators can be equipped on a fiber span between two terminal network elements.

Legend:= Primary Data flow= Synchronization Timing FW-2537

Loop timing

Clock

Freerun timing

OC-3/OC-12 Terminal OC-3/OC-12 Terminal



Figure 1-6Timing scheme in an asynchronous OC-12 diverse route regenerator system

FW-2981

Synchronous linear ADM system with 336-DS1 terminalsFigure 1-7 illustrates one possible combination of shelf timing selections for a linear system that includes two 168-DS1 TBM shelves. Typically, the two TBM shelves required to implement the 336 DS1 terminal are located in the same bay, with timing provided from the ADM shelf to the OC-12 terminal shelf.

Figure 1-7Timing scheme in a linear system

FW-2581

Synchronous linear ADM systems with optical tributariesFigure 1-8 illustrates a linear system containing ADMs and optical tributaries. The somewhat atypical location of the BITS demonstrates the various shelf timing selections that might be required in this type of system.

Legend:= Primary Data flow= Synchronization Timing FW-2981

Loop timing

Clock

Freerun timing

OC-12 Terminal OC-12 TerminalRegenerator

Throughtiming

Legend:= Transport Data flow= Synchronization Timing

FW-2581

Looptiming

OC-12 Terminal OC-12 Terminal

Looptiming

336 DS1 Terminal

BITS

ESI

Linear ADM

Externaltiming

Linear ADM

Line timing

Linear ADMExternaltiming

BITS

ESI

336 DS1 Terminal

ESI

Linear ADMLine

timing

ESI




FW-2538 R7

Synchronous OC-12 linear system as an OC-48 tributaryFigure 1-9 illustrates one possible combination of shelf timing selections for OC-12 network elements that serve as tributaries of an OC-48 system. Timing for the OC-12 network elements can be derived from transport signals received from the OC-48 or from an external source.


FW-2580

Legend:= Primary Data flow= Synchronization Timing FW-2538 (R7)

Looptiming

OC-3 Terminal

BITS

ESI

OC-12 Terminal

Externaltiming

ESI

Linear ADMLine

timing

BITS

ESI

Linear ADM

Externaltiming

ESI

OC-12 TerminalLine

timing

BITS

OC-3 Terminal

Externaltiming

ESI

Legend:= Transport Data flow= Synchronization Timing FW-2580

Looptiming

OC-12 Terminal

BITS

ESI

Linear ADM

Externaltiming

ESI

Linear ADMLine

timing

ESI

Linear ADMLine

timing

OC-12 Terminal

Looptiming

OC-48Terminal

OC-48Terminal

336 DS1 Terminal



Timing distribution between point-to-point systemsA TBM network element can use ESI to distribute timing to another system (but not to itself), even though it is operating in loop timed mode. Figure 1-10 shows an example of this configuration, where the terminal network elements of two separate point-to-point systems are located in the same building. The two systems do not necessarily share a transport interface.

Figure 1-10Timing distribution between point-to-point systems

FW-2623

Synchronous NWK ring systemThe NWK ring system can be synchronized using an external timing reference at each ring ADM node. Alternatively, such a system can be synchronized using an external timing reference at some nodes and line timing at the others. Both arrangements are illustrated in Figure 1-11. In an NWK ring, every ring ADM must contain ESI equipment (one or two ESI circuit packs), because the timing signals are filtered through ESI at every node. In the application illustrated in the lower part of Figure 1-11, node C can be provisioned to receive timing from either node B or D.

Legend:= Primary data flow= Synchronization Timing

FW-2623

Externaltiming

OC-12 Terminal OC-12 TerminalLooptiming

OC-12 TerminalExternaltiming

OC-12 TerminalLine

timing

Building

BITS

ESI ESIESI



Figure 1-11Timing schemes in NWK rings

FW-2246 (TBM)

FW-2246.1 (TBM)

B

D

A C

BITSTimingreference

BITSBITS

BITSTimingreference

Timingreference

Timingreference

ESI

G1G1S

ESI

G1S

G1

ESI

G1

G1S

ESI

G1SG1

B

D

A CBITS

Timingreference

ESI

G1G1S

ESI

G1S

G1

ESI

G1

G1S

ESI

G1SG1

(a) Ring Synchronization with BITS at all nodes (preferred)

(b) Ring Synchronization with BITS on one node only

Line timing fromsecondary transport G1S

Line timing fromprimary transport G1

Line timingfrom secondarytransport G1S



Synchronous VTM ring systemThe VTM ring system can be synchronized using an external timing reference at one node. The other nodes are VTM line timed using the capabilities of the OC-12 VTM circuit packs [see Figure 1-12 (a)]. Another example: a VTM ring system can be synchronized using an external timing reference at two of the nodes and VTM line timing at the others [see Figure 1-12 (b)]. A VTM ring ADM needs ESI equipment (one or two ESI circuit packs) only if:

• it receives an external timing reference, or

• it distributes timing to other equipment through the DS1 interface of the ESI circuit pack.

The VTM line timed network elements do not need ESI circuit packs because the OC-12 VTM circuit packs handle timing and synchronization. Each VTM line timed network element can receive timing from either direction. In the application illustrated in the lower part of Figure 1-12, node C can be provisioned to receive timing from either node B or D.

Note: To improve network performance in the event of failure of the externally timed node, it is recommended that two nodes in the ring be externally timed from BITS. If only one node is externally timed, it is recommended that one other node be ESI line timed.

When the VTM ring system is in operation, each ring ADM can perform automatic protection switching from one timing source to another. If such protection switching is required (for example, if the active timing source becomes unavailable) the network element switches to the highest-quality timing source available. The network element knows the quality of each available source of line timing because the OC-12 VTM circuit packs can read synchronization status messages. These messages, coded in the SONET line overhead, indicate the timing quality of the incoming OC-12 signal. For more information, refer to “Synchronization status messaging”.



Figure 1-12Timing schemes in VTM rings

FW-2246 (TBM R11)

A

C

B DBITS

Timingreference

G1

G2G1 G1G2

G2

G1

G2

ESI

(a) Synchronization of a VTM ring with ESI at one node only

A

C

B DBITS

Timingreference

G1

G2G1 G1G2

G2

G1

G2

ESI

(b) Synchronization of a VTM ring with ESI at two nodes

ESI BITS

Timingreference



Additional information on shelf timing and ESI• Information about the ESI hardware is provided in Circuit Pack

Descriptions, 323-1111-102.

• Information about shelf timing signal flow and protection switching is provided in Signal Flow and Protection Switching Description, 323-1111-103

• ESI installation procedures are provided in System Expansion Procedures I, 323-1111-224.

• Procedures to provision ESI and shelf timing are provided in Commissioning Procedures, 323-1111-220.

• Procedures to test Shelf timing and ESI are provided in System Testing Procedures, 323-1111-222.

• Timing reference and ESI protection switching information are provided in Protection Switching Procedures 323-1111-311.

• Troubleshooting procedures that relate to alarms associated with ESI are provided in Alarm and Trouble Clearing Procedures, 323-1111-543.

• Procedures for ESI carrier and circuit pack replacement are provided in Module Replacement Procedures, 323-1111-547.


2-1

Synchronization status messaging 2-This chapter introduces synchronization status messaging and the functional capabilities of the OC-3/OC-12 equipment to support synchronization status messaging. It describes:

• S1 byte and DS1 ESF synchronization status messaging

• system configurations that support synchronizations status messaging

• applications of synchronization status messaging

This chapter also provides examples that demonstrate how synchronization status messaging helps to prevent timing islands, timing loops and hiearchy violations.

To upgrade to synchronization status messaging, or to upgrade a system with S1 byte synchronization status messaging to also use DS1 ESF synchronization status messaging, refer to System Expansion Procedures I, 323-1111-224.

Introduction to synchronization status messagingSynchronization status messaging allows SONET network elements and BITS systems to communicate information about the quality of their timing references. These messages allow a SONET network to automatically ensure that the best quality source available is used if a failure or degradation in the timing signal occurs. Synchronization status messaging reduces the potential for timing loops and gives transport networks added robustness.

The synchronization status messages contain clock quality information, allowing SONET network elements to select the best quality timing reference from the set of available references.

Synchronization status messages are defined for both SONET and BITS. The S1 byte in the SONET line overhead carries synchronization messages between network elements. (For more information on SONET overhead, see System Description, 323-1111-100.) The extended superframe (ESF) format data link of DS1 signals carries synchronization messages:

• from the BITS to the ESI at externally timed network elements


2-2 Synchronization status messaging

• from the ESI to the BITS, at network elements that provide timing distribution

With synchronization status messaging, the network element

• monitors the quality level of the available timing reference signals

• selects the timing reference with the highest clock quality level

• performs an automatic timing reference switch, if necessary, when the available timing references or their clock quality levels change

The quality levels carried by synchronization status messages are shown in Table 2-1. Stratum 1 is traceable to the primary reference source (PRS). There is a non-standard clock quality level known as ST3E, that is not shown in Table 2-1. Although ST3E has a greater accuracy than ST3, it is represented in synchronization status messages as having a clock quality level ST3.

Table 2-1Synchronization status messages

Description Acronym Quality level SONET S1 bits (bit 5 to bit 8)

ESF Data Link Code byte

Stratum 1traceable to the primary reference source

ST1 1 0001 00000100

Traceability unknown STU 2 0000 00001000

Traceable Stratum 2 ST2 3 0111 00001100

Traceable Stratum 3 ST3 4 1010 00010000

SONET minimum clock (±20 ppm)

SMC 5 1100 00100010

Traceable Stratum 4 ST4 6 00101000

Do not use for synchronization DUS 7 1111 00110000

Reserved for network synchronization use

RES(see Note 2)

User assignable

1110 01000000

Note 1: When a system equipped with ESI receives an SMC signal, the user interface displays DUS since the internal synchronization quality level of the ESI is 4 (Stratum 3).

Note 2: RES is not provisonable. It is interpreted as a valid SSM with a value between ST3 and SMC in the hierarchy.


Synchronization status messaging 2-3

As the timing is passed from one network element to the next, each network element sends synchronization status messages. If the quality of the timing reference changes, the synchronization status messages inform the next network element of the change. In normal circumstances, a network element that receives timing from the transport signal of an adjacent network element,

• sends a do not use for synchronization (DUS) message back towards the link which is supplying timing,

• sends the received quality level to the network element downstream in the timing flow

The return of a DUS signal prevents the network element that provides the timing from timing itself (causing a timing loop). The flow of synchronization status messages for various line timed network elements is described in “Synchronization status messaging applications” on page 2-7.

Requirements to support synchronization status messagingOC-12 linear systems and NWK rings support synchronization status messaging as long as all network elements have ESI equipment. VTM rings support synchronization status messaging if ADMs have ESI equipment or are VTM line timed.

Network elements with ESI versions NT7E2CA/EA support synchronization status messaging between ESI and BITS in the extended superframe (ESF) format of the DS1 signal. For the ESI to receive DS1 ESF synchronization status messages from a BITS source, the external source that feeds into the BITS must use ESF framing format and carry synchronization status messages.

Table 2-2 summarizes the availability of synchronization status messaging in OC-3/OC-12 TBM systems.



Defining clock quality levelsSynchronization status messages can be read from the S1 byte of the SONET overhead (for Transport signals) or from the ESF format of the DS1 data link (for signals to or from BITS). To allow synchronization messages to be read automatically, you must provision the quality level for the timing reference as “auto”

You can also provision specific quality levels. To manually provision the quality level, you assign a quality level to the timing reference. When you specify a quality level for a timing source, the user interface appends “-P” to the quality level, for example, ST1-P. Manual provisioning of timing references is useful when you have an externally timed network element that supports S1 byte synchronization status messaging, but does not support DS1 ESF synchronization status messaging.

OC-3 tributary synchronization status messagingOC-3 tributary synchronization status messaging (SSM) allows synchronization status messages to be transmitted to sub-tending OC-3 NEs. To use the SSMs, the sub-tending OC-3 NE must support SSM. Any provisioned SSM quality level overrides on the receiving OC-3 optics must be removed.

This feature provides the following additional capabilities:

• transmits synchronization status messages (SSM) to the OC-3 tributaries

• the transmitted SSM is equal to the quality level of the active timing reference level, which is either the provisioned quality level, or if there is no quality level provisioned, the actual received quality level

Table 2-2Availability of synchronization status messaging in OC-3/OC-12 TBM systems

System type S1 byte synchronization status messaging between network elements

DS1 ESF synchronization status messaging between ESI and BITS

OC-3 linear not supported not supported

OC-12 linear supported only if equipped with ESI at all ADM network elements

supported at network elements with ESI version NT7E27CA/EA

NWK ring supported only if equipped with ESI at all network elements


VTM ring supported if ESI equipped at one or more network elements


Note: Synchronization status messaging is not supported on OC-3 NEs, primary optics timed NEs, and loop timed NEs. On ESI line timed OC-3 NEs, the clock quality level must therefore be provisioned as STU. TBM OC-3 NEs, line timed NEs and primary optics timed NEs transmit SMC to downstream NEs.



• when the NE enters holdover or freerun, the SSM is equal to the holdover or freerun quality level of the NE

• on NEs which support SSM, the SSM is automatically transmitted on all provisioned OC-3 tributaries that are in-service and transmit-active

• synchronization status messages transmitted on OC-3 tributaries can be viewed using the qrymsg command within the SYNCMSGCI tool (see Commissioning Procedures, 323-1111-220). The qrymsg command displays the quality level transmitted on OC-3 tributaries. It also displays the quality levels received on the OC-3 tributaries. Although the received OC-3 quality levels can be viewed, the received OC-3 tributary signal cannot be used as a timing reference for the OC-12 NE.

During a protection switch at an OC-3 tributary pair, in which the receiving OC-3 optics at the sub-tending node are both provisioned as timing references, the sub-tending node will go into holdover momentarily. There are no adverse effects on the system.

Note: If you use synchronization status messaging to time a protected pair of OC-3 optics interfaces at a subtending network element (for example, OPTera Metro 3000) by way of a protected pair of OC-3 tributaries on an OC-12 TBM network element, both of the OC-3 optics interfaces on the subtending network element must be provisioned as timing references.

Synchronization status messaging for timing distributionYou can use one of two methods to alert a BITS to a degradation in the clock quality level of the distributed timing signal:

• message pass-through mode

• alarm indication signal (AIS) generation mode

Message pass-through modeThe message pass-through mode requires the system to support DS1 ESF synchronization status messaging. In this mode, the BITS directly receives the clock quality level of the timing distribution signal.

AlS generation In the AIS generation mode, if the synchronization status message used for timing distribution is of equal or poorer quality than the user provisioned threshold value, the ESI DS1 output sends DS1 AIS. AIS generation is useful at network elements that support S1 byte synchronization status messaging, but do not support DS1 ESF synchronization status messaging.

You can use the ESI facility screen to provision the threshold AIS. If you set the AIS parameter to NULL, the ESI uses the message pass-through mode. If you set the threshold to a specific quality level, and the quality level of the timing reference source is equal to or poorer than the threshold, the ESI sends



an AIS to the BITS.Since BITS clocks recognize AIS as an unacceptable reference, the generation of AIS ensures that the BITS does not take synchronization from an optics source that has been rejected.

Figure 2-1 on page 2-6 shows an example of Threshold AIS generation. In this example, the derived DS1 of NE 1 is synchronized from the fiber from NE 4, and the Threshold AIS value at NE 1 is provisioned to Stratum 3. Timing on NE 4 is extracted from an external BITS clock. When the quality level of the timing received from the fiber (indicated by the synchronization status message byte S1 in the SONET overhead) is at or below the provisioned threshold AIS value (Stratum 3), NE 1 inserts AIS on the derived DS1 and raises the “Tx AIS” alarm.

Figure 2-1Example of Threshold AIS generation

FW-2246 (TBMR11.2)

BITS

Threshold AIS=ST3

DS1

S1=ST1

ST1

ST1

ST1

2 4

3

1

BITS

Threshold AIS=ST3

DS1AIS

S1=ST3

ST3

ST3

2 4

3

1



Synchronization status messaging applicationsThis section provides examples of applications of synchronization status messaging for various shelf timing modes. It also describes DUS for ST3 and pseudo-line timing.

Applications for various shelf timing modesFigure 2-2 on page 2-8 illustrates applications of the message set with different shelf timing modes. Each scenario shows the relationship between the timing mode, timing references and the selected timing reference quality level. The illustrations show cases when synchronization status messages are available, as well as when they are not available. The value “n” in the figure corresponds with the quality levels shown in Table 2-1.

Figure 2-2 (a) shows an externally timed network element, that uses DS1 ESF and S1 byte synchronization status messaging.

Figure 2-2 (b) shows an externally timed network element, that does not receive synchronization status messages from the BITS. In this case, the message STU (stratum traceability is unknown) is sent. STU is the quality level that the ESI assigns to the BITS source if there is no synchronization status messaging, and no provisioned clock quality level.

Figure 2-2 (c) shows a line timed network element that carries synchronization status messages. Note that the clock quality level is sent in the same direction as the received signal, while a DUS is sent in the return direction.

Figure 2-2 (d) shows a loop timed terminal. In this case, the network element receives the synchronization status message, and returns a DUS in the opposite direction.

Figure 2-2 (e) shows a line timed network element without synchronization status messages. In this case, the network element still returns a DUS in the opposite direction. The quality level of the optics is treated as STU.

Figure 2-2 (f) shows a network element with the shelf timing mode, freerun. Since shelf freerun has a quality level of SONET minimum clock (SMC), the quality level 5 is sent in both directions.

Figure 2-2 (g) shows a regenerator. The shelf timing mode for regenerators is always through timed. The synchronization status message is passed through the regenerator as shown.

Figure 2-2 (h) shows a network element in ESI Freerun or holdover. ESI Freerun or ESI Holdover has an internal clock of Stratum 3 quality. Therefore the quality level 4 is sent in both directions.



Figure 2-2Synchronization status messaging applications

FW-2330 (TBM R11.2)

NE

NE

(d) Loop timed

NE

(e) Line timed

NE

(c) Line timed

(a) Externally-timed(Messaging BITS)

(f) SONET minimum clock

(g) Through-timed

Legend:= Primary Data flow

= Tributary Data flow

FW-2330 (TBM R11.2)

= Synchronization Timing

= External Synchronization Reference

BITS

(Messaging available)n=1,3,4 sync. message n

BITS

(No sync. messaging)

n=2 Traceability unknown



n=5SONET clock

n=5SONET clock

No sync. message

No sync. message

n=7 Don't use for sync.

n=1,3,4

n=1,3,4 sync. message n

n=1-5 Sync.message n

n=1-5 Sync. message n

n=7 Don'tuse for sync


n=7 Don'tuse for sync


n=1-7 Sync. message m

n=1-7 Sync. message m


NE NE

NE

(b) Externally timed(Non-messaging BITS)

NE

n=4

n=4

ESI Freerun/holdoverh)

ESI



DUS for ST3You can use an additional option, called DUS for ST3, to customize the selection of timing references at an externally timed network element. You access the DUS for ST3 command from the synchronization messaging command interpreter tool, SYNCMSGCI.

By default, whenever an ESI enters a non-normal clock mode (such as holdover), the NE sends an ST3 quality level as its synchronization message. The DUS for ST3 option enables you to change this default. You can provision the ESI to send DUS (do not use for synchronization) instead of ST3 when the ESI enters a non-normal clock mode.

You can benefit from this option when you have a downstream network element with the clock quality level ST3E. ST3E is a non-standard clock quality level, that has a greater accuracy than ST3. In synchronization status messaging, you can have an ST3E timing reference that uses the ST3 quality level message.

Figures 2-3 and 2-4 illustrate the application of DUS for ST3. In Figure 2-3, ADM 1 has lost its external timing from the BITS, and enters ESI holdover. Since ESI holdover has a quality level of ST3, ADM 2 and ADM 3 are synchronized to the ST3 quality level.

In Figure 2-4 DUS for ST3 has been provisioned. Therefore, when the external timing from the BITS is lost and ESI enters holdover, ADM 1 sends do not use for synchronization (DUS) instead of ST3. As a result, ADM 3 derives its timing from its ST3E BITS source. ADM 2 and ADM 1 are then synchronized to the ST3E quality level.

Figure 2-3ST3 on ESI holdover

FW-5066(TBM)

ADM 1(ESI ST3holdover)

ST1BITS

ADM 2 ADM 3

DUSDUS

ST3 ST3



Figure 2-4Application of DUS for ST3

FW-5066(TBM)

Pseudo-line timing As shown in Figure 2-5, a network element can receive timing from a BITS which is timed from that same network element. A TBM network element cannot use ESI to distribute timing to itself. However, such a configuration might result when the BITS is timed from a number of network elements, with the intent that the best of the available timing references from those network elements is used by the BITS in the event the BITS enters holdover.

The network element compares the message on its DS1 input (received from the BITS) with its DS1 output. If the same quality level is detected at both its input and output, the network element suspects a timing loop. With DS1 ESF synchronization status messaging, if an OC-12 interface is the source of a DS1 output and the received quality message on that transport circuit pack group matches the received quality of the active BITS, a DUS message is transmitted on that circuit pack group.

To avoid this condition, both G1OUT and G2OUT can be placed out of service or place either G1OUT or G2OUT out of service according to which one has the same message as the message on the BITS.

ADM 1(ESI ST3holdover)

ST1BITS

ADM 2

DUSDUS

ST3E ST3E

ST3EBITS

Note: ST3E BITS are used rather than lock to ESIholdover from ADM 1.

ADM 3



Figure 2-5Externally timed network element distributing a timing signal to its own BITS source

FW-3463

Transmission of the DUS message provides the same protection from timing loops for pseudo-line timed systems as for line timed systems. In Figure 2-5, the G2 optic drives G2OUT, and its quality level matches that of the BITS source. Because the network element cannot know the cause of this condition (for example the same condition would occur it the DS1 output loops to the DS1 input), the network element transmits DUS on the G2 optics.

Figure 2-6 shows how the requirement forces the same synchronization status messages to be sent for true line timed network elements and pseudo-line timed network elements.

BITSST2

ST2

ST1

ST1

ST1

BITSA BITSB

G1 OUT G2 OUT

ST1

ST2

ST1

DUS

ST1

Legend:

DUS = Do not use for synchronizationST1 = Traceable Stratum 1ST2 = Traceable Stratum 2

G1 optics G2 optics



Figure 2-6Line timed and pseudo-line timed network elements

FW-3464 (R14)

Benefits of synchronization status messaging Synchronization status messaging gives Transport Networks added robustness. Synchronization status messages are especially needed in ring configurations in which reference timing is carried in the SONET signal.

When a fault occurs and the traffic path is reconfigured, the timing-reference source used by one or more of the network elements may become unavailable. Any network element that loses its timing source automatically switches to the highest quality alternative source available. In such a situation, the synchronization status messages provide information about the quality of available sources.

Figure 2-7 on page 2-14 illustrates an example of timing recovery following a failure in the ring. The figure shows the normal operation whereby the six network element ring has two network elements externally timed from a BITS source, with the remaining network elements line timed from the fiber.

Figure 2-7 also shows the system response to a link failure between two line-timed network elements. The affected network element (shaded in the diagram) switches to the alternate ST1 reference. After the switch completes,

G1 OUT = OCA G2 OUT = OCB

BITS BST1ST2

BITS A

ST2

ST1

DUS

ST1

G1 G2

ST2

ST1

DUS

ST1

Legend:

DUS = Do not use for synchronizationST1 = Traceable Stratum 1ST2 = Traceable Stratum 2 = Same operation as the line timed NE

Pseudo-line line timed

Line timed (Note)

Note: G2OUT must be ST1 forpseudo-line timing to work.



the network element updates the S1 byte synchronization messages to send a “DUS” indication back towards the link which is supplying timing, and “ST1” to the network element downstream in the timing flow.

Synchronization Status messaging can be used to prevent the formation of timing islands and timing loops, and to prevent synchronization hierarchy violation. The following sections provide detailed descriptions and examples that illustrate the benefits of using synchronization status messaging.

It is important to realize that a network in which timing has been improperly engineered cannot be rectified by synchronization status messaging alone. However, within a network where solid engineering rules have been followed for timing, synchronization status messaging will ensure the network is timed to the best possible reference at any time. For guidelines on mix mode provisioning, see “Mix mode provisioning” on page 3-9.

Timing synchronization islandsThe loss of a fiber link can result in the creation of a timing island, isolating the timing island from the rest of the network. Figure 2-8 on page 2-16 illustrates the creation of a small synchronization island when a failure to the optical signal timing for NE 5 occurs. The effect of synchronization failure on traffic is summarized in Table 2-3 on page 2-15.

Synchronization status messaging can be used to prevent synchronization timing islands.



Figure 2-7S1 byte synchronization status messaging in SONET ring

FW-3484

= Timing flow Note:

Event: Fiber cut

Actions: NE switches to alternate ST1 reference NE sends ST1 message to downstream node NE sends "Don't Use for Sync" to upstream node

Legend:

PRS

PRS

(a) Normal Operation

NE 6

NE 1

NE 2

NE 3

NE 4

NE 5

ST1

ST1

ST1

ST1

ST1

ST1

ST1

ST1DUS

DUS

DUS

DUS

PRS

PRS

(b) Link failure and recovery

NE 6

NE 1

NE 2

NE 3

NE 4

Fiber cut

NE 5

DUS

ST1



Table 2-3Synchronization failure impact on traffic

Traffic Impact

Traffic originating and terminating within the degraded sync island

All cases No Impact

Traffic originating from within the degraded sync. island and terminating outside the island

During the first 24 hours of ESI holdover (≤ 0.37 ppm freq. offset)

DS1/DS3Transport

No noticeable degradation

DS1/DS0 originating or terminating signals

Maximum of 255 slips/day

After the first 24 hours (ESI freerun ≤ 4.6 ppm freq. offset)

DS1/DS3Transport

Traffic continuity is maintained.Noticeable increase in payload output jitter but within the 5 UI (Unit Interval) network limit


Excessive slips; maximum of 2.2 slips/minute

SONET clock freerun (≤ 20 ppm freq. offset)

DS1/DS3Transport

Excessive payload output jitter exceeding the 5 UI (Unit Interval) limit and causing SES (Severely Errored Seconds) or LOF (Loss of Frame)


Excessive slips



Figure 2-8Line timing - synchronization timing island

FW-3485

Preventing timing synchronization islands With synchronization status messaging, the network element is able to monitor and select any of up to four available timing reference signals according to their defined clock quality levels. The signal with the highest clock quality is used, with an automatic timing reference switch being performed if the available signals or their defined clock quality change. The network element can decide to switch to a facility that offers the best synchronization quality level (ST1).

Figure 2-9 on page 2-17 shows that, with synchronization status messaging, after a synchronization failure has occurred, synchronization distribution around the ring is restored to Stratum 1 and the network is now back in equilibrium preventing the creation of synchronization islands.

= Timing flow Note:

Event: Fiber cut

Result: NEs 4 and 5 are traceable to Stratum 3.

Legend:

PRS

(a) Normal operation

NE 6

NE 1

NE 2

NE 3

NE 4

NE 5

PRS

(b) Link failure

NE 6

NE 1

NE 2

NE 3

NE 4

NE 5

Smallsynchronization

island



Figure 2-9Timing island prevented with synchronization status messaging

FW-3486

(a) Normal Operation (b) Link FailurePRS

NE 6

NE 1

NE 2

NE 3

NE 4

NE 5

ST1

ST1

ST1

ST1

ST1

DUS

DUS

DUS

DUS

DUS

ST1

ST1

PRS

NE 6

NE 1

NE 2

NE 3

NE 4

NE 5

ST1

ST1

ST1

ST1

DUS

ST3

DUS

DUS

DUS

ST3

ST3

(c) Reconfiguration

Event: Fiber cutActions: NE 5 enters ST3 holdover and

sends ST3 message to neighbouring nodes.

Event: ST3 message received byNE4 from NE5.Actions: NE 4 switches to alternate ST1 reference

NE 4 sends ST1 message to NE 5NE 4 sends DUS message to NE3.

Event: ST1 message received by NE 5 from NE 4.Actions: NE 5 switches to alternate ST1 reference


= Timing flow

Legend:

PRS

NE 6

NE 1

NE 2

NE 3

NE 4

NE 5

ST1

ST1

ST1

ST1

ST1

ST3

DUS

DUS

DUS

DUS

ST3

(d) Recovery Complete

PRS

NE 6

NE 1

NE 2

NE 3

NE 4

NE 5

ST1

ST1

ST1

ST1

ST1

ST1

DUS

DUS

DUS

DUS

DUS



Timing loopsFigure 2-10 on page 2-19 shows an example of the creation of a timing loop. Timing loops cause excessive jitter and result in loss of traffic. Because they may not be detected locally at the network element, every possible synchronization failure scenario should be analyzed for timing loops so that measures can be taken to prevent them. (See page 1-3 for more details on timing loops.)

Care must be exercised in the provisioning of timing sources to avoid inadvertently creating timing loops during provisioning. In particular, adjacent network elements must never be commissioned so that their ESI cards synchronize to each other. For example, in Figure 2-10 on page 2-19, if NE 1 is timed from adjacent network element NE 2 and NE 2 is timed from NE 1, a timing loop is formed between NE 1 and NE 2, causing them to be out of synchronization with the external timing source (that is, the primary reference source [PRS]). In this type of timing loop, neither of the network elements detects any abnormality; therefore, no alarms are raised and the timing loop cannot be detected.

The implementation of ESI synchronization status messaging greatly minimizes the risk of timing loops being created.

Preventing timing loops With synchronization status messaging, the network element is able to monitor and select any of up to four available timing reference signals according to their defined clock quality levels. The signal with the highest clock quality is used, with an automatic timing reference switch being performed if the available signals or their defined clock quality change. The network element can decide to switch to a facility that offers the best synchronization quality level (ST1) without the risk of creating a timing loop. The do no use for synchronization (DUS) message is automatically sent to indicate that the interface is unsuitable for use as a timing reference. Typically this is used to indicate a limitation imposed by the path of the signal through the network (use of this reference would form a timing loop).

Figure 2-11 on page 2-20 illustrates the self-healing capability using the S1 byte synchronization status messaging of the 6 node ring due to a fiber cut between NE 6 and NE 1. Note that no timing loop is created, which would not be the case if the network does not have synchronization status messaging (see Figure 2-10 on page 2-19).



Figure 2-10Timing loop created - no synchronization status messaging

FW-3487


(b) Link FailurePRS

NE 6

NE 1

NE 2

NE 3

NE 4

NE 5

PRS PRS

PRS

NE 6

NE 1

Timingloop

NE 2

NE 3

NE 4

NE 5

Event: Fiber cut

Timing loop created between NE1 and NE2.

= Timing flow

Legend:

Note:



Figure 2-11Timing loop prevented with synchronization status messaging

FW-3488


(b) Link FailurePRS PRS

NE 6

NE 1

NE 2

NE 3

NE 4

NE 5

ST1

ST1

ST1

ST1

ST1

ST1

ST1

DUS

DUS

ST1

DUS

DUS

PRS PRS

(c) Reconfiguration

Event: Fiber cutActions: NE 1 enters ST3 holdover and

sends ST3 message to neighbouring nodes.

Event: ST3 message received by NE2 from NE1.Actions: NE 2 switches to alternate ST1 reference


Event: ST1 message received by NE 1 from NE 2.Actions: NE 1 switches to alternate ST1 reference

NE 1 sends ST1 message to NE 6NE 1 sends DUS message to NE 2.

= Timing flow

Legend:

(d) Recovery Complete

NE 6

NE 1

NE 2

NE 3

NE 4

NE 5

ST3

ST3

ST1

ST1

ST1

ST1

ST3

DUS

ST1

DUS

DUS

PRS

PRS

NE 6

NE 1

NE 2

NE 3

NE 4

NE 5

ST3

DUS

ST1

ST1

ST1

ST1

ST3

ST1

ST1

DUS

DUS

PRS

PRS

NE 6

NE 1

NE 2

NE 3

NE 4

NE 5

DUS

DUS

ST1

ST1

ST1

ST1

ST1

ST1

ST1

DUS

DUS



Hierarchy violationA hierarchy violation occurs when a BITS of stratum N synchronizes to a BITS of stratum numbered greater than N (a less stable/accurate clock). For example, a hierarchy violation is created if a Stratum 2 BITS is provided with a timing reference from a Stratum 3 BITS. Respecting the hierarchy ensures that synchronization rearrangement does not cause a BITS to be timed from a less accurate BITS (higher-numbered stratum). (For more information, see “Synchronization hierarchy” on page 1-3.)

Figure 2-12 illustrates a hierarchy violation. The ESI interface at NE 3 uses the optical signal received from NE 2 and NE 4 to derive DS1 timing reference outputs. It then uses these DS1s to synchronize its local BITS.

Figure 2-12Hierarchy violation

FW-3539

Preventing hierarchy violations Timing distribution is used to synchronize a large number of networks within a single physical location to a single timing reference signal. The ESI interfaces use internal sources identified as OCA and OCB to derive a timing reference ESI DS1 output (G1OUT or G2OUT). These internal sources are derived from the OC-12 interfaces G1, G2, G1S, or G2S.


(b) BITS FailurePRS

NE 6

DUS

DUS

DUSDUS

ST1

ST1

ST1ST1

ST1

ST1

ST1

ST1

DUS

DUS

DUSDUS

ST3

ST3

ST3ST1

ST3

ST3

ST3

ST3

NE 1

NE 2

NE 3

NE 4

NE 5

ST2BITS

G1OUT=ST1G2OUT=ST1

G1OUT=ST3G2OUT=ST3

PRS

NE 6

NE 1

NE 2

NE 3

NE 4

NE 5

= Timing flow

Legend:

ST2BITS

ST3



With synchronization status messaging on SONET network elements, the network element is able to monitor the clock quality levels of the timing reference signals. If DS1 ESF synchronization status messaging is unavailable, you can use alarm indication signal (AIS) threshold generational the timing reference source is of equal or poorer quality than the user provisioned threshold AIS value, DS1 AIS is inserted on the ESI DS1 output. This ensures the timing distribution ESI DS1 output is not used by the BITS and thus prevents hierarchy violation from occurring.

Figure 2-12 on page 2-21 illustrates an example of how threshold AIS generation can prevent hierarchy violation. In this example, the AIS Threshold value for the ESI DS1 outputs at NE 3 is provisioned to Stratum 2. When the quality level of the timing received from the fiber (indicated by the synchronization status message S1 byte in the SONET overhead) is equal to or below the provisioned AIS threshold (Stratum 2), NE 3 inserts AIS on the ESI DS1 outputs. The Stratum 2 BITS at NE 3 switches to its internal timing, and provides a Stratum 2 quality level signal to the entire system, thus preventing the creation of a hierarchy violation.



Figure 2-13Example of AIS threshold generation

FW-3525

(a) BITS Failure (b) Reconfiguration

DUS

DUS

ST2ST2

ST3

ST3

ST2ST1

DUS

ST2

ST3

ST3

G1OUT=AISG2OUT=AIS

PRS

NE 6

NE 1

NE 2

NE 3

NE 4

NE 5

= Timing flowLegend:

ST2BITS

DUS

(c) Reconfiguration

ST2

ST2

ST2ST2

ST3

DUS

ST2ST1

DUS

ST2

DUS

ST3

G1OUT=AISG2OUT=AIS

PRS

NE 6

NE 1

NE 2

NE 3

NE 4

NE 5

ST2BITS

DUS

(d) Recovery complete

ST2

ST2

ST2ST2

ST2

DUS

ST2ST1

DUS

ST2

DUS

DUS

G1OUT=AISG2OUT=AIS

PRS

NE 6

NE 1

NE 2

NE 3

NE 4

NE 5

ST2BITS

DUS

DUS

DUS

DUSDUS

ST3

ST3

ST2ST1

ST3

ST2

ST3

ST3

G1OUT=AISG2OUT=AIS

PRS

NE 6

NE 1

NE 2

NE 3

NE 4

NE 5

ST2BITS

ST3

Event: BITS failure

Actions: NE 3 ESI DS1 outputs send out AIS.The ST2 BITS at NE 3 switches to itsinternal timing and provides a ST2 qualitylevel signal to NE 3. The NE 3 sends outST2 to neighbouring nodes.

Event: ST2 message received by NE 4 andNE 2 from NE 3.

Actions: NE 4 and NE 2 switch to alternateST2 reference.NE 4 and NE 2 send ST2 message toupstream nodes and DUS to NE 3.

ST2 message received by NE 5 and NE 1 fromNE4 and NE 2.

Actions: NE 5 and NE 1 switch to alternate ST2 reference.NE 5 and NE 1 send ST2 message to NE 6 and DUS message to downstream nodes.

Event:Event: ST2 message received by NE 6 fromNE 5 and NE 1.

Actions: NE 6 switches to alternateST2 reference.NE 6 sends ST2 message to NE 5and DUS message to NE 1.


3-1

Setting up timing and synchronization3-This chapter describes how to provision shelf timing and ESI. It provides:

• settings required for the different shelf timing modes

• the conditions when ESI is required

• the parameters required to provision shelf timing and ESI

• the SETUPESI command

• guidelines for mix mode provisioning

Specific details and procedures on provisioning shelf timing and ESI are found in Commissioning Procedures, 323-1111-220.

Introduction to shelf timingThe OC-3/OC-12 network elements support five primary shelf timing modes. The shelf timing modes available at a network element depend on the network element type. The shelf timing modes are:

• external timing (for ADMs and terminals that use an external timing source)

• line timing (for ADMs and terminals)

• loop timing (for terminals)

• through timing (for OC-12 regenerators)

• shelf freerun timing (for ADMs and terminals)

There are three types of line timing:

• ESI line timing (for ADMs and terminals equipped with ESI equipment)

• VTM line timing (for VTM ring ADMs)

• primary optics line timing (for linear ADMs without ESI equipment)

For shelf timing modes that do not use ESI equipment, the setting of the shelf clock source determines the shelf timing mode. For shelf timing modes that use ESI equipment, the settings of the clock source and timing reference together determine the shelf timing mode.


3-2 Setting up timing and synchronization

The shelf equipment screen of the network element (NE) user interface displays the shelf clock source beside the label “NE Clock Source”. The timing reference protection screen displays the timing references under the heading “Source”.

Table 3-1 lists the required shelf clock source and timing reference settings for each shelf timing mode and network element type.

Network elements, with shelf clock sources provisioned as VTM line timed or ESI, have two additional shelf timing modes:

• ESI holdover and ESI freerun

• VTM holdover and VTM freerun

ESI freerun provides a greater accuracy than shelf freerun, and ESI holdover provides a greater accuracy than ESI freerun. The VTM holdover provides greater accuracy than shelf freerun without the requirement to equip a network element with ESI units. Table 1-4 on page 1-19 shows the clock stability for holdover and freerun.

VTM and ESI holdover improve network stability under fault conditions. If a network element has a setting of ESI for its shelf clock source and all timing references fail, the shelf timing mode changes to ESI holdover. ESI holdover stability is guaranteed during the first 24 hours.

If a network element has vtmlinetimed for its shelf clock source, and all timing reference fail, the shelf timing mode changes to VTM holdover. VTM holdover stability is guaranteed during the first 24 hours.

The NE user interface allows you to provision ESI and VTM freerun and holdover. Usually, you only provision holdover for testing purposes.

The current clock mode for the ESI units or OC-12 VTM circuit packs determines if the shelf timing mode is ESI holdover or freerun, or VTM holdover or freerun. To change the clock mode, you edit the target clock mode.

You can use the ESI equipment screen of the NE user interface to change the ESI target clock mode to normal, holdover or freerun. For VTM network elements, you can use the OC-12 equipment screen of the NE user interface to change the VTM target clock mode to normal, holdover or freerun.

Table 1-4 shows the settings for ESI holdover and freerun, VTM holdover and freerun, and shelf freerun.


Setting up timing and synchronization 3-3

Table 3-1Shelf clock source and timing reference settings for each shelf timing mode

Shelf timing mode ESI required

Network element type(see Note 1)

Shelf clock source

Possible timing references(see Note 2)

External timing yes NWK ring ADM,VTM ring ADM,linear ADM,linear terminal

ESI BITSA, BITSB

Line timing ESI line timing yes NWK ring ADM,VTM ring ADM,linear ADM,linear terminal (see Note 3)

ESI G1, G2 for linear terminal and VTM ring;G1, G1S for NWK ring;G1, G2, G1S, G2S for linear ADM

VTM line timing no VTM ring ADM VTM line timed

G1, G2

Primary optics timing

no linear ADM primary optics not applicable

Loop timing no linear terminal loop timed not applicable

Through timing no OC-12 regenerator

through timed (see Note 4)

not applicable

Shelf freerun no NWK ring ADM,VTM ring ADM,linear ADM,linear terminal

freerun not applicable

Note 1: Linear systems contain OC-12 networking interface circuit packs (NT7E02) or OC-3 networking interface circuit packs (NT7E01). NWK rings contain OC-12 networking interface circuit packs (NT7E02). VTM rings contain OC-12 VTM circuit packs (NT7E05).

Note 2: When the shelf clock source is ESI, the timing reference determines if the shelf timing mode is external timing or line timing. In other cases, you only need the shelf clock source to determine the shelf timing mode.

Note 3: On terminal network elements with ESI equipment, when the shelf clock source is ESI and the timing references are G1 or G2, the shelf timing mode is line timing. On OC-48 network elements, Nortel Networks calls the same case loop timing.

Note 4: On regenerator shelves, the clock source is always through timed. You cannot change this setting.



Network elements that require ESIExternal synchronization interface (ESI) units enable the network element to

• input timing from an external source,

• improve the timing accuracy when all timing references fail, through ESI holdover or ESI freerun, and

• provide timing distribution.

The following summarizes when a network element must have ESI equipment.

Linear systems• Linear point-to-point systems running asynchronously do not require ESI

at either terminal.

• Linear systems that contain add-drop multiplexers (ADMs) must have at least one external timing source (for example, building-integrated timing supply [BITS]). This external timing source can be applied to the system at any terminal or linear ADM network element. All network elements that accept an external timing source must be equipped with ESI.

• In a linear system, a linear ADM network element that is not externally timed can use ESI line timing or primary optics line timing. Those that use ESI line timing must be equipped with ESI.

• In a linear system, a terminal network element that is not externally timed can use ESI line timing or loop timing. Those that use ESI line timing must be equipped with ESI.

NWK ring systems• In an NWK ring system, all ring ADM network elements use external

timing or ESI line timing. In either case, they must be equipped with ESI.

VTM ring system• In a VTM ring system, ESI equipment is required in ring ADM network

elements that use external timing (usually only one or two NEs in the ring), or that are ESI line timed. Network elements that are VTM line timed do not require ESI. ESI line timed network elements have better holdover stability than VTM line timed network elements.

Timing distribution• All network elements that distribute timing to other equipment must be

equipped with ESI. This applies to network elements in linear, NWK ring and VTM ring systems.

Shelf timing parametersThe following describes the parameters required to provision shelf timing and ESI. Possible values for these parameters and the default values are given in the chapter on provisioning shelf timing and ESI, in Commissioning Procedures, 323-1111-220.



Timing inputsTiming referencesAt line timed network elements, timing is derived and generated from the optics sources. To provision line timing, you must provision the source of the timing references.

At externally timed networks elements, the BITS (building-integrated timing supply) sends timing to the ESI through the ESI input facilities, BITSA and BITSB. To provision ESI timing input, you must provision the source of the timing references and the BITSA and BITSB input facilities.

You can provision up to four sources (numbered 1 to 4) as timing references for timing generation. In normal circumstances, timing reference number 1 has the highest priority and number 4 has the lowest priority. Systems that support synchronization status messaging also use the clock quality levels of the timing references. Whenever two or more available sources carry the same clock quality message, the system selects the source with the highest priority for a reference protection switch. If two or more valid timing references have the same quality level, the active timing reference remains in use. The timing reference number priority shown on the pr tp screen for activities on the inactive references or facility states switching between IS and non IS, has no effect in this case.

For systems that do not support synchronization status messaging, the clock quality level is provisioned as STU.

You must set each timing reference source to one of the following values:

• the external timing sources; BITSA or BITSB

• the optics sources; OC-3/OC-12 G1, G2, G1S or G2S (the available optics sources depend on the network element type)

• or null, to disable the timing reference source

If your system has synchronization status messaging, you can use mix mode provisioning at externally timed network elements. Mix mode provisioning uses both external and optics sources for timing references.

For synchronization status messaging, you must assign a clock quality level for each timing reference. Both the timing reference source and the quality level appear on the timing reference protection screen of the network element user interface. On linear network elements, you must also enable the SONET overhead on the working and protection channels.

Mix mode provisioningYou can use mix mode provisioning at externally timed OC-12 network elements that have synchronization status messaging.



Externally timed network elements are usually provisioned with two timing references, BITSA and BITSB. Line timed network elements are usually provisioned with one or two optical interfaces (for example, OC-12 G1 and OC-12 G2) as timing references sources.

Mix mode provisioning uses both external and optics sources for timing references. The network element allows you to provision up to four timing reference sources.

ESI timing input facilitiesTo provision the ESI input facilities, BITSA and BITSB, you must set the line coding format, the signal format and the DS1 framing format.

Timing distributionYou can distribute timing references from any network element with ESI equipment. Each ESI unit (G1 or G2) can provide one DS1 timing signal to synchronize external equipment, such as a BITS. The ESI uses its G1OUT and G2OUT facilities to distribute timing.

When you do not require timing distribution, you must set G1OUT and G2OUT out of service.

Timing distribution sourcesThe OC-3/OC-12 TBM refers to the two provisioned optics sources as OCA and OCB. The system assigns an optical interface (OC-3/OC-12 G1, G2, G1S or G2S depending on the network element type) for OCA and OCB. You can view the OCA and OCB assignments on the timing reference source screen of the NE user interface. You can also change the timing references assigned to OCA or OCB. Note that both internal shelf timing and timing distribution use the same OCA and OCB signals.

You can use the source tracking parameter to provision how the ESI derives the timing signal that it distributes on G1OUT and G2OUT. The source tracking parameter appears on the ESI facility screen. The source tracking can be set to ACT or OFF.

The effect of the ACT settings depends on whether a network element is line timed or externally timed.

When the source tracking is ACT:

• on line-timed network elements, the derived DS1 signal used for timing distribution follows the active OC-3 or OC-12 timing source

• on externally timed network elements, the derived DS1 used for timing distribution follows the OC-12 timing source with the highest quality synchronization status message



The effect of the OFF setting is the same for both line timed and externally timed network elements. When the source tracking is OFF, you use the source parameter in the ESI facility screen to directly assign OCA or OCB as sources for G1OUT and G2OUT.

You can provision the sources as follows:

• the G1OUT and G2OUT outputs for timing distribution, both come from a single OC-3 or OC-12 interface (that is, both come from OCA or both come from OCB), or

• the G1OUT outputs for timing distribution comes from one OC-3 or OC-12 interface and the G2OUT output for timing distribution comes from another OC-3 or OC-12 interface (that is, one comes from OCA and the other comes from OCB)

When the source tracking is OFF and the signal used to derive timing distribution fails, the ESI outputs an alarm indication signal (AIS) even if another timing signal is available.

You can use one of two methods to alert a BITS to a degradation in the clock quality level of the distributed timing signal:

• message pass-through mode, and

• alarm indication signal (AIS) generation mode.

The message pass-through mode requires the system to support synchronization status messaging between the ESI and BITS. In this mode, the BITS directly receives the quality level of the timing distribution signal.

In the AIS generation mode, if the synchronization status message contained within the OC-12’s S1 byte is of equal or poorer quality than the user provisioned threshold value, the ESI DS1 output sends DS1 AIS.

You can use the ESI facility screen to provision the threshold AIS. If you set the AIS parameter to NULL, the ESI uses the message pass-through mode. If you set the threshold to a specific quality level, and the quality level of the timing reference source is equal to or poorer than the threshold, the ESI sends an AIS to the BITS.

ESI timing output facilitiesTo provision the ESI output facilities, G1OUT and G2OUT, you must set the line coding format, the DS1 framing format and the line build-out.

Tools for provisioning shelf timing and ESIIn addition to the network element interface, you can use two command interpreter tools to assist in provisioning shelf timing and ESI: SHELF_CLOCK_CI and SYNCMSGCI.



SHELF_CLOCK_CI toolYou can set all the parameters required to provision shelf timing and ESI using the network element user interface. Alternatively for OC-12 NEs, you can provision all shelf timing modes (with the exception of holdover and freerun) using the SETUPESI command within the SHELF_CLOCK_CI tool. The SETUPESI command eases the provisioning of shelf timing. It also speeds setting up a network to support synchronization status messaging.

Note: Run the SETUPESI command on only one NE at a time to ensure consistent results.

You can use SETUPESI command on OC-12 NEs to provision the shelf timing modes that do not use ESI (that is, primary optics timing, VTM line timing and loop timing), as well as those that use ESI (that is ESI line timing and external timing).

The SETUPESI command includes parameters that define how it provisions shelf timing. The parameters required are dependent on the type of shelf timing mode, as summarized in Table 3-2. As indicated in the table, some parameters are mandatory, some parameters are optional.

The chapter on shelf timing and ESI in Commissioning Procedures, 323-111-220, gives the procedures to use the SETUPESI command. The following list summarizes each of the SETUPESI parameters and when they are required.

• configuration

— specifies the shelf timing mode

— required for all shelf timing modes

• frame format

— specifies whether extended superframe (ESF) or superframe (SF) framing format will be used

— required for shelf timing modes that use ESI

• messaging

— specifies whether synchronization status messaging will be used

— required for shelf timing modes that support synchronization status messaging

— messaging setting for VTM line timed network elements is always msgon because VTM rings require synchronization status messaging to retain robustness

• threshold

— specifies the AIS threshold setting for timing distribution

— optional; for shelf timing modes that use ESI



• mix mode

— specifies how the optics sources (OCA and OCB) and the BITS sources (BITSA and BITSB) are assigned to the four possible timing references

— optional; for shelf timing modes that use external timing

SYNCMSGCI toolThe SYMCMSGCI provides tthree commands: DUSFORST3, QRYMSG and EDITTX. For a description of the application of the DUSFORST3 command see “DUS for ST3” on page 2-9. QRYMSG displays each facility that receives or transmits synchronization status messages, and shows the associated clock quality level. EDITTX manually provisions the quality level transmitted on OC-12 line optics, OC-3 tributaries, and the ESI output facilities G1OUT and G2OUT. Procedures to use these commands are given in Commissioning Procedures, 323-1111-220.

Note: If the G1OUT/G2OUT facilities have been provisioned to non auto values, then source tracking has no effect. EDITTX for G1OUT/G2OUT is not supported (and hence not recommended) when source tracking is active.

Mix mode provisioningTo provide better network timing survivability, you can use mix mode provisioning at externally timed OC-12 network elements that have synchronization status messaging.

Externally timed network elements are usually provisioned with two timing references, BITSA and BITSB. Line timed network elements are usually provisioned with one or two optical interfaces (for example, OC-12 G1 and OC-12 G2) as timing references sources.

Table 3-2Parameters required for the SETUPESI command

Shelf timing mode

configuration(mandatory)

frame format(mandatory)

messaging(mandatory)

threshold(optional)

mix mode(optional)

External timing external sf, esf msgon, msgoff stu, st2, st3, smc, null

off, oca, ocb, on

ESI line timing line timed sf, esf msgon, msgoff stu, st2, st3, smc, null

– – –

VTM line timing vtmlinetimed – – – msgon – – – – – –

Primary optics timing

primaryoptics – – – – – – – – – – – –

Loop timing looptimed – – – – – – – – – – – –



Mix mode provisioning uses both external and optics sources for timing references. The network element allows you to provision up to four timing reference sources.

Mix mode provisioning provides better network timing survivability. Mix mode provisioning requires careful network planning to make sure timing loops do not form under fault conditions.

Engineering guidelinesTo provide for better timing survivability, OC-N interfaces can be provisioned at externally timed network elements. However, because of the synchronization-status messaging protocol adopted in Bellcore document GR-253-CORE, timing loops can be created during fault conditions when mix mode provisioning is used at a network element. Whenever a timing sub-system is designed within a network, it must be studied to determine its susceptibility to timing loops under fault conditions. The following sections provide engineering guidelines on mix mode provisioning in OC-12 ring and linear systems.

Mix mode provisioning in ring systems• Do not use mix mode provisioning in a ring system if there is only one

externally timed network element. Figure 3-1 on page 3-12 shows the formation of a timing loop when mix mode provisioning is used in a ring system with only one externally timed network element.

• Mix mode provisioning can be used in a ring system if there are two externally timed network elements. However, one externally timed network element must have only the clockwise optics provisioned as a source. The other externally timed network element must have only the counter-clockwise optics provisioned as a source.

Figure 3-2 on page 3-13 shows the formation of a timing loop if mix mode provisioning is used in a ring system and the rule above is not followed (both externally timed network elements have the same direction optics provisioned as a source). The timing loop would have been prevented if the rule was followed.

Note: Figure 3-2 on page 3-13 shows clockwise timing distribution. Although the network may have been originally configured to use closest-to-source or split timing distribution, it may change to use clockwise timing distribution as a result of failures and non-revertive switching between timing references.

CAUTIONRisk of timing loop formationIt can sometimes be difficult to determine the direction of traffic flow at a given network element. Examine network topology diagrams carefully.



• Mix mode provisioning can be used in a ring system if there are more than two externally timed network elements. One externally timed network element must only have the clockwise optics provisioned as a source. Another externally timed network element must only have the counter-clockwise optics provisioned as a source. The other externally timed network elements may have both optics provisioned.

Mix mode provisioning in linear systems equipped with linear ADMs• There is no danger of forming timing loops in linear systems when mix

mode provisioning is used.

• There is no benefit in using mix mode provisioning in a linear system if there is only one externally timed network element.

This is displayed in Figure 3-3 on page 3-14. In the top system, a terminal network element is externally timed. If the BITS sources fail, there would be no switch to OC-12 G1 since it is receiving the DUS synchronization status message. In the bottom system, an ADM network element is externally timed. If the BITS sources (ESI DS1 inputs BITSA and BITSB) fail, there would be no switch to OC-12 G1 or OC-12 G1S since they are receiving the DUS synchronization status message.

• Mix mode provisioning can be used in a linear system without any possibility of forming timing loops if the linear system has two or more externally timed network elements. For it to work properly, both optics (OC-12 G1 and OC-12 G1S) must be provisioned at externally timed ADM network elements as sources 3 and 4. At externally timed terminal network elements, the OC-12 G1 optics is provisioned as the third source.

This scenario is displayed in Figure 3-4 on page 3-15, where two end terminals are externally timed, and in Figure 3-5 on page 3-16, where two intermediate ADM network elements externally timed.



Figure 3-1Timing loop in ring: only one externally timed NE with mix mode provisioning

FW-3541

PRS

Event: BITS failureActions: NE 6 switches to alternate reference

G2 causing a timing loop.

Normal Operation BITS Failure

NE 6

NE 1

NE 2

NE 3

NE 4

NE 5

ST1

ST1

ST1

ST1

ST1

ST1

DUS

DUS

DUS

DUS

DUS

ST1

G1G2

G1

G2

G1

G2

G1

G2

G1

G2

G1G2

PRS

NE 6

NE 1

NE 2

NE 3

NE 4

NE 5

ST1

ST1

ST1

ST1

ST1

ST1

DUS

DUS

DUS

DUS

DUS

DUS

G1G2

G1

G2

G1

G2

G1

G2

G1

G2

G1G2

Timing sources provided at NE6 are 1.BITSA 2. BITSB 3. OC-12 G2

= Timing flow

Note:Legend:



Figure 3-2Timing loop in ring: two externally timed NEs with mix mode provisioning

FW-3542


(b) BITS FailurePRS

PRS

PRS

NE 6

NE 1

NE 2

NE 3

NE 4

NE 5

ST1

ST1

ST1

ST1

ST1

ST1

ST1

DUS

DUS

DUS

DUS

DUS

G1G2

G1

G2

G1

G2

G1

G2

G1

G2

G1G2

PRS

NE 6

NE 1

NE 2

NE 3

NE 4

NE 5

ST1

ST1

ST1

ST1

ST1

ST1

DUS

DUS

DUS

DUS

DUS

DUS

G1G2

G1

G2

G1

G2

G1

G2

G1

G2

G1G2

(c) BITS FailurePRS

NE 6

NE 1

NE 2

NE 3

NE 4

NE 5

ST1

ST1

ST1

ST1

ST1

ST1

DUS

DUS

DUS

DUS

DUS

DUS

G1G2

G1

G2

G1

G2

G1

G2

G1

G2

G1G2

Event: BITS failure at NE6Actions: NE 6 switches to alternate reference

G2 and sends DUS message to NE 5.

Event: BITS failure at NE3Actions: NE 3 switches to alternate reference

G1 causing a timing loop.

Timing sources provided at NE3 are 1.BITSA 2. BITSB 3.OC-12 G1


= Timing flow

Note:

Legend:



Figure 3-3No benefit using mix mode provisioning in linear system with only one externallytimed NE

FW-2623 (R11.2)

NE1 NE2

G1 G1 G1

G1SG1SDUS


DUS DUS

G1

NE3

ST1ST1PRS ST1

NE4

Note:

NE1 NE2

G1 G1 G1

G1SG1SST1

Timing sources provided at NE2 are 1.BITSA 2. BITSB 3.OC-12 G1 4.OC-12 G1S

= Timing flow

DUS DUS

PRS

G1

NE3

ST1DUS ST1

NE4

Note:

Legend:



Figure 3-4Mix mode provisioning in linear system with two externally timed terminal NE

FW-3481

GISGIS ST1ST1DUS

G1G1 G1G1 DUSST1ST1PRS

= Timing flow

Legend:

NE1

PRS

PRS

PRS


NE2 NE3 NE4

Timing sources provided at NE 1: 1. BITSA 2. BITSB 3. OC-12 G1

Timing sources provided at NE 4: 1. BITSA 2. BITSB 3. OC-12 G1

GISGIS ST1ST1ST1

G1G1 G1G1 DUSDUSST3PRS

NE1

(b) BITS failure and reconfiguration

NE2 NE3 NE4

Event: BITS failure at NE 1 Actions: NE1 enters ST3 holdover and sends ST3 message to NE 2. NE 2 switchesto alternate ST1 reference. NE 2 sends ST1 to NE 1 and DUS to NE 3.

GISGIS ST1ST1ST1

G1G1 G1G1 DUSDUSDUSPRS

NE1

(c) Recovery complete

NE2 NE3 NE4

Event: ST1 message received by NE 1. Actions: NE 1 switches to alternate ST1 reference. NE 1 sends DUS message to NE 2.



Figure 3-5Mix mode provisioning in linear system with two externally timed ADM NE

FW-3482

= Timing flow

Legend:


Timing sources provided at NE 2: 1. BITSA 2. BITSB 3. OC-12 G1 4. OC-12 G1S

Timing sources provided at NE 3: 1. BITSA 2. BITSB 3. OC-12 G1 4. OC-12 G1S

GISGIS DUSST1ST1

G1G1 G1G1 ST1ST1DUSNE1 NE2 NE3 NE4

Event: BITS failure at NE 2. Actions: NE 2 switches to alternate ST1 reference and sends the DSU message to NE 3.

PRS PRS

(b) BITS failure and recovery

GISGIS DUSST1ST1

G1G1 G1G1 ST1DUS DUSNE1 NE2 NE3 NE4

PRS PRS


SONET Transmission Products

S/DMS TransportNodeOC-3/OC-12 NE—TBMTiming and Synchronization Description

Copyright 1992–2001 Nortel Networks, All Rights Reserved

The information contained herein is the property of Nortel Networks and is strictly confidential. Except as expressly authorized in writing by Nortel Networks, the holder shall keep all information contained herein confidential, shall disclose it only to its employees with a need to know, and shall protect it, in whole or in part, from disclosure and dissemination to third parties with the same degree of care it uses to protect its own confidential information, but with no less than reasonable care. Except as expressly authorized in writing by Nortel Networks, the holder is granted no rights to use the information contained herein.

Nortel Networks and S/DMS TransportNode are trademarks of Nortel Networks. VT100 is a trademark of Digital Equipment Corporation. UNIX is a trademark of X/Open Company Ltd.

323-1111-192Rel 14 StandardFebruary 2001Printed in Canada

s/dms transportnode oc-3/oc-12 ne—tbm

Documents

timing synchronization

timing distribution

timing loops

external timing

freerun timing

timing sources

loop timing

shelf timing parameters