SDW2005 - TAORMINA

A NEW GENERATION OF DATA AND CONTROL INTERFACES FOR DIGITAL

DETECTORS

F. Bortoletto1, M. D’Alessandro1, E. Giro1,

R. Cosentino2, M. Belluso2, A. Carbone3, M. Gemma3

1INAF-Osservatorio Astronomico di Padova Italy,2INAF-Osservatorio Astronomico di Catania Italy, 3SKYTECH

LaSpezia Italy

SDW2005 - TAORMINA

Project Main Requirements:

1. Upgrade for the precedent generation of transputer based VME/VSB boards saving compatibility with high

level SW (table editors)2. Compatibility with modern bus architecture, I.E.: PCI,

CPCI, VME and modern bus-adapters (AMCC chips)3. Use of host computer memory for data storage via PCI

fast data transfers 4. Use of fast throughput, full-duplex, data & controls link

between host interface and remote electronics 5. On board (host interface) generation of detector clock

sequences and transmission through the fast control link

SDW2005 - TAORMINA

The PCI model for the sequencer/interface board:

Simplified PCI version for thesequencer/interface board

PCI sequencer/interfaceboard main functions

AMCCPCI-ADAPTER

S5933

FULL-DFIBRELINK

1.2 Gbaud

DSP56301

PCI-BUS

FIFO32Kx32

32K/24Y

32 bitsDATA BUS

DSP DATA/PROGRAMBUS

32K/24X

32K/24P

CLOCKS/TELEMETRY/

PROGRAMMING

DATA/CLOCKS/

TELEMETRY/PROGRAMMING

OPTOCOUPLEDPORT

8IN/8OUT

DSP LEDgreen

PMC LEDred

SYNCR. IN/OUT

AMCCNV-MEMORY

DSPhost-port

DMAFIFO

SDW2005 - TAORMINA

Dual slots PMC piggy-back detector interfacemounted on a Motorola C-PCI CPU

PMC sequencer & detectorInterface main functions

The PMC model for the sequencer/interface board:

AMCCNV-MEMORY

XILINKFPGA

XCV800

AMCCPCI-ADAPTER

S5933

FULL-DFIBRELINK

1.2 Gbaud

FPGA-BOOT

DSP56301

PMC-BUS

FIFO32Kx32

32K/24Y

8 MbSYNCR.

RAM

32 bitsDATA BUS

DSP DATA/PROGRAMBUS

32K/24X

32K/24P

CLOCKS/TELEMETRY/

PROGRAMMING

DATA/CLOCKS/

TELEMETRY/PROGRAMMING

OPTOCOUPLEDPORT

8IN/8OUT

DSP LEDgreen

XILINK LEDred

PMC LEDred

SYNCR. IN/OUT

DMAFIFO

The PMC module can be mounted in a variety of VME/C-PCI boards. It implements the same

concept found on the PCI version with the presence of a large, host computer, configurableFPGA dedicated to the implementation of fast

local functions on the data-flow

SDW2005 - TAORMINA

Glue-Logic is embedded on a Xilinx FPGA.It provides communication with the PCI/PMC host I/F board and all the logics for the implementation of a

detector controller in a scalable way

The Remote Glue Logic Board:

XlinxSpartan XCF20

1.2 GbaudFULL-DUPLEX FIBRE LINK

DETECTOR CLOCKS (8+8)PROCESSING CLOCKS (8)

TELEMETRY SERIAL ADCDATA/CONTROL BUS

BIAS/CLOCK LEVELS SERIAL DACDATA/CONTROL BUS

I M G 5B R D _ A D 2

D E V _ D T 1 4

S Y S RS T *

/ E F 2

I M G 1 9

A D + 5 V

I M G 9

D E V _ D T 1 8

I M G 2 0

V P H 1

S Y S RS T *

S Y S CL K

D E V _ D T 2 0

I M G 1 0

A D + 5 V

/ F I F O _R D 0

/ F I F O _R D 3

A + 8V

I M G 6

D E V _ A D 0

D E V _ D T 1 0

D E V _ D T 1 6

I M G 1 3

I M G 7

P 2

D I N 41 6 1 2C

A 1A 2A 3A 4A 5A 6A 7A 8A 9

A 1 0A 1 1A 1 2A 1 3A 1 4A 1 5A 1 6A 1 7A 1 8A 1 9A 2 0A 2 1A 2 2A 2 3A 2 4A 2 5A 2 6A 2 7A 2 8A 2 9A 3 0A 3 1A 3 2

B 1B 2B 3B 4B 5B 6B 7B 8B 9

B 1 0B 1 1B 1 2B 1 3B 1 4B 1 5B 1 6B 1 7B 1 8B 1 9B 2 0B 2 1B 2 2B 2 3B 2 4B 2 5B 2 6B 2 7B 2 8B 2 9B 3 0B 3 1B 3 2

C 1C 2C 3C 4C 5C 6C 7C 8C 9

C 1 0C 1 1C 1 2C 1 3C 1 4C 1 5C 1 6C 1 7C 1 8C 1 9C 2 0C 2 1C 2 2C 2 3C 2 4C 2 5C 2 6C 2 7C 2 8C 2 9C 3 0C 3 1C 3 2

/ F I F O _R D 6

D E V _ D T 7

V P H 2

/ E F 1

I 0

/ D E V _ W R

/ F I F O _R D 5

A D + 5 V

A -2 0 V

D E V _ D T 2

I M G 1

D E V _ D T 1

B R D _ A D 1

D E V _ D T 9

/ E F 4

D E V _ D T 0

/ E F 0

A D + 5 V

C 3 3 31 u

B R D _ A D 0

D E V _ D T 1 3

/ D E V _ R D

I 1

I M G 1 4

A + 34 V

I 2

D E V _ D T 3

/ F I F O _R D 1

I M G 2

A -8 V

/ E F 5

A D + 5 V

D E V _ D T 1 1

I 3

D E V _ D T 4D E V _ D T 5

I M G 1 8

/ E F 6

D E V _ A D 1

D G N D

A + 34 V

I M G 3

D E V _ A D 2

I M G 1 7

V P H 0

I M G 0

D E V _ D T 1 5

/ E F 3

I M G 1 2

/ F I F O _R D 2

/ E F 7

D E V _ D T 8

D E V _ D T 1 7

D E V _ D T 1 2

D E V _ D T 6

/ D E V _ E F

I 5

/ F I F O _R D 7

A D + 5 V

P 1

D I N 41 6 1 2C

A 1A 2A 3A 4A 5A 6A 7A 8A 9

A 1 0A 1 1A 1 2A 1 3A 1 4A 1 5A 1 6A 1 7A 1 8A 1 9A 2 0A 2 1A 2 2A 2 3A 2 4A 2 5A 2 6A 2 7A 2 8A 2 9A 3 0A 3 1A 3 2

B 1B 2B 3B 4B 5B 6B 7B 8B 9

B 1 0B 1 1B 1 2B 1 3B 1 4B 1 5B 1 6B 1 7B 1 8B 1 9B 2 0B 2 1B 2 2B 2 3B 2 4B 2 5B 2 6B 2 7B 2 8B 2 9B 3 0B 3 1B 3 2

C 1C 2C 3C 4C 5C 6C 7C 8C 9

C 1 0C 1 1C 1 2C 1 3C 1 4C 1 5C 1 6C 1 7C 1 8C 1 9C 2 0C 2 1C 2 2C 2 3C 2 4C 2 5C 2 6C 2 7C 2 8C 2 9C 3 0C 3 1C 3 2

/ F I F O _R D 4

I M G 1 5

I M G 1 1

I 6I 7

I M G 8

I M G 4

I M G 1 6

A + 20 V

I 4

D E V _ D T 1 9

VIDEO/CARD SEL.BUS (4x4 CHAN.)

SYSTEM BUS/POWER SUPPLY

SE

RV

ICE

SI/

O P

OR

T

Example of Glue-Logic remote board with programmable clocks, services,telemetry and system bus implemented on a 8 layers SMD double-euro card

SDW2005 - TAORMINA

System Expansion for High Number of Video Channels:

Ethernet

Ca

ble

Ca

ble

Ca

ble

SEQUENCER SYNC LINE

SLAVE PCI-IF SLAVE PCI-IF SLAVE PCI-IF

MASTER PCI-IF

A common synchronization line driven by a master PCI/PMC interfaceallows expansion to a distributed acquisition system.

GLUE-LOGICBOARDS