A Reduced-Bit Multiplication Algorithm for DigitalArithmetic

Harpreet Singh Dhillon and Abhijit Mitra

Abstract—A reduced-bit multiplication algorithm based on theancient Vedic multiplication formulae is proposed in this paper.Both the Vedic multiplication formulae, Urdhva tiryakbhyam andNikhilam, are first discussed in detail. Urdhva tiryakbhyam, beinga general multiplication formula, is equally applicable to all cases ofmultiplication. It is applied to the digital arithmetic and is shown toyield a multiplier architecture which is very similar to the populararray multiplier. Due to its structure, it leads to a high carry prop-agation delay in case of multiplication of large numbers. NikhilamSutra, on the other hand, is more efficient in the multiplication of largenumbers as it reduces the multiplication of two large numbers to thatof two smaller numbers. The framework of the proposed algorithmis taken from this Sutra and is further optimized by use of somegeneral arithmetic operations such as expansion and bit-shifting totake advantage of bit-reduction in multiplication. We illustrate theproposed algorithm by reducing a general 4× 4-bit multiplication toa single 2× 2-bit multiplication operation.

Keywords—Multiplication, algorithm, Vedic mathematics, digitalarithmetic, reduced-bit.

I. INTRODUCTION

D IGITAL multipliers [1], [2] are the core components ofall the digital signal processors (DSPs) and the speed

of the DSP is largely determined by the speed of its multi-pliers [3]. They are indispensable in the implementation ofcomputation systems realizing many important functions suchas fast Fourier transforms (FFTs) and multiply accumulate(MAC). Two most common multiplication algorithms followedin the digital hardware are array multiplication algorithm andBooth multiplication algorithm [4]. The computation timetaken by the array multiplier is comparatively less becausethe partial products are calculated independently in parallel.The delay associated with the array multiplier is the timetaken by the signals to propagate through the gates thatform the multiplication array. Booth multiplication is anotherimportant multiplication algorithm [5]. Large booth arraysare required for high speed multiplication and exponentialoperations which in turn require large partial sum and partialcarry registers. Multiplication of two n-bit operands usinga radix-4 booth recording multiplier requires approximatelyn/(2m) clock cycles to generate the least significant half ofthe final product, where m is the number of Booth recoderadder stages. Thus, a large propagation delay is associatedwith this case. Due to the importance of digital multipliersin DSP, it has always been an active area of research and

Manuscript received Mar 01, 2008.The authors are with the Department of Electronics and Communication

Engineering, Indian Institute of Technology (IIT) Guwahati, India. E-Mail:{harpreet; a.mitra}@iitg.ernet.in.

a number of interesting multiplication algorithms have beenreported in the literature [6]–[9].

This paper presents one such new multiplication algorithmwhich circumvents the need of large multipliers by reducingthe multiplication of large numbers to that of smaller numbers.This reduces the propagation delay associated with the con-ventional large multipliers considerably. The framework of theproposed algorithm is primarily based on the Nikhilam Sutra(formula) of Vedic mathematics [10] and is further optimizedto take full advantage of reduction in the number of bits inmultiplication.

Although Nikhilam Sutra is applicable to all cases of mul-tiplication, it is more efficient when the numbers involved arelarge. In addition to this Sutra, Vedic mathematics deals withanother multiplication formula, Urdhva tiryakbhyam, which isequally applicable to all cases of multiplication. Attempts havebeen made in the literature to apply this general multiplicationformula to binary arithmetic. In [11], this Sutra is shown tobe more efficient multiplication algorithm as compared to theconventional counterparts. Another paper [12] has also shownthe effectiveness of this Sutra to reduce the N ×N multiplierstructure into an efficient 4× 4 multiplier structures.

In this paper, Urdhva tiryakbhyam Sutra is first applied tothe binary number system and is used to develop a digitalmultiplier architecture. This is shown to be very similar tothe popular array multiplier architecture. Nikhilam Sutra isthen discussed and is shown to be much more efficient in themultiplication of large numbers as it reduces the multiplicationof two large numbers to that of two smaller ones. Theproposed multiplication algorithm is then illustrated to showits computational efficiency by taking an example of reducinga 4 × 4-bit multiplication to a single 2 × 2-bit multiplicationoperation. The basic framework of the proposed algorithm istaken from the Nikhilam Sutra of Vedic mathematics and isfurther optimized to take full advantage of the bit-reduction inmultiplication.

This paper is organized as follows. In Section 2, a briefoverview of Vedic mathematics is provided. Section 3 dealswith the Vedic multiplication Sutras followed by the proposedalgorithm. Concluding remarks are presented in Section 4.

II. VEDIC MATHEMATICS

Vedic mathematics is the name given to the ancient Indiansystem of mathematics that was rediscovered in the earlytwentieth century from ancient Indian sculptures (Vedas) bySri B. K. Tirtha (1884-1960) [10]. It mainly deals withVedic mathematical formulae and their application to various

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3 2 5

7 3 8

Result = 4 0Prev. Carry = 0

04

Carry = 4

3 2 5

7 3 8

3 2 5

7 3 8

STEP 3

Prev. Carry = 3Result = 6 5

86

8 5 0

Carry = 6

3 2 5

7 3 8

3 2 5

7 3 8

0

STEP 1 STEP 2

Result = 3 1Prev. Carry = 4

Carry = 3

5 0

53

Result = 2 3Prev. Carry = 6

2 9

Carry = 2

9 8 5 0

STEP 4

Result = 2 1Prev. Carry = 2

2 3 9 8 5 0

2 3

STEP 5

325 X 738 = 239850

Fig. 1. Multiplication of two decimal numbers by Urdhva tiryakbhyam Sutra.

5 4 9 8

1

0

0

0

8

0 0

3

1

21

5

1

1

2

5

2

2

8

0

1

4

7

6

6

9

0

4

6

3

8

2

0

21 2 7 2 2 3 7

0122210

2

3

1

4

PreviousCarry

5498 X 2314 = 12722372

Fig. 2. Alternative way of multiplication by Urdhva tiryakbhyam Sutra.

branches of mathematics. The algorithms based on conven-tional mathematics can be simplified and even optimizedby the use of Vedic Sutras. The word ‘Vedic’ is derivedfrom the word ‘veda’ which means the store-house of allknowledge. Vedic mathematics is mainly based on 16 Sutras(or aphorisms) dealing with various branches of mathematicslike arithmetic, algebra, geometry etc. [10]. These Sutras alongwith their brief meanings are enlisted below alphabetically.

1) (Anurupye) Shunyamanyat – If one is in ratio, the otheris zero.

2) Chalana-Kalanabyham – Differences and Similarities.3) Ekadhikina Purvena – By one more than the previous

one.4) Ekanyunena Purvena – By one less than the previous

one.5) Gunakasamuchyah – The factors of the sum is equal to

the sum of the factors.

6) Gunitasamuchyah – The product of the sum is equal tothe sum of the product.

7) Nikhilam Navatashcaramam Dashatah – All from 9 andthe last from 10.

8) Paraavartya Yojayet – Transpose and adjust.9) Puranapuranabyham – By the completion or non-

completion.10) Sankalana-vyavakalanabhyam – By addition and by

subtraction.11) Shesanyankena Charamena – The remainders by the last

digit.12) Shunyam Saamyasamuccaye – When the sum is the

same that sum is zero.13) Sopaantyadvayamantyam – The ultimate and twice the

penultimate.14) Urdhva-tiryakbyham – Vertically and crosswise.15) Vyashtisamanstih – Part and Whole.16) Yaavadunam – Whatever the extent of its deficiency.

These methods and ideas can be directly applied totrigonometry, plain and spherical geometry, conics, calculus(both differential and integral), and applied mathematics ofvarious kinds. As mentioned earlier, all these Sutras werereconstructed from ancient Vedic texts early in the last cen-tury [10]. Many Sub-sutras were also discovered at the sametime which are not discussed here.

The beauty of Vedic mathematics lies in the fact that itreduces the otherwise cumbersome-looking calculations inconventional mathematics to a very simple ones. This is sobecause the Vedic formulae are claimed to be based on thenatural principles on which the human mind works. This is avery interesting field and presents some effective algorithmswhich can be applied to various branches of engineering suchas computing and digital signal processing [13]–[15].

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O O O O

O O O O

O O O O

O O O O

O O O O

O O O O

O O O O

O O O O

O O O O

O O O O

O O O O

O O O O

O O O O

O O O O

STEP 1 STEP 2

STEP 3 STEP 4

STEP 5 STEP 6

STEP 7

Fig. 3. Line diagram for multiplication of two 4-bit numbers.

III. THE PROPOSED VEDIC MULTIPLIER

The proposed Vedic multiplier is based on the Vedic multi-plication formulae (Sutra). These Sutra have been traditionallyused for the multiplication of two numbers in the decimalnumber system. In this paper, we apply the same ideas tothe binary number system to make the proposed algorithmcompatible with the digital hardware. Let us first discuss boththese Sutras in detail.

A. Urdhva Tiryakbhyam Sutra

Urdhva tiryakbhyam Sutra is a general multiplication for-mula applicable to all cases of multiplication. It literally means“Vertically and Crosswise”. To illustrate this multiplicationscheme, let us consider the multiplication of two decimalnumbers (325 × 728). Line diagram for the multiplicationis shown in Fig. 1. The digits on the two ends of the lineare multiplied and the result is added with the previous carry.When there are more lines in one step, all the results are addedto the previous carry. The least significant digit of the numberthus obtained acts as one of the result digits and the rest actas the carry for the next step. Initially the carry is taken to bezero.

An alternative method of multiplication using Urdhvatiryakbhyam Sutra is shown in Fig. 2. The numbers to bemultiplied are written on two consecutive sides of the squareas shown in the figure. The square is divided into rows andcolumns where each row/column corresponds to one of thedigit of either a multiplier or a multiplicand. Thus, each digitof the multiplier has a small box common to a digit of themultiplicand. These small boxes are partitioned into two halvesby the crosswise lines. Each digit of the multiplier is thenindependently multiplied with every digit of the multiplicandand the two-digit product is written in the common box. All thedigits lying on a crosswise dotted line are added to the previouscarry. The least significant digit of the obtained number actsas the result digit and the rest as the carry for the next step.Carry for the first step (i.e., the dotted line on the extremeright side) is taken to be zero.

Now we extend this Sutra to binary number system. Toillustrate the multiplication algorithm, let us consider themultiplication of two binary numbers a3a2a1a0 and b3b2b1b0.As the result of this multiplication would be more than 4 bits,we express it as ...r3r2r1r0. Line diagram for multiplicationof two 4-bit numbers is shown in Fig. 3 which is nothing butthe mapping of the Fig. 1 in binary system. For the sake ofsimplicity, each bit is represented by a circle. Least significantbit r0 is obtained by multiplying the least significant bits ofthe multiplicand and the multiplier. The process is followedaccording to the steps shown in Fig. 3. As in the last case, thedigits on the both sides of the line are multiplied and addedwith the carry from the previous step. This generates one ofthe bits of the result (rn) and a carry (say cn). This carry isadded in the next step and hence the process goes on. If morethan one lines are there in one step, all the results are addedto the previous carry. In each step, least significant bit acts asthe result bit and all the other bits act as carry. For example,if in some intermediate step, we get 110, then 0 will act asresult bit and 11 as the carry (referred to as cn in this text).It should be clearly noted that cn may be a multi-bit number.Thus we get the following expressions:

r0 = a0b0, (1)c1r1 = a1b0 + a0b1, (2)c2r2 = c1 + a2b0 + a1b1 + a0b2, (3)c3r3 = c2 + a3b0 + a2b1 + a1b2 + a0b3, (4)c4r4 = c3 + a3b1 + a2b2 + a1b3, (5)c5r5 = c4 + a3b2 + a2b3, (6)c6r6 = c5 + a3b3 (7)

with c6r6r5r4r3r2r1r0 being the final product. Hence this isthe general mathematical formula applicable to all cases ofmultiplication. The hardware realization of a 4-bit multiplierusing this Sutra is shown in Fig. 4. This hardware design isvery similar to that of the famous array multiplier where anarray of adders is requited to arrive at the final product. All thepartial products are calculated in parallel and the delay associ-ated is mainly the time taken by the carry to propagate throughthe adders which form the multiplication array. Clearly, thisis not an efficient algorithm for the multiplication of largenumbers as a lot of propagation delay is involved in suchcases. To deal with this problem, we now discuss NikhilamSutra which presents an efficient method of multiplying twolarge numbers.

B. Nikhilam Sutra

Nikhilam Sutra literally means “all from 9 and last from10”. Although it is applicable to all cases of multiplication, itis more efficient when the numbers involved are large. Since itfinds out the compliment of the large number from its nearestbase to perform the multiplication operation on it, larger theoriginal number, lesser the complexity of the multiplication.We first illustrate this Sutra by considering the multiplicationof two decimal numbers (96 × 93) where the chosen base

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ADDER ADDER ADDER ADDER ADDER ADDER

c r r r r r r r

(Output)

bb

aaaa

bb

0123

0123

6 6 5 4 3 2 1 0

Fig. 4. Hardware architecture of the Urdhva tiryakbhyam multiplier.

Nearest base = 100

Column 1

|

Result

2 digits

Common Difference

96 X 93

93 ( 100 − 93 )

96 ( 100 − 96 )

Column 2

Multiplication96 4

93 7

2889

Result = 96 X 93 = 8928

2 digits

Fig. 5. Multiplication using Nikhilam Sutra.

is 100 which is nearest to and greater than both these twonumbers.

As shown in Fig. 5, we write the multiplier and themultiplicand in two rows followed by the differences of eachof them from the chosen base, i.e., their compliments. Wecan now write two columns of numbers, one consisting of thenumbers to be multiplied (Column 1) and the other consistingof their compliments (Column 2). The product also consistsof two parts which are demarcated by a vertical line for thepurpose of illustration. The right hand side (RHS) of theproduct can be obtained by simply multiplying the numbersof the Column 2 (7×4 = 28). The left hand side (LHS) of theproduct can be found by cross subtracting the second numberof Column 2 from the first number of Column 1 or vice versa,i.e., 96− 7 = 89 or 93− 4 = 89. The final result is obtainedby concatenating RHS and LHS (Answer = 8928).

After this illustration, we now discuss the operational prin-ciple of Nikhilam Sutra by taking the case of multiplication of

two n–bit numbers x and y having compliments x = 10n−xand y = 10n − y respectively. The required product ‘p’ isdefined as:

p = xy, (8)

which can be reframed by adding and subtracting 102n +10n(x + y) to the right hand side as:

p = xy + 102n − 102n + 10n(x + y)− 10n(x + y). (9)

The above terms can be clubbed as follows:

p = {10n(x + y)− 102n}+ {102n − 10n(x + y) + xy}= 10n{(x + y)− 10n}+ {(10n − x)(10n − y)}

= 10n{x− y}+ {xy} = 10n{y − x}+ {xy}.(10)

From (10), the expressions of LHS and RHS can be deduced,which come out to be:

LHS = {x− y} = {y − x}, (11)

RHS = {xy}. (12)

Hence the multiplication of two n- bit numbers is reduced tothe multiplication of their compliments. To take full advantageof this reduction, it should be ensured that the numbersobtained after taking the compliments are lesser than theoriginal numbers. This condition is satisfied if both the orig-inal numbers are greater than 10n/2, i.e., x > 10n/2 andy > 10n/2. This is the reason why it is said that the NikhilamSutra is more efficient in the multiplication of large numbersthan the smaller ones.

An important point to note here is the number of digitsrequired in the RHS of the product. From (10), it is clear thatRHS should have n digits irrespective of number of digitsin the product xy. We illustrate this point by considering aspecial case of the multiplication of two 2- digit numbers inwhich RHS comes out to be a single digit (99×97). As shownin Fig. 6, the LHS of the product comes out to be 99 − 3 =

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99 X 97

Nearest base = 100

99 ( 100 − 99 )

97 ( 100 − 97 )

Column 1 Column 2

96

99 1

97 3

03|

Result

2 digits 2 digits

Result = 99 X 97 = 9603

Common Difference

Multiplication

Fig. 6. Multiplication using Nikhilam Sutra.

97 − 1 = 96 and the RHS comes out to be 3 × 1 = 3. Asn = 2 in this case, we need to append a leading zero to theRHS making it to be 03. The final result thus comes out to be9603. On the other hand, if the number of digits in RHS wouldhave been three, then the most significant digit would be thecarry digit to LHS. With this knowledge of the Vedic formulae,we now describe the developed multiplication algorithm.

C. The Proposed Algorithm

We recast the Nikhilam Sutra in binary arithmetic andfurther exploit certain basic properties of multiplication likeshifting to propose a new reduced-bit multiplication algorithm.The proposed algorithm is summarized in Table 1 for the caseof multiplying two 4-bit numbers. It is shown that the proposedalgorithm reduces 4×4-bit multiplication to a single 2×2-bitmultiplication operation. As a result, it reduces the delay forcarry propagation than any standard 4× 4-bit multiplier.

In the preprocessing stage, the input binary numbers areright shifted to remove the least significant consecutive zerobits. This decreases the computational time by reducing thenumber of bits in the multiplier and the multiplicand. Theeffect of the removed zero bits is efficiently incorporatedby shifting the final product to the left by equal number ofbits. As explained in Table 1, if both the multiplier and themultiplicand obtained after the preprocessing stage are 4-bitnumbers, Nikhilam Sutra is directly applied to reduce thenumbers to atmost 3-bits. If the numbers thus obtained areexactly 3-bit numbers, the sutra is again applied to reducethe multiplication to 2 × 2-bit which can be done with anystandard multiplier. In another case, if the numbers obtainedafter preprocessing stage are 4-bit and 3-bit numbers, thelarger number is expanded as a sum of binary 1000 and a3-bit number. This reduces the entire multiplication to a 3-bitmultiplication operation, followed by a shift and an additionoperation. A 3-bit multiplication is further reduced to a 2-bitmultiplication operation as explained in the previous case. Onthe other hand, if one of the numbers is 3-bit long and the otherone 2-bit, the larger number is expanded as a sum of binary100 and a 2-bit number. This reduces the entire multiplication

TABLE ITHE PROPOSED REDUCED-BIT MULTIPLICATION ALGORITHM

(a) InitializationPredefine: flag1 = flag2 = flag3 = flag4 = 0

(b) PreprocessingInput 4-bit binary numbers a and bn1 = Number of least significant consecutive zeros in an2 = Number of least significant consecutive zeros in bn = n1 + n2

a = Right shift a by n1

b = Right shift b by n2

(c) Processing1. IF (a > 1000 & b > 1000) THEN

a = 10000− a; b = 10000− b;flag1 = 1

2. IF (a > 100 & b > 1000) THEN b = b− 1000;[Solution = a× 1000 + b× a]flag2 = 1[If b > 100 & a > 1000, THEN a = a− 1000]

3. IF a > 100 & b > 100 THENa = 1000− a; b = 1000− b;flag3 = 1

4. IF (a > 10 & b > 100) THEN b = b− 100;[Solution = a× 100 + b× a]flag4 = 1[If b > 10 & a > 100, THEN a = a− 100]

5. IF (a = 1) THEN p = b | IF (b = 1) THEN p = aGOTO Step 7

6. Perform 2-bit multiplication: p = a× b7. IF (flag4 = 1) THEN

p = a× 100 + p; b = 100 + b8. IF (flag3 = 1) THEN

p = {LHS = 1000− (a + b) + carry of RHS}|{RHS = (3-bit)p};a = 1000 + a ; b = 1000 + b

9. IF (flag2 = 1) THENp = a× 1000 + p ; b = 1000 + b

10. IF (flag1 = 1) THENp = {LHS = 10000− (a + b) + carry of RHS}|{RHS = (4-bit)p}

11. p = Left shift p by n bits12. Return the product p13. END.

to a 2-bit multiplication, shift and an addition operation. Ifthe preprocessing stage outputs 3-bit or 2-bit numbers, theyare processed as explained earlier. Finally, another case mightarise in our processing stage where either of the numbersis 1. In that case, the output always equals to the othernumber irrespective of the value of the number obtained afterprocessing. The entire algorithm to be followed in the 4 × 4multiplication operation is presented in Table 1. Here, we haveexploited the basic operational principle of Nikhilam Sutra inconjunction with certain other basic arithmetic operations likedecomposition and bit shifting as explained above.

The proposed multiplier algorithm can further be extendedfor larger numbers with some modifications in the algorithmcondition checking steps accordingly.

IV. CONCLUSION

A new reduced-bit multiplication algorithm based on a for-mula of ancient Indian Vedic mathematics has been proposed.Both the Vedic multiplication formulae, Urdhva tiryakb-hyam and Nikhilam, have been investigated in detail. Urdhvatiryakbhyam, being general mathematical formula, is equallyapplicable to all cases of multiplication. A multiplier archi-tecture based on this Sutra has been developed and is seen

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to be similar to the popular array multiplier where an arrayof adders is required to arrive at the final product. Due toits structure, it suffers from a high carry propagation delayin case of multiplication of large numbers. This problem hasbeen solved by introducing Nikhilam Sutra which reduces themultiplication of two large numbers to the multiplication oftwo small numbers. The framework of the proposed algorithmis taken from this Sutra and is further optimized by use ofsome general arithmetic operations such as expansion and bit-shifting to take full advantage of bit-reduction in multiplica-tion. The computational efficiency of the algorithm has beenillustrated by reducing a general 4× 4-bit multiplication to asingle 2× 2-bit multiplication operation.

REFERENCES

[1] K. Hwang, Computer Arithmetic: Principles, Architecture And Design.New York: John Wiley & Sons, 1979.

[2] M. M. Mano, Computer System Architecture. Englewood Cliffs, NJ:Prentice-Hall, 1982.

[3] G.-K. Ma, F. J. Taylor, “Multiplier Policies for Digital Signal Process-ing”, IEEE ASSP Mag., vol. 7, no. 1, pp. 6–20, Jan. 1990.

[4] D. Goldberg, “Computer Arithmetic”, in Computer Architecture: AQuantitative Approach, J.L. Hennessy and D.A. Patterson ed., pp. A1-A66, San Mateo, CA: Morgan Kaufmann, 1990.

[5] A.D. Booth, “A Signed Binary Multiplication Technique”, Qrt. J. Mech.App. Math.,, vol. 4, no. 2, pp. 236–240, 1951.

[6] G. Goto. “High Speed Digital Parallel Multiplier.” U. S. Patent 5 465226, Nov. 7, 1995.

[7] L. Ciminiera and A. Valenzano, “Low Cost Serial Multiplier for HighSpeed Specialised Processors”, IEE Proc., vol. 135, no. 5, pp. 259–265,Sept. 1988.

[8] D. Ait-Boudaoud, M. K. Ibrahim and B. R. Hayes-Gill, “Novel PipelinedSerial/Parallel Multiplier”, Electron. Lett., vol. 26, no. 9, pp. 582–583,April 1990.

[9] R. Gnanasekran, “A Fast Serial-Parallel Binary Multiplier”, IEEE Trans.Comput., vol. 34, no. 8, pp. 741- 744, Aug. 1985.

[10] B. K. Tirtha, Vedic Mathematics. Delhi: Motilal Banarsidass Publishers,1965.

[11] P. D. Chidgupkar and M. T. Karad, “The Implementation of VedicAlgorithms in Digital Signal Processing”, Global J. of Engg. Edu., vol.8, no. 2, pp. 153–158, 2004.

[12] H. Thapliyal and M. B. Srinivas, “High Speed Efficient N × N BitParallel Hierarchical Overlay Multiplier Architecture Based on AncientIndian Vedic Mathematics”, Enformatika Trans., vol. 2, pp. 225-228,Dec. 2004.

[13] H. Thapliyal, R. V. Kamala and M. B. Srinivas, “RSA Encryp-tion/Decryption in Wireless Networks Using an Efficient High SpeedMultiplier”, in Proc. IEEE Int. Conf. Personal Wireless Comm. (ICPWC-2005), New Delhi, Jan. 2005, pp. 417–420.

[14] H. Thapliyal and M. B. Srinivas, “An Efficient Method of Elliptic CurveEncryption Using Ancient Indian Vedic Mathematics”, in Proc. IEEEMIDWEST Symp. Circuits. Systems, Cincinnati, Aug. 2005, pp. 826–829.

[15] H. Thapliyal, M. B. Srinivas and H. R. Arabnia , “Design And Analysisof a VLSI Based High Performance Low Power Parallel Square Archi-tecture”, in Proc. Int. Conf. Algo. Math. Comp. Sc., Las Vegas, June2005, pp. 72–76.

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I. INTRODUKSI

Pengganda digital adalah komponen inti dari semua prosesor sinyal digital (digital signal

processors/DSP) dan kecepatan DSP tersebut sangat ditentukan oleh kecepatan penggandanya.

Mereka sangat diperlukan dalam pelaksanaan sistem perhitungan menyadari banyaknya fungsi

penting seperti transformasi Fourier cepat (fast Fourier transforms/FFT) dan akumulasi

perkalian (multiply accumulate/MAC). Dua algoritma perkalian yang paling sering diikuti dalam

perangkat keras digital adalah algoritma perkalian larik dan algoritma perkalian Booth. Waktu

komputasi yang diambil oleh perkalian larik lebih sedikit karena produk parsial dihitung secara

independen dan paralel. Penundaan yang terkait dengan perkalian larik adalah banyaknya

waktu yang diambil oleh sinyal untuk menyebarkan melalui gerbang yang membentuk perkalian

larik. Perkalian Booth adalah salah satu algoritma perkalian penting lainnya. Larik booth besar

dibutuhkan untuk perkalian berkecepatan tinggi dan operasi eksponensial yang pada saat

tersebut membutuhkan penjumlahan parsial besar dan register pembawa parsial. Perkalian di

antara dua operandi n bit yang menggunakan sebuah perkalian rekaman booth radix-4

membutuhkan sekitar n=(2m) siklus jam untuk menghasilkan sebagian kecil dari produk akhir,

di mana m adalah jumlah tahap penambah perekam Booth. Dengan demikian, sebuah

penundaan penyebaran yang besar dikaitkan dengan kasus ini. Karena pentingnya perkalian

digital dalam DSP, itu selalu menjadi bidang penelitian aktif dan sejumlah algoritma perkalian

menarik telah dilaporkan dalam literatur.

II. MATEMATIKA VEDIC

Metode dan ide matematika Vedic dapat diaplikasikan secara langsung ke trigonometri,

geometri sederhana dan berbentuk bola, bentuk kerucut, kalkulus (diferensial maupun

integral), dan aplikasi matematika dari berbagai jenis. Seperti yang disebutkan di awal, semua

Sutra ini direkonstruksi dari teks-teks kuno Vedic di abad sebelumnya.

Kesempurnaan matematika Vedic terlihat dari fakta bahwa itu dapat mengubah

matematika konvensional menjadi sesuatu yang mudah. Ini terjadi karena formula Vedic diklaim

didasari atas prinsip alami bagaimana pikiran manusia bekerja. Ini merupakan sebuah bidang

yang sangat menarik dan memberikan banyak algoritma efektif yang dapat diaplikasikan ke

banyak cabang permesinan seperti menghitung dan memproses sinyal digital.

III. USULAN PENGALI VEDIC

Pengali Vedic yang diusulkan didasari atas formula perkalian Vedic (Sutra). Sutra tersebut

telah digunakan secara tradisional untuk perkalian dua angka dalam sistem angka desimal.

Dalam jurnal tersebut, mereka mengaplikasikan ide-ide yang sama dalam sistem bilangan biner

untuk membuat algoritma yang diusulkan kompatibel dengan perangkat keras digital.

Nikhilam Sutra dituangkan kembali dalam aritmetika biner dan dieksploitasi lebih dalam

untuk mengambil properti dasar dari perkalian yang bergeser untuk mengusulkan sebuah

algoritma perkalian bit baru. Algoritma yang diusulkan mengurangi perkalian 4x4 bit menjadi

sebuah operasi perkalian 2x2. Sebagai hasilnya, hal itu mengurangi penundaan penyebaran

pembawa daripada perkalian 4x4 bit standar yang lain.

Dalam tahap preprocessing, bilangan biner yang dimasukkan digeser ke kanan untuk

menghilangkan bit nol konsekutif signifikan yang paling sedikit. Ini mengurangi waktu

penghitungan dengan mengurangi jumlah bit pengali. Hal ini berakibat penyatuan secara efisien

dengan menggeser hasil akhir ke kiri oleh angka bit yang sama. Kedua pengali dan perkalian

yang diperoleh setelah tahap preprocessing adalah bilangan 4 bit. Bilangan yang diperoleh

adalah bilangan 3 bit tepat, sutra diaplikasikan kembali untuk mengurangi bilangan menjadi 3

bit. Ini akan mengurangi seluruh perkalian ke operasi perkalian 3 bit, diikuti dengan sebuah

penggeseran dan operasi penambahan. Perkalian 3 bit dikurangi lebih jauh lagi menjadi operasi

perkalian 2 bit yang dijelaskan dalam kasus sebelumnya. Di sisi lain, jika salah satu bilangan

memiliki 3 bit dan yang lainnya memiliki 2 bit, angka yang terbesar akan diperluas menjadi

jumlah biner dari 100 dan sebuah angka 2 bit. Ini mengurangi seluruh perkalian menjadi sebuah

perkalian 2 bit, menggeser dan sebuah operasi penambahan. Jika tahap preprocessing

mengeluarkan hasil bilangan 3 bit atau 2 bit, mereka akan diproses seperti penjelasan

sebelumnya. Akhirnya, keadaan lain yang mungkin muncul dalam tahap preprocessing ini di

mana salah satu bilangan adalah 1. Di sini, hasil keluaran selalu sama dengan bilangan tidak

respektif lainnya dari hasil bilangan yang diperoleh setelah pemrosesan. Di sini, kita telah

mengeksploitasi dengan operasi aritmetika dasar lain seperti dekomposisi dan penggeseran bit

seperti yang dijelaskan di atas.

Algoritma pengali yang diusulkan dapat diperluas lebih jauh untuk angka-angka yang

lebih besar dengan beberapa modifikasi dalam kondisi algoritma untuk mengecek langkah-

langkah yang sesuai dengannya.

IV. KESIMPULAN

Sebuah algoritma baru perkalian bit yang dikurangi didasari atas formula matematika

Vedic India kuno telah diusulkan. Formula perkalian Vedic maupun Urdhva tiryakbhyam dan

Nikhilam telah diinvestigasi secara detail. Urdhva tiryakbhyam, formula matematika umum saat

ini, dapat diaplikasikan secara sama dalam semua soal perkalian. Sebuah arsitektur perkalian

yang didasari atas Sutra ini telah dikembangkan dan terlihat mirip dengan perkalian larik

populer di mana sebuah larik penambah dibutuhkan untuk dicapai di hasil akhir. Mengacu pada

strukturnya, terdapat kekurangan pada sebuah penundaan penyebaran pembawa yang tinggi

dalam hal perkalian angka-angka besar. Masalah ini dapat diselesaikan dengan mengenalkan

Nikhilam Sutra yang mengurangi perkalian dua angka-angka besar ke dalam perkalian dua

angka-angka kecil. Kerangka algoritma yang diusulkan diambil dari Sutra ini dan dioptimalkan

lebih jauh dengan menggunakan beberapa operasi aritmetika umum seperti perluasan dan

penggeseran bit untuk menghasilkan keuntungan penuh dari pengurangan bit dan perkalian.

Efisiensi penghitungan algoritma ini telah diilustrasikan dengan mengurangi perkalian 4x4 bit

yang umum ke operasi perkalian 2x2 bit tunggal.