section 4: sequential circuits - university of waterloomsachdev/ece223/seq.pdf · section 4:...

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Department of Electrical Engineering, University of Waterloo 1/59

Section 4: Sequential Circuitsn Major Topics

¦ Types of sequential circuits¦ Flip-flops¦ Analysis of clocked sequential circuits¦ Moore and Mealy machines¦ Design of clocked sequential circuits¦ State transition design method¦ State reductions¦ Counters¦ Shift registers


Introductionn Combinational Circuit

¦ Output = f ( present inputs)

n Sequential circuit¦ Output = f ( present and past inputs)

; Circuit “remembers”past history; Must contain “memory” elements; Time is variable that must be considered

¦ Memory elements hold the present state of the system¦ The past history is recorded in the state¦ As time progresses, the system moves from state to state

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n General sequential circuit model

¦ Outputs are functions of inputs and present state¦ Next state is function of inputs and present state

inputs k n outputs

present state next state

combinationalcircuit

memorym m

state


n Choosing the set of permissible states is a crucial part of sequential circuit design

n Choice of states has three issues:

¦ Identifying the number of unique states

¦ Identifying rules for transition from state to state

¦ Finding a coding for the state that simplifies the circuit (usually fairly obvious for small systems)

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Types of Sequential Circuits

n Fundamental Mode (asynchronous)

¦ Short-term memory consists of signal propagation delay (gate delays) in the combinational circuit

¦ Frequently memory is not distinct¦ Fastest possible circuit¦ Combinational circuit with feedback

; Feedback can cause instability; Difficult to design, analyse, debug

¦ Don’t use them unless forced to


n Pulse or synchronous Mode

¦ memory is provided by flip-flops

¦ Circuit only changes state in response to a “pulse” input

¦ Unless pulse rate is too high, circuit is always stable

¦ Synchronization is achieved through clock pulses; Circuit behavior depends only on the inputs at the discrete

times at which clock pulse occurs

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n In fundamental mode one must consider the differences in delay along various paths, and the effect of simultaneously input changes

n With several different pulse inputs, in the worst case the circuit must be designed as a fundamental mode circuit

n However, in clocked sequential circuits one is only concerned with

¦ Correct combinational circuit¦ Clock period greater than the maximum propagation delay through

the combinational circuit


Flip - Flopsn A flip-flop (FF) is the basic memory element of pulse mode circuitn A flip-flop stores one bit of informationn RS (Reset/Set) Latch (Flip-flop)*

(unlocked version)

n Two states :- Set : Q = 1, Q´ = 0 ; Reset: Q = 0, Q´ = 1

R

R´

S´

S

Q

Q

Q´

Q´

S Q

R Q´

S QR Q´

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n * Some texts use the term latch and flip-flop interchangeably

n Others restrict¦ flip-flop to elements with a pulse (clock) input,¦ and latches to elements without a pulse input, ¦ although a latch may have an enable input


n Truth Table (Characteristic Table)

n If R = S = 1 then Q = Q´ = 0 (NOR) and Q = Q´ = 1 (NAND) If R and S go to 0 almost simultaneously then the circuit can

; (1) Fall into either state; (2) Oscillate, or; (3) Remain at an indeterminate value for an arbitrarily long

time, i.e. metastable state

R S Qn Qn+1

0 0 0 00 0 1 10 1 0 10 1 1 11 0 0 01 0 1 01 1 0 -1 1 1 -

Qn = present outputQn+1 = output after input applied

Output undefinedOutput undefined

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n A) (Clocked) RS FF

n Characteristic table as before¦ Qn - output before clock pulse¦ Qn+1 - output after clock pulse

n Characteristic equation

¦ Qn+1 = S + R´Qn

with constraint: RS = 0

R

S

Q

Q´

S Q

R Q´CP CP

CP = Clock Pulse

SR Qn

00 01 11 10

0 X 1

1 1 X 1

Qn+1


n B) Clock RS FF with asynchronous Reset and SetDirect Clear and Preset

¦ Asynchronous Reset and Set controls; Used for circuit initialization

clearl

R

S

Q

Q´CP

l

l

preset

l

l

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n C) D (data) flip-flop

¦ Characteristic Table

¦ Qn+1 = Dcopies input to output on clock pulse

D Q

Q´

DQ

Q´CP CP

D Qn Qn+1

0 0 00 1 01 0 11 1 1


n D) T (toggle) flip-flop

¦ Qn+1 = T ⊕ Qn

changes state on clock pulse when T = 1

T Qn Qn+1

0 0 00 1 11 0 11 1 0

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n E) JK flip-flop¦ Eliminate the indeterminate state of the RS flip-flop

J = setK = clear

JK simultaneously = toggle

characteristic equationQn+1 = JQ´n + K´Qn

J K Qn Qn+1

0 0 0 00 0 1 10 1 0 00 1 1 01 0 0 11 0 1 11 1 0 11 1 1 0

JK Qn

00 01 11 10

0 1 1

1 1 1

Qn+1


Flip - Flop Triggeringn To prevent repeated triggering of a JK flip-flop when J=K=1, clock

pulse width must be less than propagation delay through flip-flop

n To avoid clock pulse width problems, prefer to trigger on edges of CP

n Two approaches; Master-slave flip-flop; Edge triggered flip-flop

CP

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Master - Slave Flip - Flopn Basic idea (RS flip-flop)

CP = 1 → master is affectedCP = 0 → slave is affected

S Q

Q´

CP

S Q

R Q´

Y

l

Y´R Q´

S Q

R

master slave

CP

Y

Q


n Master- Slave JK Flip- Flop

Master

l

J

K

CP

ll

Q

Q´l

l

ll

l

l

Slave

CP

master affected slave affected

(JK inputs ignored) (slave is an RS flip-flop)

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n J - K master- slave flip-flops are susceptible to noise on control lines while clock is high

¦ Would prefer a system where the interval for noise/glitch susceptibility is small

CP

J

K

Y

Q

noise pulse


Edge Triggered Flip - Flops

n Basic ideal is to make the intervals where flip-flop is susceptible to noise as small as possible¦ Example- D- flip-flop

CP

output changes here(positive edge triggered)

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Edge Triggered D Flip- Flop

n Changes state (if Q ≠ D) when CP makes a positive transition (0→ 1)

l

l

l

l

l

l

Q

Q´R´

S´

A

BD

CP


n in circuit, D must be present for before CP → 1 tsetup = delay from D to A output

n D must stay constant for thold after CP → 1 thold is delay throughS´and R´ gates

n Note: - All flips-flops have a tsetup and thold constraints- If the constraints are not met, the flip-flop may go into

metastable state.

CP

D

tsetup

thold

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Analysis of Clocked Sequential Circuits

n Analysis Procedure

¦ Circuit equations¦ Excitation table¦ (Next state) Transition Table and State equations¦ State diagram¦ Timing chart

SYNTHESIS IS JUST REVERSE !


Analysis Example

n A ( t + 1) = A ( t ) x ( t ) + B ( t ) x ( t ) n B ( t + 1) = A' ( t ) x ( t )

B´CP

y

Q´

D A•

A´•

•

•

•

B••

•

•

Q

Q´

QD

x

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n Alternatively¦ A ( t + 1 ) = Ax + Bx¦ B ( t + 1 ) = A' x

n Similarly¦ y ( t ) = [ A ( t ) + B ( t ) ] x' ( t )¦ y = ( A + B ) x'


State TablePresentState

Input NextState

Output

A B x A B y

0 0 0 0 0 00 0 1 0 1 00 1 0 0 0 10 1 1 1 1 01 0 0 0 0 11 0 1 1 0 01 1 0 0 0 11 1 1 1 0 0

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State Table Continued

Next State Output

Present State x = 0 x = 1 x = 0 x = 1

AB AB AB y y

00 00 01 0 001 00 11 1 010 00 10 1 011 00 10 1 0


Flip - Flop Characteristic TablesJK Flip - Flop

J K Q ( t + 1)0 0 Q ( t ) No change0 1 0 Reset1 0 1 Set1 1 Q' ( t ) Complement

RS Flip - FlopS R Q ( t + 1)0 0 Q ( t ) No change0 1 0 Reset1 0 1 Set1 1 ? Unpredictabe

D – Flip - Flop

D Q ( t + 1 )

0 0 Reset

1 1 Set

T – Flip - Flop

T Q ( t + 1 )

0 Q ( t ) No Change

1 Q' ( t ) Complement

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Moore and Mealy Machinesn Mealy Machine

¦ Output are pulses dependent upon the total input state; total input state ≡ inputs + internal state

101/10q1

q2

Internal stateinputs

outputs


n Moore Machine¦ Outputs are levels dependent upon only the present internal state

¦ try to use this form when designing clocked circuits

outputs

q1/11

q2/10

101

internal stateinputs

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Flip - Flop Excitation TablesQ ( t ) Q ( t + 1 ) S R 0 0 0 X 0 1 1 0 1 0 0 1 1 1 X 0

Q ( t ) Q ( t + 1 ) J K 0 0 0 X 0 1 1 X 1 0 X 1 1 1 X 0

Q ( t ) Q ( t + 1 ) D 0 0 0 0 1 1 1 0 0 1 1 1

Q ( t ) Q ( t + 1 ) T 0 0 0 0 1 1 1 0 1 1 1 0

(c) D

(a) RS (b) JK

(d) T


Design Proceduren The (classical) approach to clocked sequential circuit design

follows the steps:¦ 1) words or timing diagram¦ 2) state transition diagram¦ 3) state table¦ 4) reduced state table (if possible)¦ 5) assign binary values to states (state variable assignment)¦ 6) develop transition table¦ 7) select flip-flop type¦ 8) excitation table and output table¦ 9) simplified equations¦ 10) circuit diagram

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Example

Next State

Present State x = 0 x = 1

A B A B A B0 0 0 0 0 10 1 1 0 0 11 0 1 0 1 11 1 1 1 0 0

00

1101

10

0

0

0

0

1

11


Excitation TableInputs of Combinational

CircuitOutputs of

Combinational CircuitPresent

State InputNextState Flip- Flop Inputs

A B x A B JA KA JB KB

0 0 0 0 0 0 X 0 X0 0 1 0 1 0 X 1 X

0 1 0 1 0 1 X X 1

0 1 1 0 1 0 X X 0

1 0 0 1 0 X 0 0 X

1 0 1 1 1 X 0 1 X

1 1 0 1 1 X 0 X 0

1 1 1 0 0 X 1 X 110

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Block Diagram

Q' Q'K KJ J

x

CP

QQBB'A' A

A'AB'

B

Combinationalcircuit

JBJAKA KBExternaloutputs (none)

External inputs


Logic DiagramBx B

A 00 01 11 10

0 1

A 1 X X X X

xJA = Bx'

X X X X

1

KA = Bx

1 X X

1 X X

JB = x

X X 1

X X 1

KB = ( A ⊕ x )'

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Logic Diagram Continued

Q'K J

Q

A

Q'K J

Q

B

CP

x


State Reductionsn Redundant states can be generated in going from a verbal

description to the state diagramn “Two states are equivalent if, for each member of the set of

inputs, they give exactly the same output and send the circuit to the same state or to an equivalent state” M.M. Mano

n When two states are equivalent, one of them may be removed¦ Example

Next statePresentstate x = 0 x = 1

Output

A D C 1B A E 0C D A 1D B D 0E C B 0

F

¦ A and C are equivalent, B and E are equivalent

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n Reduced tableNext statePresent

state x = 0 x = 1output

(A,C) P D P 1(B,E) Q P Q 0

D Q D 0

A/1 C/1 P/1

D/0 D/0

Q/0E/0B/0

0

0 0

0

0

0

0 0

1

1

1

1

1

1

1

1


Registersn A register is a bank of D flip-flops

(0 → clear )

(negative edge triggered)

(load- so can disable circuit without performing logic on clock pulse)

(direct ) clear

o

o

A1

AnIn

I1

CPload

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n RS version

n D version

¦ Note feedback to maintain Q value when load = 0

load

o

o

o

•

•

clear

I iAiS Q

R

CP

load

I i

o

AiD Q

o

•

•

clear

CP

o o

•


n Registers + Logic þ Sequential Circuits

n Use of ROM

¦ N.B. If system is a Moore Machine, try to take the outputs directly from registers if possible (both of above cases)

registers (present state)

km

n

n

next state

outputsinputsCP

could be PLAn

registers (present state)

km

nnext state

outputsinputsCP

could be PLA

2(n +m) x(n + k ) ROM

Combinational circuit

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Shift Registers

n Above is a sample shift register¦ usually has an asynchronous clear input¦ used in serial to word conversions

; many can be read in parallel; many can be loaded in parallel

•

D Q

•

D Q

•

D Q

•

D Qserial in serial out

CP


Bi-directional Shift Register with Parallel Load

(parallel outputs)

I4 I3 I2 I1

A1A2A3A4

(parallel inputs)

Ai

0123 21 20

MUX D Q

CPclear

Iis1 s0

•

Ai+1Ai-1

o

s1s0 function0 0 no change0 1 shift right1 0 shift left1 1 load

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Special Sequential Circuitsn 4.7.1 Serial Adder

¦ This circuit was developed on slide number 61 as the Carry Save Adder (CSA)

¦ The clock pulse CP; records the carry; advances inputs and outputs

CP clear

z D Q

o

S

C

xy full

adder

serial output

carry

serial input

least significant bits first


Ripple Counter (Asynchronous Counter)

n Flip-flops do not change state simultaneously¦ Consider case where count pulse is the clock pulse:

n Note: In asynchronous mode clock skew will occur at each stage

o

•

o

•

o

•

o

( negative edge triggered flip-flops) 1 1 1 1 1 1 1 1

K K K K JJJJ

QQQQ

A1A2A3A4

count pulse

flip-flop setting delay

CP

A1

A2

A3

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Synchronous Counters

n This is a general version of counters.

control logic(combinational circuit)

o

Q

K J

A4

o

Q

K J

A3

o

Q

K J

A2

o

Q

K J

A1

• • •

••••


Binary Counter (Iterative Design)n Counters are commonly designed using an iterative cell

approach:

n cell changes state if all cells to the right are 1 and E = 1

clear CP

o

o

Ai - 1 … A1E••

•

K J

QQ'

Ai

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n A four bit counter has the form:

o

Q

K J

A4

oo

Q

K J

A3 A2

•

•

oo

Q

K J

•

•

o

A1

o

Q

K J

•

•

o

• • •

••••••

E - count enable

E

C - (asynchronous) clear

CPC


n max. clock rate <¦ where

; Tdelay = delay through AND gate chain; Tsettling = flip-flop settling time; Tsetup = flip-flop set up time

flip-flop setting delay

E

CP

A1

A2

A3

1Tdelay+ Tsettling + Tsetup

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Binary Up-Down Countern The (iterative) cell has the form:

¦ U = 1 ⇒ count up and D = 1 ⇒ count down¦ U • D ≠ 1

o

Q

K Jo

•

•Ai

Q'

Ai’ -1 . . . A1 ’ D

AI -1 . . . A1 U

clear CP


Up Counter with Parallel Load

n N.B. This is iterative design¦ non-iterative design is faster

o

Q

K Jo

•

•Ai

I i

clear CP o

•

• •

•

•

C = Ai -1 . . . A1EL’

C

L

LE Function

1X load01 count00 no change

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Modulo-N Countern Suppose we want 1,2,3,4,5,6,7,8,9 (mod-9 counter)

n Notes:¦ any initial value¦ any final value¦ self correcting

E

I4

A4

I3

A3 A2 A1

I2 I1

L

CPclear

CP1countreset

••

10 0 0

parallel loadup counter


Timing Signal Generationn What is needed?

T0

CP

T1

T2

T3

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n 2n states required¦ n flip-flops¦ n x 2n decoder

Counter and Decoder

T0

T1

T2

T3

CP 2 2 x 4

decoder

2- bitcounter

enable


Circular Shift Register ( Ring Counter )

n circuit normally has an enable inputn requires a method of loading initial pattern (1 0 0 0 )n 2n flip-flops

•

D Q

•

D Q

•

D Q

•

D Q •

CP

T0 T1 T2 T3

•••1 1 0 0

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n If the circulating pattern is made 11 1 0 0 symmetric signals are generated

T0T1

T2

T3


Johnson (Switched-Tail) Countern The number of states in a circular shaft register can be doubled

by connecting the complement of the last stage as the input to the first.

¦ Normally have enable input¦ Also needs clear (for resetting)¦ Self starting (after clear)

•

D Q

•

D Q D Q

CP

A B C

••

Q'

•

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n 3 flip-flops, 6 AND gates ⇒ 6 timing signalsn N flip-flops, 2N AND gates ⇒ 2N timing signalsn Drawback: Locks into invalid sequences (Can be fixed)

Sequencenumber

A B C Timingsignal

1 0 0 0 A'C' (extreme 0s )2 1 0 0 AB' ( 1 0 )3 1 1 0 BC' ( 1 0 )4 1 1 1 AC (extreme 1s )

5 0 1 1 A'B ( 0 1 )6 0 0 1 B'C ( 0 1 )

0 1 01 0 10 1 0

etc.

section 4: sequential circuits - university of waterloomsachdev/ece223/seq.pdf · section 4:...

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