section 7

77Changing Wafer Size

and the Move to 300mm

As discussed in Chapter 1, the industryÕsability to increase productivity by 25-30 per-cent per year is the combined result of wafersize transitions, shrinking device geometries,equipment productivity improvements, andincremental yield improvements. Wafer sizetransitions historically account for 4 percentof the 25-30 percent productivity gain.

Companies make wafer size transitionsbecause of the overall cost benefits resultingfrom the larger number of dice per wafer,thereby using the same number of processsteps to produce more dice. Based on histor-ical trends, peak demand for 200mm waferswill be reached around 2003, as shown inFigure 7-1. In addition, this SEMATECHstudy[1] indicates that each wafer sizeremains in production for approximately 24years Ð allowing companies sufficient time torecoup investments in the technology.

This lifecycle perspective can be used as aguide as the industry makes transitions tolarger wafers. By the year 2000, the first pro-cessing on 300mm (12 inch) wafers is antici-pated. 300mm wafers will accommodateroughly twice as many dice per wafer as200mm wafers. Driving forces for all wafersize transitions include the factors of ever-increasing die size and increasing numbers

of integrated functions per chip. Less obvi-ous, yet no less important factors such asincreasing global competition, 200mminstalled base and market conditions areinfluencing the rapidity with which 300mmsilicon wafers will become manufacturing-worthy and cost effective. Today, while man-ufacturers in the silicon world are making150 to 200mm transitions and evaluating300mm processing, many GaAs manufactur-ers are undergoing or considering transitionsto 150mm processing from 100mm. The rela-tive wafer sizes are shown in Figure 7-2.

Upgrading to a New Wafer Size

Wafer size increases can also be viewed interms of percentage increase in wafer area, asshown in Figure 7-3. Interestingly, the movefrom 100mm (4 inch) wafers to 150mm (6inch) wafers increased the silicon area by 125percent Ñ the same relative gain that will berealized when semiconductor companiesmake the transition from todayÕs 200mm (8inch) wafers to 300mm (12 inch). Beyond300mm, the same gain requires a jump to450mm wafers. Trends indicate that wafersize transitions industry-wide have typicallyenabled a 4 percent per year productivityimprovement, and the transition to 300mmshould provide between 2 and 4 percent peryear lower IC cost/cm2.[1]

INTEGRATED CIRCUIT ENGINEERING CORPORATION 7-1

7 Changing Wafer Size and the Move to 300mm

Changing Wafer Size and the Move to 300mm

INTEGRATED CIRCUIT ENGINEERING CORPORATION7-2

Figure 7-4 illustrates the number of dice perwafer based on wafer size and die size, whileFigure 7-5 can be used for more precise cal-culation of the maximum number of dice perwafer. Unfortunately, due to equipment pro-ductivity and price increases for larger waferprocessing tools, the cost savings resultingfrom wafer size transitions may not scalewith these die per wafer calculations. Forinstance, 200mm wafers offer nearly twicethe area of 150mm wafers (1.78X), but manyearly adopters of 200mm technology arguethat this transition did not result in twice as

many chips produced for the same manufac-turing costs. In fact, if the cost of owning andoperating 200mm equipment is twice as highas the 150mm equipment, then the manufac-turing cost (per square centimeter of silicon)is the same. In this case, the cost savings onlyresults from the need for less than twice asmany pieces of equipment to process thelarger wafers. For these reasons, the questionof whether or not a fab can cost-effectivelymake wafer size transitions depends greatlyon the utilization and efficiency of the waferprocessing equipment.

Are

a D

eman

d/Y

ear

(106

in.2

)

Year

'60 '65 '70 '75 '80 '85 '90 '95 '00 '05 '10 '15 '20 '25

100,000

10,000

1,000

100

10

1

0

Source: VLSI Research, SEMATECH, I300I 22624

1997

Ironman

Pilot Line

Total Wafer Area Trend Model

1976-2025: 10% CAGR

100%

33%

10%

38/51mm75/100mm

125/150mm

200mm

300mm

450mm

Figure 7-1. Lifecycles of Different Wafer Sizes



Evaluating the Cost Benefits of 150 to200mm Transitions

In making wafer size transitions, generallyspeaking, only a percentage of tools can beused to process subsequent wafer sizes.Interestingly enough, many fabs and equip-ment manufacturers anticipated makingsmall modification to equipment whenmaking transitions from 100mm to 125mmor 125mm to 150mm wafer processing. Inreality, only 40-50 percent of the systemswere transferable; equipment needed to beredesigned, and usually new equipment setswere needed. When making transitions from150mm to 200mm wafer processing, only ahandful of systems can be used on both sizes.It is anticipated that none of the 200mm pro-cessing systems will be used to processupcoming 300mm wafers.

As users might expect, transitions in wafersize require complete evaluations of costfactor differences for each different processtool in the fab. A simplified cost-of-owner-ship (COO) study of 150mm versus 200mmwet benches performed by Intel[2] revealedthat the top four contributors to COO are sig-nificantly different for 200mm and 150mmwet cleaning equipment (Figure 7-6).Deionized (DI) water costs, capital costs, con-sumable costs and facilities costs dominated200mm benches while capital, facilities, mon-itor wafer, and DI water costs dominated for150mm systems. Most significantly, DI water,in going from 150 to 200mm wafer process-ing, jumps from being the fourth highest costfactor to the first. This difference is primarilydue to the tripling of flow rates needed toachieve equivalent rinsing of the 200mmbatch. Interestingly, while the test wafer costrose from $35 to $135, its impact on COO less-ened because the monitoring frequencystayed constant between the two wafer sizes.

22664Source: ICE

100mm

125mm

150mm

200mm

300mm

Figure 7-2. Relative Difference in Wafer Sizes



0 50 100 150 200

��

��

��

��

��

��

��

��

��

125

56

78

125

78

156

125

56

Waf

er D

iam

eter

Tra

nsi

tio

n

100mm → 125mm

100mm → 150mm

125mm → 200mm

150mm → 200mm

200mm → 250mm

Percent Increase

Source: ICE 18603A

250mm → 300mm

200mm → 300mm

300mm → 400mm

300mm → 450mm

44

Figure 7-3. Wafer Area Increases (Percent)

20191Source: ICE

Dic

e P

er W

afer

Die Size (mm2)

10,000

1,000

100

10

110 200 400 600 800 1,000 1,200 1,400

300 mm

200 mm

150 mm

125 mm

100 mm

Figure 7-4. Dice Per Wafer Based on Die Size and Wafer Size



DIE AREA

mil x1,000

2

mm2 3-INCH 100mm 125mm 150mm 200mm

90.096.1

102.4108.9115.6122.5129.6136.9144.4152.1160.0168.1176.4184.9193.6202.5211.6220.9230.4240.1250.0260.1270.4280.9291.6302.5313.6324.9336.4348.1360.0372.1384.4396.9409.6422.5435.6448.9462.4476.1490.0504.1518.4532.9547.6562.5577.6592.9608.4624.1640.0656.1672.4688.9705.6722.5739.6756.9774.4792.1810.0828.1846.4864.9883.6902.5921.6940.9960.4980.1

1,000.0

58.162.066.170.374.679.083.688.393.298.1

103.2108.5113.8119.3124.9130.6136.5142.5148.6154.9161.3167.8174.5181.2188.1195.2202.3209.6217.0224.6232.3240.1248.0256.1264.3272.6281.0289.6298.3307.2316.1325.2334.5343.8353.3362.9372.6382.5392.5402.6412.9423.3433.8444.5455.2466.1477.2488.3499.6511.0522.6534.3546.1558.0570.1582.3594.6607.0619.6632.3645.2

mils mm

300310320330340350360370380390400410420430440450460470480490500510520530540550560570580590600610620630640650660670680690700710720730740750760770780790800810820830840850860870880890900910920930940950960970980990

1,000

7.67.98.18.48.68.99.19.49.79.9

10.210.410.710.911.211.411.711.912.212.412.713.013.213.513.714.014.214.514.715.015.215.515.716.016.316.516.817.017.317.517.818.018.318.518.819.019.319.619.820.120.320.620.821.121.321.621.822.122.422.622.923.123.423.623.924.124.424.624.925.125.4

DIE SIZE**AREA

5244444032323232322424242424161616161612121212121212121212121212444444444444444444444444444444444444

———

9688807676686052525252524444403232323232323224242424242424161616161616161212121212121212121212121212121212444444 444444444444

15614814012012011211296968880807676686860525252525252444440403232323232323232242424242424242424161616161616161616121212121212121212121212121212121212

2402242081921881641561481481401201201121121049696888880767676686868605252525252525244444440403232323232323232323224242424242424242424241616161616161616161612

CANDIDATE NUMBER OF WHOLE DICE

44842439237634033230829226825624824021620820818818818016415614814814813212012012011211211210496968888888080767676686868686060525252525252525252444444444040403232323232323232

Corner of die at center of full radius wafer.3mm band around edge of wafer not used.Size after die separation, 3 mil saw kerf.

*

**22673Source: ICE

300mm

1,0601,012

936880820780732688656616600556540508492460440432392392376356340332316308292284268256256248240224216208208200188188180180164164156156148148148148132132120120120120112112112112112104969696888888888080

Figure 7-5. Die Size Versus Die Count*



Studies like this and others can be used totarget key areas for cost reduction in 200mmfabs. In this example, the authors cited possi-ble reductions in bath volume through cassetteor cassette-less processing (which would bringDI water and consumables costs down), or theuse of hot DI water or sonic energy rinses toreduce rinse times. Operating costs can bereduced by optimizing the system for higherthroughput and utilization. For instance, anincrease of 10 wafers per hour throughput or 5percent utilization would reduce the 200mmCOO by 13 to 15 cents. Initial cost of the wetbench would have to be reduced by $500,000to have an equivalent impact.[2] Many of thecurrent 200mm wafer cleaning systems featurereduced use of DI water and chemicals,smaller tool footprint, increased system avail-ability, and higher throughputs.

In summary, the factor affecting cost savingsthe most in wafer size transitions is the rela-tive cost-effectiveness of the equipment usedto process the two wafer sizes. Users makingthe transition must weigh the added cost ofnext-generation equipment and possiblylower throughput and productivity (espe-cially with single-wafer systems) versus the

long-term benefits of more dice per wafer,assuming that the same or better yields canbe realized on the larger wafers.Understanding such differences, it comes asno surprise to learn that the transition from150mm to 200mm processing occurred theslowest of any transition, requiring 5 years toreach 100 million square inches of produc-tion instead of 3 years in the case of 150, 125and 100mm wafers.[3] 200mm processingtools first became available in the late 1980s,and approximately a decade later about athird of all wafers shipped are 200mm.

The Promise of 300mm Wafers

As of early 1997, seven IC manufacturerswere planning 300mm pilot line operationsfor 1998, and anticipating production ramp-up in 1999. These firms include:

¥ Hitachi¥ IBM¥ Intel¥ Motorola¥ NEC¥ Samsung¥ Texas Instruments

Source: Microcontamination 20186

200mm Wet Bench Equipment 150mm Wet Bench Equipment

Others15%

Others18%DI Water

32%

DI Water13%

Capital23%

Capital31%

Consumables16%

Facilities20%

Facilities14%

Monitors18%

Figure 7-6. Components of Operating Costs of 200mm and 150mm Wet Benches



Beyond these early indications, TI hasannounced its intention to install a 300mmline at its plant in Avezzano, Italy; Sony plansto build a line in Nagasaki Prefecture, Japan;and Intel, Mitsubishi, Toshiba and Siemensalso intend to build pilot line 300mm fabs inthe 1998-1999 time frame. SEMI estimates thatlow and medium volume fabs will emerge bythe year 2000 and high volume 300mm fabs(starting 20,000 wafer per month) will soonfollow (see Figure 7-7). The first devices pro-duced on these wafers will probably be high-margin advanced logic chips (DSPs, ASICs,FPGAs, PLDs) and microprocessors, probably0.18µm generation devices, while memorymanufacturers are expected to trail in 300mmadoption due to low margins experiencedover the last year and a half.

Semiconductor manufacturers have unques-tionably stated that 300mm development willnot be performed solely by the IC manufac-turers, as they were in previous generationswith Intel enabling the transition to 150mmand IBM managing the transition to 200mm.In the case of 300mm, the technical challengesare so involved that they require an unprece-dented level of industry-wide cooperation.

Many sources estimate the industryÕs overallcost of making the transition to 300mmwafers at between $15 and $20 billion. Thisincludes development of the tools and tech-niques for making the wafers, developmentcosts of all the wafer processing and han-dling tools, all computer integrated manu-facturing (CIM) software, factoryautomation tools, and cleanroom technology.Development costs for 300 or 400mm equip-ment are estimated by Applied Materials tobe at least 1.4 to 1.7X the cost of developingnew 200mm systems. Possibly $50 to $100million or more in development costs foreach process technology step will be needed.Samsung estimates that a 20,000 wafer permonth 300mm line will cost approximately$2.4 billion, and will require a 12,000m2

cleanroom (130,000ft2), while a 30,000 waferper month fab will cost approximately $3.6billion, requiring 18,000m2 (200,000ft2) ofcleanroom space.

Early studies by SEMATECH estimated that300mm tool costs would increase by 50 per-cent over 200mm, tool throughput would bereduced by 40 percent. Starting wafer costwould be decreased by 30 percent per unitas estimated by VLSI Research (Figure 7-8).

High Volume (20,000)

Medium Volume (10,000)

Low Volume (2,000)

Pilot Line (500-1,000)

Fab Size (Wafers per Month)

—

—

2

9

1998

—

1

5

5

1999

5

4

—

—

2000

4

—

—

—

2001

2

1

—

—

2002

Source: SEMI 22665

Figure 7-7. Planned 300mm Wafer Fabs



Today industry experts are much more con-fident that these costs can be brought downwith TIÕs Robert Doering estimating a 20-40percent increase in tool cost, 3-14 percentmore dice per wafer (based on lower edgeloss for larger chips), and an overall reduc-tion in cost per chip of 27-39 percent, asshown in Figure 7-9.[4] In addition, TI esti-mates that labor cost, materials use andemissions should be comparable betweenthe two wafer sizes and that higher yieldsmay be possible. As of 1Q Õ97, prime 300mmwere as high as $1,500 but are expected todrop to $650-$800 each in volume.

A 300mm test wafer is shown in Figure 7-10.One industry participant estimated that pos-sibly over 40,000 test wafers will be requiredto validate equipment in 1997 alone.Bringing down the starting wafer cost isabsolutely critical. Intel has stated that the300mm cost per wafer cannot exceed 200mmcost per wafer. To meet this, higher through-puts on all tools is required and the utiliza-tion of chemicals and materials must beincreased (dramatically in some cases),including that of ultrapure DI water.

$100 $75 $50

150mm 200mm 300mm

Source: VLSI Research Inc. 22798

Figure 7-8. Cost/Unit of Silicon

Cost Per Square cm

Usable Portion of Wafer

Cost Per Chip

Labor

Tool Capital Cost

Materials Use

Emissions

Process/Probe Yield

25 - 30% Less

3 - 14% More

27 - 39% Less

About Equal

20 - 40% More

About Equal

About Equal

Slightly Better

Source: Texas Instruments 22623

Figure 7-9. 300mm Versus 200mm at Maturity



Although the issues raised by the prospect ofconversion to 330mm are multifaceted, themotivation is clearly economic rather thantechnical. At the 2nd annual global 300mmsymposium[6] held in June of 1997,MotorolaÕs Manufacturing TechnologyDevelopment presented a comparison of256M DRAM die cost on 200mm and 300mmwafers showing a 40 percent lower die costassuming comparable sized fabs (Figure 7-11). Even with downsizing the 300mm fab toequalize die output, they predict a die costsavings of between 25-30 percent.

Source: MRS Technology 22622

Figure 7-10. A 300mm Test Wafer

Source: Motorola MTD 22772

ToolDepreciation

42%

Tool Maintence15%

Direct Pers6%

Indirect Pers7%

ManufacturedSpace7.5%

Non-ManufacturedSpace

.5%

Wafer12%

Consumables7%

ControlWafer

3%

ToolDepreciation

41%

Tool Maintence15%

Direct Pers8%

Indirect Pers10%

ManufacturedSpace

10%

Non-ManufacturedSpace

1%

Wafer4%

Consumables10%

ControlWafer

1%

200M 300M

$X $1.45X

200mm 300mmPercent Delta

(300/200)

85

—

68

—

208

—

163

—

+145

–40.8

+140

–39.6

280mm2 Die Count

280mm2 Die Cost

350mm2 Die Count

350mm2 Die Cost

Key Assumptions:

• 20K Wafer Starts/Month• 300mm/200m Tool Cost = 1.3X• 300mm/200mm Wafer Cost = 3.7X

Figure 7-11. 256M DRAM Die Cost Analysis



300mm Development

The development of 300mm processingcapability is primarily taking place in Austin,Texas, and Yokohama, Japan.

In early 1996, a cooperative venture wasformed between 10 Japanese firms to assessand improve 300mm wafer quality, and toevaluate 300mm wafer processing equipment.Companies involved in the venture includeNEC, Toshiba, Hitachi, Fujitsu, Mitsubishi,Matsushita, Oki, Sanyo, Sharp, and Sony.Wafer standards are being developed by aworking group including representativesfrom the EIAJ, JEIDA, SIRIJ, Japan Society ofNewer Metals, and SEAJ. The group is testing10-15 wafer processing systems at its lab inYokohama, and is expected to have received60 systems by the end of 1997, including a248nm stepper from Canon. The SELETEorganization is expected to spend roughly$350 million between 1996 and 2000, andbetween SELETE, the Japan Working Groupfor 300mm Technology and the Association ofSuper-advanced Electronics Technologies,approximate funding is $550million (60 bil-lion yen) over five years.

Meanwhile, a parallel effort was organizedamong U.S., European, Korean, andTaiwanese firms, the International 300mmInitiative (I3001). Participants include Intel,Motorola, Lucent Technologies, TexasInstruments, IBM, AMD, Siemens, SGS-Thomson, Philips, Samsung, Hyundai, LGSemicon, and TSMC. Both groups target late1997 or early 1998 for first 300mm wafer use,and first production on 0.25µm or 0.18µmgeneration of devices (256M and 1GDRAMs, respectively).

I3001 anticipates having 70-80 wafer process-ing tools tested and qualified by the end of1998. Initially funded at $26 million ($2 mil-lion from each of its 13 members), I3001Õs 18-month program goals include:

¥ providing inputs to international stan-dards activities,

¥ developing consensus on performancemetrics and demonstration methods,

¥ demonstrating 300mm equipment/materi-als for 0.25µm processing,

¥ defining a program by mid-1998 fordemonstrating and qualifying 0.18µmequipment, which will be performedthrough 2000.

Over 30 pieces of equipment will begindemonstration in SEMATECHÕs lab inAustin in 1997. These tools are manufacturedfrom a number of different vendors world-wide including ADE, Applied Materials,JEOL, Kokusai, Leica, Lumonics, Mattson,Schmitt Measurement, SCP, SEZ, Tencor, TELand Verteq.

Equipment Developments

Some of the equipment-level developmentsin 300mm processing include the following:

¥ AET Thermal shipped an RTA system toMEMC

¥ Applied shipped its first 300mm RTPsystem to Hyundai

¥ Empak announced its first front-openingpod

¥ Equipe Technologies developed a vacuumcluster tool platform

¥ Horiba developed an interferometer-basedwafer flatness tester

¥ Kokusai Electric has prototyped a 300mmdiffusion furnace



¥ Nanometrics installed a thin film metrol-ogy tool at SELETEÕs lab

¥ PRI Automation developed a tool thatloads wafer carriers to and from a loadport, first integrated on EatonÕs andSTEAGÕs tools

¥ SubMicron Systems is developing a300mm automated wet station

¥ Tokyo Seimitsu and Kulicke & Soffa aredeveloping a 300mm dicing machine

Standards

Standardization of many tool-specific issuesshould reduce 300mm capital equipmentcost significantly. As summarized in TheProduction Cost Savings Forum Report[5],lack of standardization in the industry onnon-competitive parts of the wafer process-ing systems typically leads to capital costincreases of up to 2X the base system cost.For this reason, such standards are beingdeveloped for 300mm processing with manyof the issues are summarized in Figure 7-12.

Sputtering challenges include step coverageof barrier metals and the ability to fill higheraspect ratio holes uniformly. Bringing downthe cost of high energy ion implanters willincrease the likelihood that its brought intothe fab, while low current challenges forshallower source and drain junctions remaina challenge. The industry has identifiedexposure tools and defect detection tools asbeing two of the most significant challengesfor 300mm processing. Stepper performance(depth of field, overlay and resolution) of248nm tools is the primary concern, followedby reliability of the system and excimer laser,stage speed and accuracy, and vibration con-trol. Efficient in-situ monitoring and clean-ing processes are needed for CVD

multi-chamber systems in addition to theaccommodation of new materials in bothCVD and etch. Small batch (also called mini-batch) systems are being considered forwafer cleaning and furnace processes.

Beyond the processing equipment, factoryautomation in a 300mm fab is critical. In par-ticular, a lack of standards for automatedproduction and handling systems exists. Theindustry must also standardize the way thatprocess tools and handlers interface with thecarrier. Currently both open and closed carri-ers are being considered.

Most believe that the transitional lot size of 24wafers would not be manageable beyond200mm processing. Thirteen wafer lots andsmaller are being considered. Ergonomicissues become critical at 300mm and largerwafer sizes. For instance, 150mm wafers are0.675mm thick and weigh about 30 grams,while 200mm wafers have a thickness of0.725mm and weigh 50-60 grams. The pro-posed new 300mm wafer will be approxi-mately 0.800mm thick, weighing about 140grams. The automation needed to movebatches of 300mm wafers will be costly. This isan issue that many Japanese and other ICmanufacturers realized early in 200mm pro-cessing, and many U.S. manufacturers arebeginning to understand as they implementautomation to improve the efficiency oftodayÕs 200mm fabs. Even so, 200mm process-ing equipment has no standard equipmentinterface and there are multiple differences inloading height, depth and direction by equip-ment manufacturer and equipment type.



Sputterer

Implanter

Lithography

CVD

—

3 DeviceManufacturers

—




7 DeviceManufacturers2 Suppliers


Device Manufacturer Equipment ManufacturerSingle WaferBatch

Type Comment

—

—

• Resolution, overlay accuracy, exposure field size (balance against throughput)• Capability for new resist material

• Keep up with advanced process with high density plasma• Higher reliability, particle free transfer mechanism• Multi-chamber, continuous processing

• Less particles/higher coverage and better filling• Sputtering in finer, higher aspect ratio holes• Less contamination, residues• Establishment of chamber monitoring technologies (stage temperature uniformity, RGA, particles etc.)• Across the surface erosion cathode• Improve existing technologies for larger diameter• Step coverage, especially bottom coverage (barrier metal, etc.)

• Equipment stability, maintenance free equipment• Higher speed, charge up, footprint, lower weight• Lower prices for high energy implanter• Control over contamination, and damage• Batch type for high dose; single wafer for medium dose• Contamination reduction• Medium dose: improve the beam current uniformity across the wafer• High dose: better throughput• Single wafer high current implanter equipment (without a drop in throughput)• Introduction of high energy implanter, smaller equipment footprint

• Excimer lithography capability (control over the atmosphere)• Faster pattern defect inspection and automation (wafers)• Optical system function (0.18-0.25µm)• Efficient in-line setup between CV/DV and stepper• Safer, longer lifetime, and finer geometry excimer process• Measures for reducing construction cost and running cost• Localized hollowing by equipment module• Mask transfer/loading method (less clean environment) standardization of mask I/O among stocker, transfer system, and lithography system• Vibration specification• Lack of basic performance (resolution, depth of field, dimensional tolerance, overlay accuracy)• Larger field size, improvement in resolution alignment, resist development (excimer, etc.)

• Fewer particles/higher coverage, better planarization• Wider applications (smaller geometries, new materials)• Improved dust control and safety• In situ monitoring and cleaning• Hardware specification for making native oxide free polysilicon and SiN deposition possible using multi-chamber system• Single wafer LPCVD (high throughput needed)

Source: SEMI 22674/22675

Figure 7-12. 300mm Tool Development Issues



Dry Etch

Wet Etch

Diffusion

—





Device Manufacturer Equipment ManufacturerSingle WaferBatch

Type Comment

• Ensuring performance uniformity• Improvement in plasma uniformity (to keep up with larger chamber)

• Lot size (throughput) definition for compound process

• Structure of end station tie-in• Wafer cooling• Matching between beam scanning system and electron flood gun• Better transfer system reliability

• Elimination of particles/no residues/anisotropic etching/low damage• EDP reliability• Wider applications (finer geometries, new material)• Better control over dust and safety• In situ monitoring and cleaning• Process technology for 0.2µm• Uniformity and throughput improvement with better profile selectivity will be required for 12" diameter• Improve existing technology for larger diameter• Finer geometry processing (contact) and selectivity (Al) are needed, although no problem with single wafer• Stable performance and self cleaning technology

• Less particles/control over suface cleanliness/ control over atmosphere• Particle• Single wafer and in-line process, simpler, dry process• Combination of dry etch and light etch• Use multiple chemicals for resist stripping depending on the process• Small, low capacity wet etcher for various applications• Combined use of single wafer treatment equipment and small batch treatment equipment• Problems of micro-roughness and native oxide treatment• Less chemicals should be used for single wafer treatment

• Non-contact wafer temperature measurement method• Speed of temperature ramp up and ramp down (prevent wafer warp)• Wider use of RTP, low temperature treatment• Improved uniformity• 8" diameter: entire process is batch type for 64M, cluster for critical steps with 256M (single wafer or 25 wafer batch treatment necessary)• 12" diameter: same as 8" for critical steps, mini batch treatment for other steps• Maintain the throughput• Need to develop high speed anneal• Small batch treatment• Lower equipment cost and establishment of low temperature process for single wafer diffusion

Source: SEMI 22676/22677

Figure 7-12. 300mm Tool Development Issues (continued)



Beyond equipment concerns, Figure 7-13shows the targeted production schedule for300mm starting wafers from five major sup-pliers, and looking out further the supplyescalates beyond the year 2001 (Figure 7-14)according to the Japan Society of NewMetals. As shown in Figure 7-15, exports ofsilicon from Japan has increased significantly

in recent years as semiconductor manufac-turing in other regions has continued toincrease. One of the major challenges for sil-icon suppliers is managing 300mm demandtogether with balancing demand for wafersof the various other sizes. Some of the chal-lenges for 400mm have already been antici-pated (Figure 7-16).

Company

Monthly Prototype Production Targets

July 96 Dec. 96 July 97 July 98Dec. 97

SEH

Sumitomo

Mitsubishi

Komatsu

Toshiba

Total

1,000

500

500

—

—

2,000

5,000

1,000

1,000

—

—

7,000

1,000

—

8,000

5,000

—

13,000

20,000

10,000

2,000

5,000

1,000

38,000

Source: Nikkei Sangyo Shimbun, Nihon Keizai 22625

Figure 7-13. Japan 300mm Wafer Supplier Plans

0

200

400

600

2011200620011996

Year

Un

its

Per

Mo

nth

(T

ho

usa

nd

)

Source: JSNM 22627

300mm Wafers

400mm Wafers

Figure 7-14. Large Diameter Wafer Forecast



Outlook for 300mm Wafer Processing

Perhaps the biggest question in 300mmdevelopment pertains to the issue of cost ÐHow will the semiconductor manufacturingand equipment and materials suppliers,with a combined market size of approxi-mately $170 billion, build a $15-20 billioninfrastructure for 300mm processing in afew years while meeting on-going require-ments for device and process developmentfor 0.25µm, 0.18µm, and future generationsof devices? Possibly many semiconductor

manufacturers will find that through alter-native device design techniques, smaller diesize will be possible, thereby delaying300mm adoption out to the 0.15µm or0.13µm generation.

The second pressing question is to what theextent will the two consortiums, I3001 andSELETE, cooperate? Information from SEMIindicates that standards will be jointly devel-oped but the tool projects are clearly separateefforts. Time will tell to what extent 300mmprocessing information will be shared.

0

1,000

2,000

3,000

4,000

5,000

199719961995199419931992

Ton

s

Source: JEI 22626

4,500

5,000

4,0994,108

3,816

3,327

3,0513,028

2,4582,509

2,1152,335

Polysilicon Production

ExportsDemand Within Japan

Single-Crystal Silicon Sales

Actual Sales Projected Sales

Figure 7-15. Projected and Actual Sales Figures For Ultrahigh Purity Silicon



Outside of the largest semiconductor manu-facturers, companies will carefully observethe advantages and disadvantages associ-ated with the 300mm transition. No one inthe industry can foresee how many compa-nies will ultimately use these larger wafers.This, of course, should come as no surprise,as to date, a number of manufacturers havenever needed to progress beyond 150, 125, oreven 100mm wafer processing. In any case,wafer size transitions, especially the move to300mm, will not become a reality until it canbe made more cost-effective.

References

1. Anderson, ÒStoking the Productivity Engine with New Materials and Larger Wafers,Ó Solid State Technology, March 1997, p.57.

2. Ching and R. Mirtha, ÒComparing Cost of Ownership for 200- and 150-mm Immersion Wet-cleaning Equipment,Ó Microcontamination, January 1994, p.29.

3. S. Myers, ÒThe Realities of Conversion to 300 mm Silicon Wafers,Ó Semiconductor International, April 1996, p.83.

4. R. Doering, speech in Grenoble, France, April 1997.

5. Production Cost Savings Forum Ð IC Report, published by SEMI, June 1995.

6.D, Tull, Motorola MTD Ò300mm FactoryDesign,Ó 2nd Annal Global 300mmSymposium, June 1997.

Growth of a 400kg. 400mmdiameter dislocation-freesilicon ingot

Develop crystal cutting,polishing, etching, and wetcleaning processescapable of making waferswith flatness of 0.13µm orbetter, surface metalcontamination of 108

atoms/cm2, and controlledparticle size of 0.04µm orbetter

Grow epi films withthickness and resistivityvariations of 1 percent orbetter, and transistionsregion width of 0.5µm orless

Crystal Growth

Wafer Fabrication

Epitaxial Growth

Equipmentdesign

andsimulation

Equipmentdesign

Equipmentdesign

Equipmentfabricationand basic

experiments

Equipmentfabrication

andexperiments

Equipmentfabrication

andexperiments

Equipmentrevision

and crystalgrowth

Equipmentrevision

andexperiments

Equipmentrevision

andexperiments

Integrationwith otherprocesses

Integrationwith

inspection/evaluationtechniques

Equipmentrevisionand final

experiments

—



Source: Super Silicon Crystal Research Institute 22628

Department Goal 1996 1997 1998 1999 2000

Figure 7-16. Roadmap for 400mm Wafers

section 7

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