Solid-State Electronics 54 (2010) 919–924

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Solid-State Electronics

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Self-aligned inversion-channel In0.75Ga0.25As metal–oxide–semiconductorfield-effect-transistors using UHV-Al2O3/Ga2O3(Gd2O3) and ALD-Al2O3

as gate dielectrics

T.D. Lin a, H.C. Chiu a, P. Chang a, Y.H. Chang a, Y.D. Wu a, M. Hong a,*, J. Kwo b,c,**

a Department of Materials Science and Engineering, National Tsing Hua University, Hsinchu 30013, Taiwanb Department of Physics, National Tsing Hua University, Hsinchu 30013, Taiwanc Center for Condensed Matter Sciences, National Taiwan University, Taipei 10617, Taiwan

a r t i c l e i n f o a b s t r a c t

The review of this paper was arranged byProf. S. Cristoloveanu

Keywords:Ga2O3(Gd2O3)Al2O3

InGaAsIII–VHigh-jMetal gateUHVALDSelf-alignedInversion-channelMOSFET

0038-1101/$ - see front matter � 2010 Elsevier Ltd. Adoi:10.1016/j.sse.2010.04.033

* Corresponding author.** Corresponding author at: Department of Physics, N

Hsinchu 30013, Taiwan.E-mail addresses: mhong@mx.nthu.edu.tw (M. Hong

(J. Kwo).

High-performance self-aligned inversion-channel In0.75Ga0.25As n-MOSFETs using in situ ultra-high-vac-uum (UHV) deposited Al2O3/Ga2O3(Gd2O3) [GGO] and ex-situ atomic-layer-deposited (ALD) Al2O3 as gatedielectrics have been fabricated. Both devices exhibit high drain currents and transconductances. A1.2 lm-gate-length In0.75Ga0.25As MOSFET using Al2O3 (2 nm-thick)/GGO (13 nm-thick) gate dielectricdemonstrated a maximum drain current of 970 lA/lm, a peak transconductance of 410 lS/lm, and apeak mobility of 1560 cm2/V s. A maximum drain current of 740 lA/lm and a peak transconductanceof 325 lS/lm were exhibited by a 1 lm-gate-length In0.75Ga0.25As MOSFET using ALD-Al2O3 (6 nm-thick). A comparison between the inversion-channel InGaAs MOSFETs with gate dielectrics using theUHV- and ALD-approaches, and fabricated using the same self-aligned process, was carried out to provideinsights for achieving InGaAs MOSFETs with even higher device performances. The comparison in thedevice performances was extended to cover representative enhancement-mode InGaAs MOSFETs, includ-ing self-aligned inversion-channel, non-self-aligned inversion-channel, and flat-band, or buried channel-type of E-mode (non inversion-channel) III–V devices.

� 2010 Elsevier Ltd. All rights reserved.

1. Introduction

The technology of high-j dielectrics plus metal gates, which hasresolved the gate leakage issue in the 45 nm MOSFET production, isone of the most important recent innovations in CMOS (comple-mentary metal–oxide–semiconductor). Moreover, the dominantrole of Si as the semiconductor channel is now in question, as fur-ther scaling does not guarantee performance benefits. High-j onhigh carrier mobility semiconductors of InGaAs hybrid with Si, astrong contender with consensus for the technology beyond the15 nm node CMOS, may lead to faster devices and close the so-called performance gap, where the expected increase in switchingspeed of the devices no longer keeps up with the scaling trend [1].

Achieving a low interfacial density of states (Dit) and low elec-trical leakage currents in high-j/InGaAs, key for fabricating theinversion-channel MOS field-effect-transistors (MOSFETs), hasbeen realized firstly in ultra-high-vacuum (UHV) deposited amor-

ll rights reserved.

ational Tsing Hua University,

), raynien@phys.nthu.edu.tw

phous Ga2O3(Gd2O3) [GGO] [2] and single crystal Gd2O3 [3] onGaAs. A low Dit of <1012 cm�2 eV�1 along with low leakage currentsof 10�8 A/cm2 was demonstrated. In addition, without employinginterfacial passivation layers (IPL), atomic-layer-deposited (ALD)Al2O3 [4,5] and HfO2 [6] have given low Dit’s and low electricalleakages. Good electrical properties were also reported in MOS de-vices with Si [7] and Ge [8] as IPL between high-j’s and InGaAs.Notice that the MOS capacitors of GGO/In0.2Ga0.8As with in situAl2O3 cap have shown remarkably excellent C–V characteristicsand thermodynamic stability at high temperatures as well as alow CET of �1 nm [9,10].

These efforts of unpinning Fermi level in the high-j/InGaAsinterface have opened up a new era, timely for inversion-channelInGaAs MOS devices.

The first non-self-aligned inversion-channel GaAs and In0.53-

Ga0.47As MOSFETs were demonstrated using UHV-GGO as gatedielectrics [11–13]. Inversion-channel InGaAs (In content P53%)MOSFETs with ALD high j gate dielectrics have given excellent de-vice performances [14–19]. With Si (Silane) IPL, (In)GaAs MOSFETswith ALD and MOCVD high j oxides have also shown good draincurrents [7,20]. With the UHV-Al2O3/GGO gate dielectric,self-aligned inversion-channel In0.53Ga0.47As MOSFETs have exhib-ited very high drain current (ID) and transconductance (Gm)

920 T.D. Lin et al. / Solid-State Electronics 54 (2010) 919–924

[21,22]. The device structure and characteristics of these aboveinversion-channel InGaAs MOSFETs are similar to those exhibitedin the traditional SiO2/Si. On the other hand, non-inversion-chan-nel enhancement-mode (E-mode) III–V MOSFETs have beenfabricated in the configurations of flat-band [23] or buriedchannel-type [24,25].

Compared with In0.2Ga0.8As MOSFETs [26,27], the In0.53Ga0.47AsMOSFETs [14,21] have demonstrated improved device perfor-mance in terms of maximum ID and peak Gm, and In0.75Ga0.25AsMOSFETs showed even better performance [16,17]. The enhance-ments in electron mobility, saturation velocity, and intrinsic carrierconcentrations in the channel with high Indium contents mayattribute to the improved performance.

In this work, In0.75Ga0.25As was employed as the channel mate-rial for fabricating self-aligned inversion-channel MOSFETs. BothUHV-Al2O3/GGO and ALD-Al2O3 were used to passivate the In0.75-

Ga0.25As surface, without invoking any IPL or surface treatments.Comparisons between the inversion-channel devices fabricatedwith those two passivation methods and moreover, among manyrepresentative E-mode GaAs and InGaAs MOSFETs operated invarious configurations are given.

2. Experimental

2.1. Growth of device structures

A schematic cross-section of the self-aligned inversion-channelIn0.75Ga0.25As MOSFETs is shown in Fig. 1. The InGaAs layers of un-doped buffer and the p-doped (with Be) well were grown on semi-insulating InP substrates using molecular-beam-epitaxy (MBE).Al2O3/GGO gate dielectrics were e-beam evaporated onto In0.75-

Ga0.25As surface in UHV, with a procedure reported previously[2]. Also, ALD-Al2O3 films were ex-situ deposited on top of theIn0.75Ga0.25As layer, with a controlled short transfer time of lessthan 10 min from the UHV system to the ALD reactor, which resultsin a high-quality Al2O3/In0.53Ga0.47As interface [28]. After post-deposition-annealing at 300 �C for 30 min in a N2 ambience, thesamples were covered by TiN 160–200 nm thick by reactive-sput-tering from a pure Ti target in Ar/N2 RF-plasma.

2.2. Device fabrication and measurements

The inversion-channel devices were fabricated with a previ-ously published self-aligned process [21,27]. The definition andformation of the metal gates was carried out using inductively cou-pled plasma reactive ion etching (ICP-RIE). The dry-etched metalgates and photo-resist defined the S/D regions, onto which Si+ ionswere implanted through the gate dielectrics. Activations of the im-planted ions were accomplished with rapid-thermal-annealing

Fig. 1. Schematic cross-section of self-aligned In0.75Ga0.25As n-MOSFETs with TiNmetal gate. The gate dielectrics are UHV-Al2O3/GGO and ALD-Al2O3.

(RTA) at 600–700 �C in He or N2 ambience. The Al2O3 and GGO atthe S/D contact regions were then etched using dilute buffered-oxide-etch (BOE) and HCl solutions, respectively. The ohmic con-tacts were subsequently formed by e-beam/thermal evaporationof Pd/Ge/Ti/Pt metal stack and a lift-off process, which was fol-lowed by annealing at 400 �C for 10 s in a N2 ambience to achievea low contact resistance. Finally, the Ti/Pt/Au pads for measure-ment (not shown in Fig. 1) were deposited using e-beam/thermalevaporation. The electrical properties of MOSFETs were character-ized by Precision Semiconductor Parameter Analyzer Agilent4156C.

3. Results and discussion

3.1. MOSFETs using UHV-Al2O3/GGO gate dielectrics

The DC output characteristics, ID–VD curves, of a self-alignedinversion-channel In0.75Ga0.25As MOSFET with UHV-deposited2 nm-thick Al2O3 and 13 nm-thick GGO is shown in Fig. 2a for a1.2 lm (gate-length (L)) � 10 lm (gate width (W)) device; a max-imum drain current (ID) of 970 lA/lm was obtained under a gatebias (VG) of 3 V and a drain bias (VD) of 2.5 V. The transconductance(Gm) curve measured from the same device is shown in Fig. 2b,from which a maximum Gm of 410 lS/lm was obtained atVD = 2.5 V and VG = 0.95 V. The threshold voltage extracted from alinear extrapolation is about 0.22 V.

Notice that the gate dielectric of this device is thicker than thatused in our previous work of Al2O3/GGO/In0.53Ga0.47As MOSFET, inwhich the thicknesses of Al2O3 and GGO were 2 nm and 5 nm,respectively [21]; the capacitance equivalent thickness (CET) here

Fig. 2. (a) Output characteristics ID vs VD of a 1.2 lm (L) � 10 lm (W) inversion-channel UHV-Al2O3/GGO/In0.75Ga0.25As MOSFET. A maximum ID of 970 lA/lm ismeasured at VG = 3 V and VD = 2.5 V; (b) The Gm curve of the same device showing apeak Gm of 410 lS/lm, measured at VD = 2.5 V.

T.D. Lin et al. / Solid-State Electronics 54 (2010) 919–924 921

is �4.76 nm, roughly 1.8 times thicker than that of our previousIn0.53Ga0.47As MOSFET. However, the drain current obtained inthe In0.75Ga0.25As MOSFET with 1.2 lm-gate-length is comparablewith the In0.53Ga0.47As MOSFET with 1 lm-gate-length. Moreover,the In0.75Ga0.25As MOSFET shows higher Gm than that demon-strated in the In0.53Ga0.47As MOSFET, if being normalized to thesame CET and gate-length. The improvements in both drain currentand Gm have been achieved using InGaAs channel with higher Incontent with Al2O3/GGO gate dielectrics.

A peak field-effect mobility of 1560 cm2/V s, estimated from thetransconductance analysis, was achieved, as shown in Fig. 3. Themobility of this In0.75Ga0.25As MOSFET is higher than the1300 cm2/V s obtained from the In0.53Ga0.47As MOSFET using thesame method [21], as expected for the InGaAs channel with higherIn content. Fig. 4 shows curves of drain currents versus gate voltagemeasured under drain voltages of 0.5 V and 1.5 V, respectively. Adrain-induced-barrier-lowering (DIBL) of 31 mV/V and a sub-threshold swing (S.S.) of 220 mV/decade was obtained, higher than100 mV/decade demonstrated in our previous work of Al2O3/GGO/In0.53Ga0.47As MOSFET. The higher S.S. is likely resulted from thelow oxide capacitance (high CET) and degraded GGO/In0.75Ga0.25Asinterface after 700 �C RTA for dopants activation, which was notyet optimized for the GGO/In0.75Ga0.25As hetero-structure andmay have damaged the GGO/In0.75Ga0.25As interface. Studies ofthe GGO/In0.75Ga0.25As interface properties, such as interfacial den-sity of states, are undertaken, and will be reported in the future.

Fig. 3. Plot of field-effective electron mobility (lFE) as a function of gate bias for a4 lm (L) � 10 lm (W) inversion-channel UHV-Al2O3/GGO/In0.75Ga0.25As MOSFET.The mobility was derived using the formula shown in the inset.

Fig. 4. Drain currents versus gate voltage of a 4 lm (L) � 10 lm (W) inversion-channel UHV-Al2O3/GGO/In0.75Ga0.25As MOSFET measured at drain voltages of 0.5 Vand 1.5 V, respectively, showing a DIBL of 31 mV/V and a S.S. of 220 mV/decade.

3.2. MOSFETs using ALD-Al2O3 gate dielectrics

Fig. 5a exhibits the ID–VD curves of a self-aligned inversion-channel 1 lm (L) � 50 lm (W) In0.75Ga0.25As MOSFET with 6 nm-thick ALD-Al2O3 as a gate dielectric. A maximum ID of 740 lA/lmwas obtained under a gate bias of 2.5 V and a drain bias of 2.5 V.The device was fabricated with a self-aligned process similar tothat used for the aforementioned Al2O3/GGO/In0.75Ga0.25As MOS-FET, however, with a difference in the dopant activation tempera-ture (600 �C in this case). The Gm curve measured from the same

Fig. 5. (a) Output characteristics ID vs VD of an 1 lm (L) � 50 lm (W) inversion-channel ALD-Al2O3/In0.75Ga0.25As MOSFET. A maximum ID of 740 lA/lm ismeasured at VG = 2.5 V and VD = 2.5 V; (b) The Gm curve of the same deviceshowing a peak Gm of 325 lS/lm, measured at VD = 2 V.

Fig. 6. Plot of field-effective electron mobility (lFE) as a function of gate bias for a1 lm (L) � 50 lm (W) inversion-channel ALD-Al2O3/In0.75Ga0.25As MOSFET. Themobility was derived using the formula shown in the inset.

922 T.D. Lin et al. / Solid-State Electronics 54 (2010) 919–924

device is shown in Fig. 5b. A maximum Gm of 325 lS/lm was dem-onstrated at VD = 2 V and VG = 1.25 V. A peak field-effect mobility of490 cm2/V s was estimated from the transconductance analysis, asshown in Fig. 6. Notice that the field-effect mobility is generallylower than the effective mobility extracted using split-CV method.A DIBL of 107 mV/V and a S.S. of 139 mV/decade were also ob-tained, as shown in Fig. 7. The threshold voltage extracted from alinear extrapolation is about 0.15 V. In our previous work, 1 lm-gate-length ALD-Al2O3 (10 nm)/In0.53Ga0.47As MOSFETs showed amaximum ID of 288 lA/lm and a peak Gm of 93 lS/lm [18]. Incomparison, the In0.75Ga0.25As MOSFET reported in this workexhibits maximum ID and peak Gm of about 2.6 and 3.5 times,respectively, higher than those reported for the In0.53Ga0.47As MOS-FETs, while the oxide capacitance is �1.7 times larger than that ofthe In0.53Ga0.47As MOSFETs. The ‘‘extra” increments in ID and Gm

may be attributed to the In0.75Ga0.25As channel.

Fig. 7. Drain currents vs gate voltage of a 2 lm (L) � 100 lm (W) inversion-channelALD-Al2O3/In0.75Ga0.25As MOSFET measured at drain voltages of 0.5 V and 2 V,respectively, showing a DIBL of 107 mV/V and a S.S. of 139 mV/decade.

Fig. 8. Drain current and peak transconductance versus inverse gate-length (1/LG)for (a) UHV-Al2O3/GGO/In0.75Ga0.25As and (b) ALD-Al2O3/In0.75Ga0.25As MOSFETs.Both properties are proportional to the inverse gate-length.

Fig. 8 summarizes the systematic dependence of maximum ID

and peak Gm on various gate-lengths for UHV-Al2O3/GGO/In0.75-

Ga0.25As (Fig. 8a) and ALD-Al2O3/In0.75Ga0.25As (Fig. 8b) MOSFETs;the two values are proportional to the inverse gate-length, 1/LG.Therefore, an improved performance is anticipated for devices withsub-micron gate-length; for example, a drain current of approach-ing 2 mA/lm for a 0.5 lm-gate-length Al2O3/GGO/In0.75Ga0.25AsMOSFETs. Higher performance will also be realized by reducingthe oxide thickness.

3.3. Comparison between MOSFETs using UHV- and ALD-oxides

The UHV-Al2O3/GGO/In0.75Ga0.25As MOSFET used a relativelythicker oxide and has a slightly longer gate-length than that ofALD-Al2O3/In0.75Ga0.25As MOSFET, yet the former showed betterperformance in terms of ID and Gm. Considering the same bias con-dition, the GGO MOSFET exhibits a ID of 834 lA/lm (at VG = 2.5 Vand VD = 2.5 V) and a peak Gm of 374 lS/lm (at VD = 2.0 V) whilethe ALD-Al2O3 MOSFET showed a ID of 740 lA/lm and a peak Gm

of 325 lS/lm. Since both devices use the same In0.75Ga0.25As chan-nel with the same doping concentration, the main factor affecting

Fig. 9. Summary of (a) maximum drain currents and (b) peak transconductances ofrepresentative work on III–V enhancement-mode n-MOSFETs reported in the lastdecade. Devices with gate-length longer than 2 lm are excluded. The number neareach data point indicates the In content (x) of the InxGa1�xAs channel used incorresponding device; x = 0 stands for a GaAs channel. The self-aligned processedinversion-channel devices are denoted with a solid circular and diamond symbols,and the data of non-self-aligned processed inversion-channel devices are denotedwith hollow circular and triangular symbols. Symbols of cross and stars representthe data of other types of E-mode (non inversion-channel) devices.

T.D. Lin et al. / Solid-State Electronics 54 (2010) 919–924 923

the performance may be the difference in interface qualities. Acontrolled short transfer time of less than 10 min from the UHVsystem to the ALD reactor has led to a high-quality Al2O3/In0.53-

Ga0.47As interface compared with most ex-situ ALD approaches[28]. Nevertheless, native oxides, including In2O3, In(OH)3, Ga2O3,and Ga(OH)3, still inevitably exist at the ALD-Al2O3/InGaAs inter-face due to air-exposure [29]. The higher S.S. of the GGO MOSFETthan that of the ALD-Al2O3 MOSFET is more likely resulted froma relative smaller oxide capacitance (Cox) due to its thick oxide.Nevertheless, the device fabrication process has damaged inter-faces and caused high interfacial traps, leading to the high S.S. val-ues in both devices, and needs to be further improved.

3.4. Comparison among E-mode GaAs and InGaAs MOSFETs

Maximum ID and peak Gm of representative E-Mode (inversion-channel or non inversion-channel) InGaAs MOSFETs are summa-rized in Fig. 9a and b, respectively [12–17,19–25]. The details onthe device configurations, Indium contents, gate dielectrics, sur-face/interface treatments and the device performances are summa-rized in Table 1.

The drain current achieved in the self-aligned 1.2 lm-gate-length UHV-Al2O3/GGO/In0.75Ga0.25As MOSFET in this work is com-parable to that reported in our previous work of 1 lm-gate-lengthAl2O3/GGO/In0.53Ga0.47As MOSFET using thinner GGO [21,22], andit is also comparable to the non-self-aligned In0.65Ga0.35As and In0.75-

Ga0.25As MOSFETs using ALD-Al2O3 and shorter gate-length of0.4 lm and 0.75 lm, respectively [15,16]. All these devices are re-cord-keepers showing maximum drain currents of�1 mA/lm. Evenwith relatively thick CET and long channel length, the Al2O3/GGO/In0.75Ga0.25As MOSFET demonstrated a peak transconductance com-parable to most of the leading-edge E-mode III–V MOSFETs. Much

Table 1Summary of representative E-mode n-MOSFETs reported in the last decade.

No. Yearpublished[Ref.]

Research group Type/channel Mat’l Gate dielecmethod/ox(passivatio

(1) 1998 [12] Bell LabsRen, et al.

Inversion-channel/In0.53Ga0.47As

UHV E-beatox = 40 nm

(2) 1999 [13] Bell LabsWang, et al.

Inversion-channel/GaAs

UHV E-beatox = 38–52

(3) 2007 [14] Purdue Univ.Xuan, et al.

Inversion-channel/In0.53Ga0.47As

ALD-Al2O3

tox = 8 nm(4) 2007 [23] Freescale/U.

Glasgow;Hill, et al.

Implant-free/In0.3Ga0.7As

UHV E-beaGaGdO/Ga

(5) 2007 [24] IBMSun, et al.

Buried channel/In0.7Ga0.3As

ALD-Al2O3

tox = 7 nm(6) 2008 [15] Purdue Univ.

Xuan, et al.Inversion-channel/In0.65Ga0.35As

ALD-Al2O3

tox = 10 nm(7) 2008 [21] Natl Tsin-Hua Univ.;

Lin, et al.Inversion-channel/In0.53Ga0.47As

UHV E-beaGGO; tox =

(8) 2008 [16] Purdue Univ.Xuan, et al.

Inversion-channel/In0.75Ga0.25As

ALD-Al2O3

tox = 10 nm(9) 2008 [25] IBM

Sun, et al.Buried channel/In0.7Ga0.3As

ALD-Al2O3

a-Si (tSi < 1(10) 2009 [19] Natl Tsin-Hua Univ.;

Chiu, et al.Inversion-channel/In0.53Ga0.47As

ALD-Al2O3

tox = 6 nm(11) 2009 [17] Purdue Univ.

Wu, et al.Inversion-channel/In0.75Ga0.25As

ALD-Al2O3

tox = 5 nm(12) 2009 [20] Univ. Singapore

Chin, et al.Inversion-channel/In0.53Ga0.47As

MOCVD Hftox = not av

(13) 2009 ThisWork

Natl Tsin-HuaUniv.; Lin, et al.

Inversion-channel/In0.75Ga0.25As

UHV E-beaGGO; tox =

(14) 2009 ThisWork

Natl Tsin-HuaUniv.; Lin, et al.

Inversion-channel/In0.75Ga0.25As

ALD-Al2O3

tox = 6 nm

better performance is expected with the device scaling to sub-mi-cron gate-length and using thinner gate dielectrics.

By using a high In channel of In0.75Ga0.25As, drain current andtransconductance of the ALD-Al2O3/In0.75Ga0.25As MOSFET was im-proved over the previous ALD-Al2O3/In0.53Ga0.47As MOSFET[18,19]. In general, MOSFETs using InGaAs channel with high In-dium contents have shown much better ID and Gm than those usingGaAs or InGaAs channels with low Indium contents [13,26,27].

Taking the gate-length and oxide thickness into consideration,the In0.75Ga0.25As MOSFETs using UHV-Al2O3/GGO as gate dielec-trics showed better performance than those using ALD-Al2O3, fab-ricated with either self-aligned or non-self-aligned process [16,17].The interface quality may be the key for achieving a highperformance.

Comparing with the inversion-channel and non-inversion-channel E-mode III–V MOSFETs, the inversion-channel devicesdemonstrated in our work [18,19,21,22] and by Xuan and Wuet al. [14–17] have shown better performance than those of flat-band [23], or buried channel-type [24,25] of E-mode (non inver-sion-channel) III–V devices. Although the non-inversion-channeldevices were proposed to relax the requirements of low inter-face-state density [24], the interface quality still dominates thegate controllability to the channel and thus the device perfor-mance. Moreover, the relatively thick effective oxide thickness(EOT) of the structures of flat-band or buried channel-type devicesand difficulty in applying a self-aligned process are obstacles forfurther downscaling of the non-inversion-channel E-mode III–VMOSFETs. Taking the advantages of using a structure in thederivatives of high mobility devices, the non-inversion-channelMOSFETs, nevertheless, also showed high transconductances.

In summary, self-aligned inversion-channel In0.75Ga0.25As MOS-FETs using in situ UHV-Al2O3/GGO and ex-situ ALD-Al2O3 as gatedielectrics have shown high performances in terms of drain

tric/depositionide thicknessn)

Device characteristics

m evaporated GGO ID,max = 375 lA/lm (1 lm); Gm = 190 lS/lm(0.75 lm)ID � LG/WG = 375 lA; Gm � LG/WG = 142.5 lS

m evaporated GGOnm

LG = 1 lm; ID,max = 30 lA/lm; Gm = 4 lS/lmID � LG/WG = 30 lA; Gm � LG/WG = 4 lSLG = 0.5 lm; ID,max = 430 lA/lm; Gm = 160 lS/lmID � LG/WG = 215 lA; Gm � LG/WG = 80 lS

m evaporated2O3; tox = 10 nm

LG = 1 lm; ID,max = 407 lA/lm; Gm = 477 lS/lmID � LG/WG = 407 lA; Gm � LG/WG = 477 lS

LG = 0.26 lm; ID,max = 117 lA/lm; Gm = 157 lS/lmID � LG/WG = 30.4 lA; Gm � LG/WG = 40.8 lSLG = 0.4 lm; ID,max = 1050 lA/lm; Gm = 350 lS/lmID � LG/WG = 420 lA; Gm � LG/WG = 140 lS

m evaporated Al2O3/2 nm/5 nm

LG = 1 lm; ID,max = 1050 lA/lm; Gm = 714 lS/lmID � LG/WG = 1050 lA; Gm � LG/WG = 714 lSLG = 0.75 lm; ID,max = 1000 lA/lm; Gm = 430 lS/lmID � LG/WG = 750 lA; Gm � LG/WG = 322.5 lS

(tox = 5.5 nm).5 nm)

LG = 0.09 lm; ID,max = 390 lA/lm; Gm = 610 lS/lmID � LG/WG = 35.1 lA; Gm � LG/WG = 54.9 lSLG = 0.6 lm; ID,max = 678 lA/lm; Gm = 354 lS/lmID � LG/WG = 406.8 lA; Gm � LG/WG = 212.4 lSLG = 0.13 lm; ID,max = 440 lA/lm; Gm = 705 lS/lmID � LG/WG = 57.2 lA; Gm � LG/WG = 91.7 lS

AlO; SiH4 and NH3

ailableLG = 0.25 lm; ID,max � 420 lA/lm; Gm = 45.3 lS/lmID � LG/WG = 105 lA; Gm � LG/WG = 11.3 lS;*with S/D stressors

m evaporated Al2O3/2 nm/13 nm

LG = 1.2 lm; ID,max = 960 lA/lm; Gm = 410 lS/lmID � LG/WG = 1152 lA; Gm � LG/WG = 492 lSLG = 1 lm; ID,max = 740 lA/lm; Gm = 325 lS/lmID � LG/WG = 740 lA; Gm � LG/WG = 325 lS

924 T.D. Lin et al. / Solid-State Electronics 54 (2010) 919–924

current, transconductance, and mobility. Improvement over previ-ous In0.53Ga0.47As MOSFETs has also been achieved with theemployment of In-rich In0.75Ga0.25As channels. With the sameself-aligned process, UHV-Al2O3/GGO passivated In0.75Ga0.25AsMOSFETs outperform the ex-situ ALD-Al2O3 passivated devices.The better performance is contributed by the high-quality GGO/InGaAs interface free of In/Ga native oxides, which inevitably existat the Al2O3/InGaAs interface formed in an ex-situ ALD process. Thedata presented in this work and all the others’ work summarized inTable 1 and Fig. 9, are extrinsic values, which are far less than theintrinsic values; the extrinsic performances will approach theintrinsic values if the parasitics are improved.

Acknowledgements

The authors wish to thank the National Science Council (GrantNos. NSC-97-2120-M-007-008 and NSC-97-3114-M-007-001), andthe Ministry of Education, Taiwan for supporting this work. Wewould also like to acknowledge the support from Intel and the AsianOffice of Aerospace Research and Development of the US Air Force.

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