self-testing embedded two-rail checkers

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JOURNAL OF ELECTRONIC TESTING: Theory and Applications KL549-08-Nikolas February 12, 1998 13:35

JOURNAL OF ELECTRONIC TESTING: Theory and Applications 12, 69–79 (1998)c© 1998 Kluwer Academic Publishers. Manufactured in The Netherlands.

Self-Testing Embedded Two-Rail Checkers

DIMITRIS NIKOLOSDepartment of Computer Engineering and Informatics, University of Patras, 26500 Rio, Patras, Greece

[email protected]

Abstract. This paper presents a new simple and straightforward method for designing Completely TestableEmbedded (CTE) parity trees, and Self-Testing Embedded (STE) two-rail checkers. In the design of CTE paritytrees the two inputs XOR gate has been used as the building block. In the case of STE two-rail checkers withninput pairs the building block is the two-rail checker with 2 input pairs. During normal, fault free, operation eachXOR gate receives all possible input vectors, while each two-rail checker with 2 input pairs receives all possiblecode input vectors. The great advantage of the proposed method is that it is the only one that gives in a simpleand straightforward way an optimal CTE/STE tree realization with respect to the hardware (number of blocks) andthe speed (number of block levels). Designing the two input two-rail checker as proposed by Lo inIEEE J. ofSolid-State Circuits, 1993, we get optimal STE two-rail checkers taking into account realistic faults.

Keywords: parity tree, parity checker, two-rail checker, self testing, embedded self-testing circuits

1. Introduction

There are many advantages to modular design of com-plex VLSI circuits. One significant advantage is theenhancement of circuits’ testability. It is simpler todeal with smaller blocks when the question of the testpattern generation or error checking capability is ad-dressed. This partitioning, however, creates a new prob-lem, which is the controllability of the input lines of theembedded blocks. A block C is considered embeddedin a larger circuit if some or all the input lines of C arenot primary inputs of the larger circuit.

In some cases the embedded block can be designedin such a way so as to be completely testable, that is,it is tested for a set of faultsF , by the input patternsthat it receives during normal, fault free, circuit opera-tion. Such a logic block is called Completely TestableEmbedded (CTE) circuit [1], while in the case thatthe logic block is a checker is called Self-Testing Em-bedded (STE) circuit [2–6]. The main advantage ofCTE/STE circuits is that the input lines of a CTE/STElogic block need not be controllable, for testing pur-poses, from the primary inputs of the larger circuit.Such a direct control from the primary inputs of the

larger circuit requires extra pins and/or circuitry on thechip and adds to the complexity of the design [2].

The problem of designing a CTE/STE circuit is, in asense, the inverse of the problem of test pattern gener-ation. In the latter, a realization of a circuit that imple-ments a certain logic function is given and the problemis to find a set of input patterns for the circuit that testit. In the former however, the set of input patterns thatthe circuit receives during normal, fault free, opera-tion is given, and the problem is to find a realizationof the circuit that implements the required logic func-tion and that is tested by the given set of normal inputpatterns.

Among the techniques that are used for error check-ing and correcting in computer systems, parity codesand two-rail codes have found wide application [7].Parity encoding is usually used on buses, registersand memory arrays while the two-rail code is usedfor comparing outputs of duplicate systems, and forcompaction of error detector outputs in self-checkingsystems. Evidently in most cases [2] the parity tree, theparity checker or the two-rail checker is an embeddedcircuit that receives during normal, fault free, opera-tion a predetermined set of code inputs which may be a

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70 Nikolos

subset of its entire input code space. Thus, the problemof designing CTE parity trees, STE parity checkers andtwo-rail checkers arises.

Two approaches have been followed to designSTE parity and two-rail checkers. One approach usesadditional hardware and/or signals with aim the gener-ation of additional code words [8–12]. In [8] in orderto achieve the design of a STE two-rail checker in acascaded form proposed the use of two flip-flops thatchange values with every clock input. The disadvan-tage of this method is the long delay due to the cas-caded form of the checker. Also a stuck-at fault on theclock line is never detected while prevents the two-railchecker from receiving its test set. A stuck-at fault onthe clock line can be detected by using a TSC checkerfor periodic signals [13]. This checker is implementedusing two monostable multivibrators [13] and increasesthe hardware requirements of the two-rail checker. Be-sides monostable multivibrators are parameter depen-dent devices and their use should be avoided becausethey cause various testing problems [14]. In [9] the in-sertion of clockedD flip-flops at selected input pairs ofa two-rail checker was proposed. The main drawbackof this technique is that a stuck-at fault on the clocksignal can not be detected, while prevents the two-railchecker from receiving its test set. The use of an LFSRwas proposed in [10]. The great drawback of thismethod is the prohibitively large hardware overhead.For a checker withn inputs this method requiresnXORs andn clocked flip-flops. Besides this, a stuck-atfault on the clock signal can not be detected and causesthe same problem with the previously referencedmethods.

In [11] the use of a simpler circuit than the LFSR wasproposed. As in the other methods [8–10] that use theclock signal, a stuck-at fault on the clock line cannotbe detected and causes the same problem. One moredrawback of this method is the long delay due to thecascade form of the proposed checker. Specifically, thedelay is equal to the delay ofn module levels, wherenis the number of input pairs. The STE two-rail checkerdesigned in [11] for each input vector produces a se-quence of four vectors. This means that if, due to itsspecifications, the maximum delay of the functionalcircuit should be less than or equal tot , the maximumdelay of the checker should be less than or equal tot /4.Taking into account the above and the long delays ofthe two-rail checkers proposed in [11] we conclude thattheir applicability may be limited when the number ofinputs is not very small.

Recently a self-checking comparator/two-rail chec-ker with one periodic output was proposed in [12],which as it has been shown [12] can be modified to havea standard two-rail encoded output. A disadvantage ofthis method is that a stuck-at fault on the clock line ofthe comparator/two-rail checker with two-rail encodedoutput is never detected and also prevents the two-railchecker from receiving its test set. If the frequencyof the periodic signalx0 is twice the frequency of theinput patterns, two complementary input code wordsare sufficient to detect all single stuck-at faults (exceptthat on the clock line). In the case that the clock signalx0 and the input patterns have the same frequency thetesting of the XOR gates depends on the order of thearrival of the input patterns, thus the checker is not selftesting. The necessity the frequency of the periodicsignal to be twice the frequency of the input patternsimplies that the checker should be two times faster thanthe functional circuit, which limits the applicability ofthese comparators/two-rail checkers when the numberof input pairs is large.

In the other approach the checker is designed in sucha way to be self testing with the code inputs that receivesduring the normal, fault free, operation of the functionalcircuit [1–6, 15, 16]. The first method that followedthis approach is given in [1]. The algorithm proposedin [1] make backtracks in order to design CTE paritytrees or STE parity checkers. The backtracks make thealgorithm prohibitively time consuming for large num-ber of inputs. Besides the above drawback in order toget an optimal, with respect to the XOR-gate levels, im-plementation of the parity tree or checker an exhaustivesearch of the design space is required, which when thenumber of inputs is not small can be prohibitively large.Three algorithms for designing STE parity checkers,under different conditions or possible faults, have al-ready been presented in [2–6]. The self-testing two-railchecker tree withn input pairs, as described in [17, 18],has one to one correspondence with ann-input paritytree. Thus, in [2, 4, 5] it has been shown that the al-gorithms proposed to design STE parity checkers canbe modified to be applied for designing STE two-railcheckers.

The parity trees and parity checkers, which are de-signed by Algorithm A [2, 4], Algorithm B∗ [2] andAlgorithm B0 [5], are tested by the normal input pat-terns for single stuck-at faults on the terminal lines ofthe XOR gates. However, in most implementations ofthe XOR gate there are possible faults that may not bemodeled as single stuck-at faults on the input or output

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Self-Testing Embedded Two-Rail Checkers 71

lines of the gate. In such cases it is desirable to testeach XOR gate exhaustively.

It has been shown in [2, 6] that for any one 4-by-nBoolean matrix with four distinct even-parity rows suchthat each column has exactly two 0’s and two 1’s, thereexists a STE even-parity checker that is tested by thefour rows of this matrix. Also in [2, Algorithm C∗],[5, Algorithm C0], [6] an algorithm has been presentedwhich finds a realization of the parity checker such thateach XOR gate of the tree is tested exhaustively by therows of the given matrix. Particularly, for any 4-by-nmatrix satisfying the above mentioned conditions thealgorithm presented in [2, Algorithm C∗], [5, Algo-rithm C0], [6] gives a set of STE parity checker real-izations any one of which has the same cost, that is,the same number of XOR gates, but the number ofXOR gate levels may differ from realization to real-ization. The algorithm given in [2, Algorithm C∗], [5,Algorithm C0], [6] suffers from the following draw-backs. The authors have not shown that for any 4-by-n Boolean matrix satisfying the necessary conditionsthe set of STE parity checker realizations that can bedesigned by their algorithm includes an optimal real-ization with respect to the number of XOR gate levels.Also the authors have not given guidelines to reducethe number of realizations that should be designed inorder to get the best realization that can be designed bytheir algorithm, thus an exhaustive search of the designspace is required which when the number of inputs isnot small can be prohibitively large.

In [19] it was shown that by duplicating one of theinput pairs of the two-rail checker the algorithm givenin [2, Algorithm C∗], [5, Algorithm C0], [6] can beapplied in a much larger number of cases.

To avoid the above drawbacks a new method to de-sign STE parity checkers was presented in [15]. In[15] guidelines are given which help in reducing thenumber of STE realizations that should be examined toget an optimal one, avoiding the exhaustive design ofall possible realizations. The optimality of a realiza-tion refers to the number of gate levels; all realizationshave the same number of gates. The drawback of themethod presented in [15] is that the functionality of theguidelines has been verified only by examples, thustheir general applicability is questionable.

A technique allowing the exercising of the final two-rail checker under dependency constrains of the func-tional blocks input data was proposed recently in [16].The conditions of our method and of the method givenin [6], are more general than the constrains of [16]

and can be used to design any checker, not only thefinal.

This paper gives a new simple and straightforwardmethod for designing CTE parity trees, and STE two-rail checker trees. The great advantage of the proposedmethod is that it is the only one that gives in a simple andstraightforward way an optimal (when the necessaryinput code words are provided) CTE/STE realizationwith respect to the number of gate levels and hardwareoverhead (zero hardware overhead).

2. Design of CTE Parity Trees

Through out this paper parity trees realized with two-input XOR gates are considered. Thus when in the se-quence of this paper we refer to a parity tree realizationwe mean a realization with two-input XOR gates. Inthis section we first discuss the necessary conditionswhich are satisfied by any test set of a parity tree real-ized with two inputs XOR gates.

It has been shown in [20] that if a parity tree is real-ized with two input XOR gates, then four inputs (testpatterns) of the tree are sufficient to test exhaustivelyany XOR gate of the tree, or in other words, when thetree receives four suitable input patterns each XOR gateof the tree receives all possible four input patterns. Ofcourse, the actual four test patterns required depend onthe exact shape of the parity tree.

The following lemma gives the necessary conditionsthat satisfy any test set of a parity tree realized with twoinputs XOR gates. This lemma is similar to Lemma 1of [6].

Lemma 1. Consider a4-by-n Boolean matrix F′

whose rows constitute a test set of a parity tree re-alized with two inputs XOR gates. Then F′ has distinctrows, two of which have even parity and the other twoodd parity, and each of its columns has exactly two0’sand two1’s.

A proof of the above Lemma is given in [21].There are six possible 4-bit sequences with two 0’s

and two 1’s:

a0 a1 a2 a3 a4 a5

0 0 0 1 1 10 1 1 1 0 01 0 1 0 1 01 1 0 0 0 1

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We can see thata0 anda3 are bitwise complementary,alsoa1, a4 anda2, a5 are bitwise complementary. Thatis, a3 = a0, a4 = a1, a5 = a2.

Let a Q-matrix be any 4-by-n Boolean matrix withcolumns from the set{a0,a1,a2,a3,a4,a5} and dis-tinct rows, such that two rows have even parity and theother two have odd parity. Also, let anR-matrix beany 4-by-n Boolean matrix with columns from the set{a0,a1,a2} and distinct rows, two of which have evenparity and the other two have odd parity. Note thataccording to Lemma 1, when the four test patterns ofa parity tree entered as the rows of a matrix, result in aQ-matrix.

In the Appendix we prove that if we replace thecolumnsa3,a4 anda5 of a 4-by-n Q-matrix F ′ withthe columnsa0,a1 anda2, respectively, we get anR-matrix F . It is evident that a number of distinctQ-matrices correspond to the sameR-matrix. LetSF bethe set ofQ-matricesF ′ which corresponds to the sameR-matrix F .

Theorem 1. If in a realization of a parity tree eachXOR is tested exhaustively when the tree receives therows of an R-matrix F, then the same is valid whenthe tree receives the rows of a Q-matrix F′, whereF ′ ∈ SF , and vice versa.

Proof: We can see thatai ⊕aj = ak andai ⊕ aj =ak for i, j, k ∈ {0, 1, 2} i 6= j, j 6= k andk 6= i . Thatis, if we substitute the input sequenceai of a XOR gateby ai then the output sequence of the gate is comple-mented. Also if the XOR gateg receives the sequencesai andaj with i 6= j and i, j ∈ {0, 1, 2}, and we re-placeai , andaj with ai andaj , respectively, then theoutput sequence ofg remains the same. Suppose that

Fig. 1. A complete parity tree with four XOR gate levels.

for the realizationT of a parity tree each XOR gate istested exhaustively by the rows of a matrixF . Whenduring normal operationT receives as input vectors therows ofF, a gateg of T receives the input sequencesai

andaj with i 6= j andi, j ∈ {0, 1, 2}. Then taking intoaccount the above we conclude that whenT receives,during normal operation, as input vectors the rows ofa matrix F ′, where F ′ ∈ SF , the gateg receives theinput sequencesai ,aj or ai ,aj or ai , aj with i 6= jand i, j ∈ {0, 1, 2}. We can see that each pair of se-quences (ai ,aj ), (ai ,aj ) and (ai , aj ) with i 6= j andi, j ∈ {0, 1, 2} gives all possible four vectors. There-fore, each gateg of T is tested exhaustively. The proofof the inverse can be made in the same way. 2

Theorem 1 implies that the design of a CTE paritytree for aQ-matrix F ′ is equivalent to the design of aCTE parity tree for anR-matrix F , whereF ′ ∈ SF .

Consider a parity tree with the suitable input se-quencesa0, a1 and a2 assigned to the inputs of thetree so that each XOR gate is tested exhaustively. LetXi (m), X j (m) andXk(m) be the number ofai ,aj andak input sequences respectively on them level of a par-ity tree, whereai ,aj ,ak ∈ {a0,a1,a2},ai 6= aj ,aj 6=ak and ak 6= ai . For example on the third level ofthe parity tree of Fig. 1 we haveXi (3)= 2, X j (3)= 3and Xk(3)= 3. The counting of the levels beginsfrom the root of the tree. Consider the output of the treeas the input of the 0th level. Then taking into accountthat the inputs of a XOR gate with outputai areaj andak we conclude that in a complete parity tree

Xi (m+ 1) = X j (m)+ Xk(m)

X j (m+ 1) = Xi (m)+ Xk(m)

Xk(m+ 1) = Xi (m)+ X j (m)

(1)

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Then using the recursive relations (1) we can calculatethe number ofai ,aj andak on each level of a completeparity tree with any number of XOR gate levels.

Henceforth we will characterize a XOR gate in a treeby its output sequence. For example a XOR gate withoutput sequenceai will be called anai gate.

The design of optimal CTE parity trees is based onthe following theorem.

Theorem 2. Let ni , nj and nk be the number of thecolumns ai ,aj and ak, respectively, of an R-matrixF,where ai ,aj ,ak ∈ {a0,a1,a2} and ai 6=aj ,aj 6=ak,

ak 6= ai . Then each parity tree realization such thatwhen the tree receives the four rows of F each XORgate of the tree is tested exhaustively has

gi = (nj + nk − X j (0)− Xk(0))/2

gj = (ni + nk − Xi (0)− Xk(0))/2

gk = (ni + nj − Xi (0)− X j (0))/2

gates with output sequences, respectively, ai ,aj

and ak.

Proof: Suppose that a parity treeT with mXOR gatelevels exists whose test set constitutes anR-matrix Fwith ni , nj andnk columnsai ,aj andak respectively.We append to the parity treeT XOR gates so as toget a complete parity treeT ′ with m XOR gate levels.For any appended XOR gate we know the desired out-put sequencea0,a1, or a2, so we can derive the inputsequences of that gate. Thus, fromT we get the com-plete parity treeT ′ and its test set. Note that adding aXOR gate with output sequenceai we reduce the num-ber of the input sequencesai of the tree by one andwe increase the number of the input sequencesaj andak by one. When the test set of the complete treeT ′

is entered as rows of a matrix we get anR-matrix Fwith Xi (m), X j (m) andXk(m) columnsai ,aj andak,

respectively. Suppose that to get the complete paritytreeT ′ we appended toT g′i XOR gates with output se-quenceai , g′j XOR gates with output sequenceaj andg′k XOR gates with output sequenceak. Therefore:

ni − g′i + g′j + g′k = Xi (m)

nj − g′j + g′i + g′k = X j (m)

nk − g′k + g′i + g′j = Xk(m)

or equivalently

g′i = (X j (m)+ Xk(m)− nj − nk)/2

g′j = (Xi (m)+ Xk(m)− ni − nk)/2

g′k = (Xi (m)+ X j (m)− ni − nj )/2

The number of XOR gates with output sequencesai ,aj

andak, respectively, in the complete parity treeT ′ isequal to

m−1∑f=0

Xi ( f ),m−1∑f=0

X j ( f ) andm−1∑f=0

Xk( f )

Therefore, the number of XOR gates with outputsequencesai ,aj and ak in the XOR treeT will be,respectively,

gi =m−1∑f=0

Xi ( f )− (X j (m)+ Xk(m)− nj − nk)/2

gj =m−1∑f=0

X j ( f )− (Xi (m)

+ Xk(m)− ni − nk)/2 and (2)

gk =m−1∑f=0

Xk( f )− (Xi (m)+ X j (m)− ni − nj )/2

From (1) we can see that

X j (m)+ Xk(m)

= 2Xi (m− 1)+ X j (m− 1)+ Xk(m− 1)

= 2Xi (m− 1)+ 2Xi (m− 2)

+ X j (m− 2)+ Xk(m− 2)

= · · · = 2m−1∑f=0

Xi ( f )+ X j (0)+ Xk(0)

In the same way we can see that

Xi (m)+ Xk(m) = 2m−1∑f=0

X j ( f )+ Xi (0)+ Xk(0)

Xi (m)+ X j (m) = 2m−1∑f=0

Xk( f )+ Xi (0)+ X j (0)

Then from the above relations and relations (2) we get:

gi = (nj + nk − X j (0)− Xk(0))/2,

gj = (ni + nk − Xi (0)− Xk(0))/2,

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74 Nikolos

and

gk = (ni + nj − Xi (0)− X j (0))/2 2

We note that when the output sequence of the treeis ai then Xi (0)= 1 and X j (0)= Xk(0)= 0. Theabove theorem implies that given the values ofni , nj

andnk, the number of gates with outputsai ,aj andak,respectively, is constant, independent of the realizationof the tree.

Design Procedure 1. Consider aQ-matrix F ′ andsuppose that we want to design a CTE parity tree suchthat each XOR gate of the tree is tested exhaustivelyby the four rows ofF ′.

At first replace the columnsa3,a4 and a5 of F ′

with the columnsa0,a1 and a2, respectively, to getthe R-matrix F , where F ′ ∈ SF . Let ni , nj and nk

be the number ofai ,aj and ak columns, respec-tively, of F , with ai ,aj ,ak ∈ {a0,a1,a2} andai 6=aj ,

aj 6=ak,ak 6=ai . Also suppose that the exclusive ORof the columns of theR-matrix F is equal toai . Thenwe havegi = (nj + nk)/2, gj = (ni + nk − 1)/2 andgk= (ni + nj − 1)/2.

Also let Zti , Zt

j andZtk be the numbers ofai ,aj and

ak input sequences, respectively, of thet level of a treeT with t XOR gate levels.

Algorithm 1. Consider a tree T consisting of oneXOR gate with output ai and set gi = gi −1 and t= 1.

Step 1.SetWi = min{Zti , gi }, Wj = min{Zt

j , gi } andWk = min{Zt

k, gk}.Step 2.Append to the inputs ofT with input sequences

ai ,aj andak,Wi ,Wj andWk XOR gates with out-puts, respectively,ai ,aj andak and setgi = gi −Wi ,

gj = gj −Wj , gk= gk −Wk andt = t + 1.Step 3.If gi = 0 andgj = 0 andgk = 0 end. Else go

to step 1.

The following example illustrates the application ofDesign Procedure 1.

Example 1. Consider the 4-by-11 matrixB′ = [a0 a0

a0 a0 a3 a3 a3 a1 a4 a5 a5] and that we want to designan optimal CTE parity tree such that each XOR gateof the tree is tested exhaustively when the tree receivesas inputs the rows ofB′. We can see thatB′ is a Q-matrix. According to Design Procedure 1, we have toreplace the columnsa3 a4 anda5 of B′with the columnsa0,a1 anda2, respectively. Then we get anR-matrix

B = [ a0 a0 a0 a0 a0 a0 a0 a1 a1 a2 a2], whereB′ ∈ SB.We can easily see that the exclusive OR among thecolumns ofB is equal toa0 andn0 = 7, n1 = 2 andn2 = 2. Then from Theorem 2 we getg0 = (n1+n2)/2= 2, g1 = (n0+ n2− 1)/2= 4 andg2 = (n0+ n1−1)/2= 4. Now we will follow Algorithm 1.

Consider a treeT consisting of one XOR gate withoutputa0 and setg0 = g0− 1 andt = 1.

(a) Append to the inputs ofT with input sequencesa0,a1 and a2: W0 = min{Z1

0, g0} = 0, W1 =min{Z1

1, g1} = 1 andW2 = min{Z12, g2} = 1 gates

with outputsa0,a1 anda2, respectively. Then setg0 = g0−0= 1, g1 = g1−1= 3, g2 = g2−1= 3andt = t + 1= 2.

(b) Append to the inputs ofT with input sequencesa0,a1 and a2: W0 = min{Z2

0, g0} = 1, W1 =min{Z2


with outputsa0,a1 anda2, respectively. Theng0 =g0−1= 0, g1 = g1−1= 2, g2 = g2−1= 2 andt = t + 1= 3.

(c) Append to the inputs ofT with input sequencesa0,a1 and a2: W0 = min{Z3

0, g0} = 0, W1 =min{Z3


with outputsa0,a1 anda2, respectively. Theng0 =0, g1 = g1−2= 0, g2 = g2−2= 0 and the designhas been completed.

The designed CTE parity tree is given in Fig. 2.

Theorem 3. For each Q-matrix F′ Procedure1givesan optimal, with respect to the number of gate levels,

CTE realization of the parity tree.

Proof: Theorem 1 implies that it is equivalent toprove that for theR-matrix F , whereF ′ ∈ SF , Pro-cedure 1 gives an optimal realization of the CTE paritytree. The theorem will be proved by contradiction.Let T be a CTE realization of the parity tree designedaccording to Procedure 1 andt is the number of gatelevels ofT . Suppose that for theR-matrixF there exista CTE realizationT ′ of the parity tree witht ′ XOR gatelevels, wheret ′< t . Note that given theR-matrix F ,hence the values ofni , nj andnk, all CTE realizationsof the parity tree with respect toF will have the sameoutput sequencea0,a1 or a2. We can see that the num-ber of XOR gates with outputsa0, and/ora1 and/ora2

which can be appended to the inputs of the XOR gatesof thew level, of a tree withw levels, increases withthe number of the gates of this level. Then taking into

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Fig. 2. A STE parity tree with 7 input sequencesa0, 2 input sequencesa1 and 2 inputsequencesa2.

account thatt ′< t and the fact that given anR-matrixF all CTE realizations of the parity tree will have thesame number of XOR gatesgi , gj andgk (Theorem 2)we conclude that each level ofT ′ will have a number ofXOR gates greater than or equal to the correspondinglevel of T and will exist at least one level ofT ′ whichwill contain more XOR gates thanT . But this contra-dicts the fact that following Procedure 1 we append toeach level the maximum number of gates and then wego to the next level. 2

3. Design of STE Two-Rail Checkers

A two-rail checker withn input pairs can be imple-mented as a tree of two-rail checkers with 2 inputpairs or as a two-level AND/OR network (or its equiv-alent) [18]. Also, a PLA implementation is possi-ble [22, 23]. A two-level AND/OR network (or itsequivalent) implementation as well as a PLA imple-mentation of a two-rail checker, it is required to re-ceive during normal, fault free, operation all possiblecode inputs to be self testing . Thus, we will addressthe problem of designing STE two-rail checkers re-alized as a tree of two-rail checkers with two inputpairs.

The self-testing two-rail checker tree withn inputpairs, as described in [18] has a one-to-one correspon-dence with ann-input parity tree, where each inputof the parity tree corresponds to an input pair fromthe two-rail code, and each XOR gate corresponds toa two-rail checker with two input pairs and 1-out-of-2output code [18] (Fig. 3). This correspondence impliesthat Algorithm 1 developed in Section 2 for design-

ing CTE parity trees can be applied to design two-railcheckers.

Also, the above correspondence implies that a STEtwo-rail checker tree withn input pairs can be designedif and only if the corresponding CTE parity tree can bedesigned. We have seen in Section 2 that a parity treerealization exists for which each XOR gate is testedexhaustively, when the parity tree receives as inputsthe rows of a matrixF ′, if and only if F ′ has fourdistinct rows, two of which have even parity and theother two have odd parity, and each of its columns hasexactly two 0’s and two 1’. Then, taking into accountthe above and the fact that one output line of the two-rail checker is the parity of, say, the true input lines ofthe checker, we come to the following conclusion.

Let T-matrix be any 4-by-2∗ n binary matrixsuch that the columnsk and k+ 1, for k = 1, 3,5, . . . ,2∗ n− 1, are bitwise complementary and ignor-ing the columnsi , for i = 2, 4, 6, 8, . . . ,2∗ n we geta Q-matrix F ′. A two-rail checker realization exists,such that when the two-rail checker withn inputs pairsreceives as inputs the rows of a matrixF ′′, each module(two-rail checker with 2 input pairs) receives all possi-ble code input vectors, if and only ifF ′′ is aT-matrix.

The above discussion implies that for any matrixF ′′

satisfying the above mentioned conditions, the follow-ing algorithm gives a two-rail checker realization thatis tested by the rows ofF ′′.

Design Procedure 2.

Step 1. Ignore the columnsi , for i = 2, 4, 6, 8, . . . ,2 ∗ n, of matrix F ′′ to get theQ-matrix F ′.

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76 Nikolos

Fig. 3. The one-to-one correspondence between two-rail checkers and parity trees.

Step 2.Use matrixF ′ and Design Procedure 1 to designan optimal CTE parity tree realization.

Step 3.Replace each XOR gate of the parity tree real-ization with a 2 input pairs two-rail checker. End.

Taking into account the correspondence among par-ity trees and two-rail checkers and the fact that for eachparticularQ-matrixF ′Design Procedure 1 gives an op-timal CTE parity tree realization, we conclude that foreach particularT-matrix F ′′ Design Procedure 2 givesan optimal STE two-rail checker realization.

Example 2. Consider the problem of designing a STEtwo-rail checker for the followingT-matrix: B′′ =[a0 a3 a0 a3 a0 a3 a0 a3 a3 a0 a3 a0 a3 a0 a1 a4 a4 a1 a5

a2 a5 a2]. Ignoring the columnsi , for i = 2, 4,6, 8, 10, 12, 14, 16, 18, 20, 22, we get theQ-matrixB′ = [a0 a0 a0 a0 a3 a3 a3 a1 a4 a5 a5]. Note thatB′ is the matrix given in Example 1 thus, Fig. 2 givesan optimal CTE realization of the parity tree. The STEtwo-rail checker can be designed from the CTE paritytree of Fig. 2 using the correspondence of Fig. 3.

4. Discussion

To estimate the practical interest of the proposed opti-mal STE two-rail checkers we will compare these withthe STE two-rail checkers designed according to [6].

The values ofn0, n1 andn2 have been generated ran-domly. The design procedure in [6] is based on succes-sive partition of the inputs into two groups satisfyingsome properties. Since each partition can be made inmany ways and guidelines have not been given in [6],the partition is generated randomly. A partition not sat-isfying the conditions is discarded and a new partition isgenerated randomly. When the number of inputs is notvery small, the number of the realizations that shouldbe designed in order to get the best realization, that canbe designed according to [6], is prohibitively large. Forexample for theQ-matrix B = [a0 a4 a1 a4 a4 a5 a2]following the algorithm given in [6] we get 18 differentrealizations. All realizations use the same number ofmodules (two-rail checkers with 2 input pairs) but as wecan see from Table 1 the optimal STE two-rail checkershave a significantly smaller number of module levels.For the case thatni = 0, nj = r (r = 1, 2, . . .) andnk = 1 there exist only one STE realization. Thus, inthis case the proposed method and the method givenin [6] give the same realization (case marked with∗ inTable 1).

In the following we will investigate the cases thatduring the normal fault free operation the checker doesnot receive the rows of aT-matrix.

Let T ′ be any 4-by-n binary matrix with columnsfrom the set{a0,a1,a2} such that the columnsk andk + 1, for k = 1, 3, 5, . . . ,2 ∗ n − 1, are bitwisecomplementary and ignoring the columnsi , for i =

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Table 1.

Number of module levels

n0, n1, n2 [6] (L) Optimal (Lop) ((L − Lop)/L) ∗ 100

3, 3, 6 5 4 20.0

10, 3, 10 11 5 54.5

7, 16, 11 9 5 44.4

16, 8, 11 9 6 33.3

18, 13, 26 11 7 36.3

23, 13, 28 12 7 41.7

4, 0, 1 4 4∗ 0.0

9, 2, 9 7 5 28.6

20, 12, 15 9 6 33.3

1, 7, 10 7 5 28.6

4, 6, 5 6 4 33.3

10, 10, 7 10 5 50.0

15, 20, 25 11 7 36.3

1, 2, 1 2 2 0.0

13, 16, 9 10 6 40.0

10, 8, 5 6 5 16.7

9, 19, 14 11 6 45.4

9, 10, 5 10 5 50.0

14, 17, 22 11 6 45.4

8, 8, 3 7 5 28.6

2, 4, 6, 8, . . . ,2 ∗ n we get a matrix with four distincteven parity rows or four distinct odd parity rows. Con-sider that the checker receives the rows of aT ′-matrixF . Then there are two possible solutions. By dupli-cating the columnsk andk + 1 of F , wherek is anodd number, we get aT-matrix F ′. This duplicationimplies that the same output pair of the functional cir-cuit or another checker drives two input pairs of thetwo-rail checker. In [19] it was proven that a combi-national checker circuit constructed as a feedforwardinterconnection of two-rail checkers, including circuitswith reconvergent fanout from the two-rail input vari-ables and TRC outputs, is code-disjoint, and totallyself-checking (TSC) if all TRCs receive the four inputcombinations required as tests. Each module (2-inputtwo-rail checker) of the tow-rail checker tree designedaccording to our method, receives during the normalfault free operation all possible code inputs, thereforeour design is self-testing and code disjoint. The hard-ware overhead of this method is equal to the hardwarerequired for the implementation of one 2-input two-rail

checker module. The other solution is based on the useof the modified two-rail checker proposed in [24] or[25]. A modified two-rail checker receives as inputstwo column pairs ofF, (ai , ai ) and (aj , aj ) with i 6= jandi, j ∈ {0, 1, 2} and produces the pair (ai , ai ). Thenthe pair (ai , ai ) along with the rest columns ofF , thathave not been used, constitute aT-matrix. Then a STEchecker can be designed according to our method. Thisdesign has the same hardware overhead with the pre-viously described design but in some cases may haveone more module level.

In the cases that during the normal, fault free, opera-tion the checker does not receive the rows of aT-matrix,we can partition the inputs into groups such that eachgroupi receives the rows of aT-matrix Fi . Then foreach group we can design according to Procedure 2 anoptimal STE two-rail checker. The outputs of thesecheckers can be compacted using the methods given in[10] or [11]. As we have mentioned in the introduc-tion the hardware overhead of the method given in [10]as well as the delay imposed by the method given in[11] are prohibitively large for many inputs. But in thiscase due to the small number of the outputs that shouldbe compacted, the hardware and the delay overhead aresmall. We have, however, to note that the problem withthe stuck-at faults on the clock line, associated with themethods given in [10, 11], remains.

When the technique based on the partition of inputsinto groups cannot be used, we can use the design ofFig. 4. The first row consists ofn CG modules [11],wheren is the number of the input pairs. The row of theCG modules from any code input produces four codewords. We can consider three cases. Whenn= 2k+ 1,we setm1= k+1 andm2= k. Whenn= 2k andk is anodd number, we setm1=m2= k, while whenk is aneven number, we setm1= k+1 andm2= k−1. Thenit is easy to see that in any of the above cases the row ofthe CG modules receiving a code input generates a se-quence of four code words which constitute the rows ofaT-matrix M . Therefore, the proposed method in thispaper can be used to design an optimal STE two-railchecker forM , which receives its test set independentlyof which and how many code words are produced by itsdriving functional block or checker. The STE two-railchecker of Fig. 4 have the same hardware requirementswith those given in [11]. However, as we can see fromTable 2, the STE two-rail checkers of Fig. 4 are muchmore efficient, with respect to the number of modulelevels than those designed in [11]. In Table 2 the valuesof n have been generated randomly.

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78 Nikolos

Table 2.

Number of module levels

n [11] (L) Proposed (Lpr) ((L − Lpr)/L) ∗ 100

12 12 12 50.0

23 23 7 69.6

34 34 7 79.4

35 35 7 80.0

57 57 8 86.0

64 64 8 87.5

5 5 4 20.0

20 20 6 70.0

47 47 8 83.0

18 18 6 66.7

15 15 6 60.0

27 27 7 74.0

60 60 8 86.7

4 4 4 00.0

38 38 7 81.6

23 23 7 69.6

42 42 7 83.3

24 24 7 70.8

53 53 8 84.9

19 19 6 68.4

5. Conclusion

A simple and straightforward method of designingCompletely Testable Embedded parity trees and Self-Testing Embedded two-rail checkers was presented inthis paper. The great advantage of the proposed methodis that it is the only one that gives in a simple and

Fig. 4. Alternative design.

straightforward way an optimal CTE/STE realization.In the other, already known from the open literaturemethods, the selection of an optimal realization is basedon the exhaustive search of the design space, which isusually prohibitively large. Besides the theoretical in-terest that an optimal solution always has, in Section 4we have shown that the proposed design has also prac-tical interest. The building block in the case of CTEparity trees in the two input XOR gate. In the caseof STE two-rail checker withn-input pairs, the build-ing block is the two-rail checker with 2 input pairs.During normal, fault free, operation, each XOR gatereceives all possible input vectors, while each two-railchecker with 2 input pairs receives all possible code in-put vectors. Designing the 2 input two-rail checker asproposed in [26] we get optimal STE two-rail checkerswith respect to realistic faults (stuck-at, stuck-on andvarious bridging, breaks and stuck-open faults).

Appendix

Lemma A1. Consider a4-by-n Q-matrix F′. Thenif we replace the columns a3,a4 and a5 of F′ withthe columns a0,a1 and a2, respectively, we get anR-matrix F.

Proof: a3,a4 anda5 are bitwise complementary witha0,a1 and a2, respectively. If we replace a columnai ,ai ∈ {a3,a4,a5}, by its complement all the rowsof the 4-by-n matrix will change parity, thus, we willget a matrix whose two rows will have even and theother two odd parity. Now suppose that two rows ofF ′ differ only in the f bit. It is obvious that replacingthe f column of theF ′ with its complement thef bit

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of both rows will change value, thus the two rows willremain distinct. The above implies that replacing thecolumnsa3,a4 anda5 of a Q-matrix F ′ by the columnsa0,a1 anda2, respectively, we get a matrix with distinctrows, two of which have even parity and the other twoodd parity, that is, we get anR-matrix F . 2

Acknowledgment

I would like to thank my students Sidiropoulos G.,Foukarakis G., and Gnardellis Th., for the comparisonresults of Table 1.

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Dimitris Nikolos was born in Arta, Greece. He received the B.Sc.degree in Physics in 1979, the M.Sc. degree in Electronics in 1981and the Ph.D. degree in computer Science in 1985, all from Universityof Athens. He is currently an Associate Professor at the Departmentof Computer Engineering and Informatics of University of Patras,and head of the Hardware and Computer Architecture Division. Hehas served as Program co-chairman of the 3rd IEEE InternationalOn-Line Testing Workshop. He has also served on the program com-mittees for the IEEE International On-Line Testing Workshop in1995 and 1996, and for the 1997 IEEE International Symposium onDefect and Fault Tolerance in VLSI Systems. His main researchinterests are fault-tolerant computing, computer architecture, VLSIdesign, test and design for testability.

self-testing embedded two-rail checkers

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