semiconductor device technology overview
TRANSCRIPT
-
7/29/2019 semiconductor device technology overview
1/38
Semiconductor Device
Technology
-
7/29/2019 semiconductor device technology overview
2/38
Technology
MEMS technology is based on a number of tools and
methodologies used to form small structures with dimensions in the micrometer
scale
Three basic building blocks deposit thin films of material on a substrate
to apply a patterned mask on top of the films by photolithograpy
and to etch the films selectively
Bonding and packaging
A MEMS process is structured sequence of these operationsto form actual devices Significant parts adopted from integrated circuit (IC) technology
Most devices are built on wafers of silicon, like ICs
There are however several processes that are not derived from ICtechnology, and as the technology continues to grow the gap with ICtechnology also grows
-
7/29/2019 semiconductor device technology overview
3/38
Photolithography Lithography is the transfer of a pattern to a photo-
sensitive material by selective exposure to aradiation source such as light.
A photosensitive material is a material thatexperiences a change in its physical properties when
exposed to a radiation source.Radiation sources:
Optical
X Ray
Electron beam
-
7/29/2019 semiconductor device technology overview
4/38
Photo-resist coating
-
7/29/2019 semiconductor device technology overview
5/38
Positive and Negative PL
The photosensitive polymers areused, called photoresist (or resist)
When resist is exposed to aradiation source of a specific awavelength (UV) the chemicalresistance of the resist to developersolution changes
If the resist is placed in a developersolution after selective exposure toa light source, it will etch away oneof the two regions (exposed orunexposed).
If the exposed material is etchedaway by the developer and theunexposed region is resilient, thematerial is considered to be apositive resist
If the exposed material is resilient tothe developer and the unexposedregion is etched away, it isconsidered to be a negative resist
-
7/29/2019 semiconductor device technology overview
6/38
Additive and Subtractive PL PL technique is capable of producing fine features in an economic fashion
Photosensitive layer is often used as a temporary mask when etching an
underlying layer, to transfer the pattern to the underlying layer
Photoresist may also be used as a template for patterning material deposited
after lithography. The resist is subsequently etched away, and the material
deposited on the resist is "lifted off".
The deposition template (lift-off)approach for transferring apattern from resist to anotherlayer is less common than usingthe resist pattern as an etchmask. The reason for this is thatresist is incompatible with most
MEMS deposition processes,usually because it cannotwithstand high temperaturesand may act as a source ofcontamination.
Once the pattern has been
transferred to another layer, theresist is usually stripped
-
7/29/2019 semiconductor device technology overview
7/38
Alignment A useful device may involve
several lithography steps.
Patterns for differentlithography steps that belongto a single structure must bealigned to one another.
The first pattern transferred to
a wafer usually includes a setof alignment marks, which arehigh precision features thatare used as the referencewhen positioning subsequentpatterns
Subsequent masks should alsohave reference marks so thatall the steps are alignedproperly
-
7/29/2019 semiconductor device technology overview
8/38
Exposure The exposure parameters required for accurate pattern transfer
depend primarily on the wavelength of the radiation source andthe dose required to achieve the desired properties change of thephotoresist.
Different photoresists exhibit different sensitivities to differentwavelengths.
The physics of the exposure process affects the dose
actually received. A highly reflective layer under the photoresist may result
in the material experiencing a higher dose than if the
underlying layer is absorptive, as the photoresist is
exposed both by the incident radiation as well as the
reflected radiation.
The dose will vary with resist thickness.
There are also higher order effects, such as interference
patterns in thick resist films on reflective substrates,
which may affect the pattern transfer quality and
sidewall properties.
At the edges of pattern light is scattered and diffracted
-
7/29/2019 semiconductor device technology overview
9/38
The Lithography Process1. Dehydration bake: dehydrate the wafer to aid resist adhesion.
2. HMDS prime: coating of wafer surface with adhesion promoter.Not necessary for all surfaces.
3. Resist spin/spray - coating of the wafer with resist either by spinningor spraying. Typically desire a uniform coat.
4. Soft bake - drive off some of the solvent in the resist, mayresult in a significant loss of mass of resist (and
thickness). Makes resist more viscous.
5. Alignment - align pattern on mask to features on wafers.6. Exposure - projection of mask image on resist to cause selective
chemical property change.
7. Post exposure bake - baking of resist to drive off further solvent content.Makes resist more resistant to etchants (other thandeveloper).
8. Develop - selective removal of resist after exposure (exposed resist
if resist is positive, unexposed resist if resist is positive).Usually a wet process (although dry processes exist).
9. Hard bake - drive off most of the remaining solvent from the resist.
10. Descum - removal of thin layer of resist scum that may occludeopen regions in pattern, helps to open up corners.
-
7/29/2019 semiconductor device technology overview
10/38
-
7/29/2019 semiconductor device technology overview
11/38
The Lithography Module The lithography process steps need to be characterized as a sequence in order to ensure that the
remaining resist at the end of the modules is an optimal image of the mask, and has the desiredsidewall profile.
Unfortunately, even if the module is executed perfectly, the properties of lithography are veryfeature and topography dependent. The designer influences the lithographic process through theirselections of materials, topography and geometry.
The material(s) upon which the resist is
to be deposited is important, as it affects
the resist adhesion. The reflectivity and
roughness of the layer beneath the
photoresist determines the amount of
reflected and dispersed light present
during exposure. It is difficult to obtain a
nice uniform resist coat across a surface
with high topography, which complicatesexposure and development as the resist
has different thickness in different
locations. If the surface of the wafer has
many different height features, the
limited depth of focus of most
lithographic exposure tools will becomean issue
-
7/29/2019 semiconductor device technology overview
12/38
Photolithography
-
7/29/2019 semiconductor device technology overview
13/38
The resolution of the process depends on
the resolution of the mask
the resolution of the photo-resist the optical aberrations and
depth of focus in the exposed field and
the diffraction effects
-
7/29/2019 semiconductor device technology overview
14/38
Deposition The ability to deposit thin films of materials is important for MEMS
The thin film thickness can vary from a few nm to about 100 m. Depositions that happen because of a chemical reaction:
These processes exploit the creation of solid materials directly from chemicalreactions in gas and/or liquid compositions or with the substrate material. The solidmaterial is usually not the only product formed by the reaction. Byproducts caninclude gases, liquids and even other solids.
Chemical Vapor Deposition (CVD) Electrodeposition
Epitaxy
Thermal oxidation
Depositions that happen because of a physical reaction:
These processes involve material deposition by physically moving on to thesubstrate. There is no chemical reaction which forms the material on the substrate.This is not completely correct for casting processes, though it is more convenient tothink of them that way.
Physical Vapor Deposition (PVD): evaporation and sputtering Casting
-
7/29/2019 semiconductor device technology overview
15/38
-
7/29/2019 semiconductor device technology overview
16/38
Chemical Vapor Deposition (CVD) The substrate is placed inside a reactor to which a number of gases are supplied. A
chemical reaction takes place between the source gases. The product of that reaction is a
solid material which condenses on all surfaces inside the reactor. The two most important CVD technologies in MEMS are the Low Pressure CVD (LPCVD) and
Plasma Enhanced CVD (PECVD). The LPCVD process produces layers with excellent uniformity of thickness and material
characteristics. The main problems with the process are the high deposition temperature(higher than 600C) and the relatively slow deposition rate.
The PECVD process can operate at lower temperatures (down to 300 C) thanks to the extraenergy supplied to the gas molecules by the plasma in the reactor.
The quality of the PECVD films tend to be inferior
to processes running at higher temperatures.
Most PECVD deposition systems can only deposit
the material on one side of the wafers on 1 to 4
wafers at a time. LPCVD systems deposit films onboth sides of at least 25 wafers at a time.
a good rule of thumb is that higher process
temperature yields a material with higher quality
and less defects.
-
7/29/2019 semiconductor device technology overview
17/38
Comparison LPCVD and PECVD for silicon oxide
LPCVD SiH4 (g) + O2(g) + heat SiO2(s) + 2H2(g)
300 - 500 mT at 450 C
PECVD
SiH4 (g) + N2O (g) + plasma SiO2(s) + 2N2(g) + 2H2(g)
Addition of 3%-5% phosphine gas for doped PSG.
LPCVD and PECVD for silicon nitride
LPCVD
3SiH2 Cl2 (g) + 4NH3(g) + heat Si3 N4 (s) + 6HCl (g) + 6H2(g)
300-500 mT at 700-900 C High stress (1-3 GPa), strong films
Low stress requires adjustment of SiH2 Cl2 : NH3 ratio
PECVD
3SiH4 (g) + 4NH3(g) + plasma Si3N4 (s) + 12H2(g)
Stoichiometry can be adjusted via gas ratios to produce SixNy
Lower flow temperature
Faster attack by HF
Dopant source is toxic
-
7/29/2019 semiconductor device technology overview
18/38
Electrodeposition (electroplating) Typically restricted to electrically conductive materials.
Basically two technologies: Electroplating and Electroless plating.
Electroplating process: the substrate is placed in a liquid solution (electrolyte). When anelectrical potential is applied between a conducting area on the substrate and a counterelectrode (usually platinum) in the liquid, a chemical redox process takes place resultingin the formation of a layer of material on the substrate and usually some gas generationat the counter electrode.
Electroless plating process is more complex. Chemical solution is used, in whichdeposition happens spontaneously on any surface which forms a sufficiently high
electrochemical potential with the solution. This process is desirable since it does notrequire any external electrical potential and contact to the substrate during processing.Unfortunately, it is also more difficult to control with regards to film thickness anduniformity.
The electrodeposition is well used to make filmsof metals such as copper, gold and nickel. The
films can be made in any thickness from ~1m to>100m. The deposition is best controlled whenused with an external electrical potential,however, it requires electrical contact to thesubstrate when immersed in the liquid bath. Inany process, the surface of the substrate must
have an electrically conducting coating before thedeposition can be done.
-
7/29/2019 semiconductor device technology overview
19/38
Thermal oxidation This is one of the most basic deposition technologies. It is simply oxidation of
the substrate surface in an oxygen rich atmosphere. The temperature is raised
to 800 C-1100 C to speed up the process. This is also the only depositiontechnology which actually consumes some of the substrate as it proceeds. Thegrowth of the film is spurned by diffusion of oxygen into the substrate, whichmeans the film growth is actually downwards into the substrate. As thethickness of the oxidized layer increases, the diffusion of oxygen to thesubstrate becomes more difficult leading to a parabolic relationship betweenfilm thickness and oxidation time for films thicker than ~100nm. This process is
naturally limited to materials that can be oxidized, and it can only form filmsthat are oxides of that material. This is the classical process used to form silicondioxide on a silicon substrate.
This is a simple process, whichunfortunately produces films withsomewhat limited use in MEMS
components. It is typically used to formfilms that are used for electrical insulationor that are used for other process purposeslater in a process sequence
-
7/29/2019 semiconductor device technology overview
20/38
Epitaxy This technology is quite similar to CVD processes. If the substrate is an ordered
semiconductor crystal (i.e. silicon, gallium arsenide), this process allows to continuebuilding on the substrate with the same crystallographic orientation with the substrateacting as a seed for the deposition. If an amorphous/polycrystalline substrate surface isused, the film will also be amorphous or polycrystalline.
There are several technologies for creating the conditions inside a reactor needed tosupport epitaxial growth, The most important is Vapor Phase Epitaxy (VPE). In this process,a number of gases are introduced in an induction heated reactor where only the substrateis heated. The temperature of the substrate typically must be at least 50% of the meltingpoint of the material to be deposited.
An advantage of epitaxy is the high growth rate of material, which allows the formation offilms with considerable thickness (>100m). Epitaxy is a widely used technology forproducing silicon on insulator (SOI) substrates. The technology is primarily used fordeposition of silicon.
This has been and continues to be anemerging process technology in MEMS.The process can be used to form films ofsilicon with thicknesses of ~1m to>100m. Some processes require hightemperature exposure of the substrate,whereas others do not require significantheating of the substrate. Some processescan even be used to perform selective
deposition, depending on the surface ofthe substrate.
-
7/29/2019 semiconductor device technology overview
21/38
Evaporation In evaporation the substrate is placed inside a vacuum chamber, in which a block
(source) of the material to be deposited is also located. The source material is
then heated to the point where it starts to boil and evaporate. The vacuum isrequired to allow the molecules to evaporate freely in the chamber, and theysubsequently condense on all surfaces. This principle is the same for allevaporation technologies, only the method used to the heat (evaporate) thesource material differs. There are two popular evaporation technologies, whichare e-beam evaporation and resistive evaporation each referring to the heatingmethod. In e-beam evaporation, an electron beam is aimed at the source material
causing local heating and evaporation. In resistive evaporation, a tungsten boat,containing the source material, is heated electrically with a high current to makethe material evaporate.
Many materials are restrictive in
terms of what evaporation method
can be used (i.e. aluminum is quite
difficult to evaporate using resistive
heating), which typically relates to
the phase transition properties of
that material.
-
7/29/2019 semiconductor device technology overview
22/38
Sputtering
Sputtering is a technology in which the material is released from the source atmuch lower temperature than evaporation. The substrate is placed in a vacuum
chamber with the source material, named a target, and an inert gas (such asargon) is introduced at low pressure. A gas plasma is struck using an RF powersource, causing the gas to become ionized. The ions are accelerated towardsthe surface of the target, causing atoms of the source material to break offfrom the target in vapor form and condense on all surfaces including thesubstrate. As for evaporation, the basic principle of sputtering is the same forall sputtering technologies. The differences typically relate to the manor inwhich the ion bombardment of the target is realized.
-
7/29/2019 semiconductor device technology overview
23/38
CastingIn this process the material to be deposited is dissolved in liquid form in a solvent.
The material can be applied to the substrate by spraying or spinning. Once the
solvent is evaporated, a thin film of the material remains on the substrate. This is
particularly useful for polymer materials, which may be easily dissolved in organic
solvents, and it is the common method used to apply photoresist to substrates (in
photolithography). The thicknesses that can be cast on a substrate range all the way
from a single monolayer of molecules (adhesion promotion) to tens of
micrometers. In recent years, the casting technology has also been applied to formfilms of glass materials on substrates.
Casting is a simple technology which canbe used for a variety of materials (mostlypolymers). The control on film thickness
depends on exact conditions, but can besustained within +/-10% in a wide range.If you are planning to usephotolithography you will be usingcasting, which is an integral part of thattechnology. There are also otherinteresting materials such as polyimide
and spin-on glass which can be appliedby casting.
-
7/29/2019 semiconductor device technology overview
24/38
Etching Processes In order to form a functional MEMS structure
on a substrate, it is necessary to etch the thinfilms previously deposited and/or thesubstrate itself. In general, there are twoclasses of etching processes:
Wet etching where the material is dissolvedwhen immersed in a chemical solution
Dry etching where the material is sputtered ordissolved using reactive ions or a vapor phase
etchant
-
7/29/2019 semiconductor device technology overview
25/38
Wet etching
This is the simplest etching technology. All it requires is a container with a liquid solution thatwill dissolve the material in question. Unfortunately, there are complications since usually a
mask is desired to selectively etch the material. One must find a mask that will not dissolve orat least etches much slower than the material to be patterned. Secondly, some single crystalmaterials, such as silicon, exhibit anisotropic etching in certain chemicals. Anisotropic etchingin contrast to isotropic etching means different etch rates in different directions in thematerial. The classic example of this is the crystal plane sidewalls that appear whenetching a hole in a silicon wafer in a chemical such as potassium hydroxide (KOH). Theresult is a pyramid shaped hole instead of a hole with rounded sidewalls with a isotropicetchant. The principle of anisotropic and isotropic wet etching is illustrated in the figure below.
This is a simple technology, which will give good results if you can find the combination ofetchant and mask material to suit your application. Wet etching works very well for etchingthin films on substrates, and can also be used to etch the substrate itself. The problem withsubstrate etching is that isotropic processes will cause undercutting of the mask layer by thesame distance as the etch depth. Anisotropic processes allow the etching to stop on certaincrystal planes in the substrate, but still results in a loss of space, since these planes cannot bevertical to the surface when etching holes or cavities. If this is a limitation for you, you should
consider dry etching of the substrate instead. However, keep in mind that the cost per waferwill be 1-2 orders of magnitude higher to perform the dry etching
If you are making very small features in thin films (comparable to the film thickness), you mayalso encounter problems with isotropic wet etching, since the undercutting will be at leastequal to the film thickness. With dry etching it is possible etch almost straight down withoutundercutting, which provides much higher resolution.
-
7/29/2019 semiconductor device technology overview
26/38
Dry etching
In RIE, the substrate is placed inside a reactor in whichseveral gases are introduced. A plasma is struck in thegas mixture using an RF power source, breaking the gasmolecules into ions. The ions are accelerated towards,and reacts at, the surface of the material being etched,forming another gaseous material. This is known as thechemical part of reactive ion etching. There is also aphysical part which is similar in nature to the sputteringdeposition process. If the ions have high enoughenergy, they can knock atoms out of the material to beetched without a chemical reaction. It is a very complextask to develop dry etch processes that balancechemical and physical etching, since there are manyparameters to adjust. By changing the balance it is
possible to influence the anisotropy of the etching,since the chemical part is isotropic and the physical parthighly anisotropic the combination can form sidewallsthat have shapes from rounded to vertical.
Three classes called reactive ion etching (RIE), sputter etching, and vapor phaseetching.
-
7/29/2019 semiconductor device technology overview
27/38
DRIE A special subclass of RIE which continues to grow rapidly in popularity is
deep RIE (DRIE). In this process, etch depths of hundreds of microns can beachieved with almost vertical sidewalls. The primary technology is based onthe so-called "Bosch process", named after the German company RobertBosch which filed the original patent, where two different gas compositionsare alternated in the reactor. The first gas composition creates a polymer onthe surface of the substrate, and the second gas composition etches the
substrate. The polymer is immediately sputtered away by the physical partof the etching, but only on the horizontal surfaces and not the sidewalls.Since the polymer only dissolves very slowly in the chemical part of theetching, it builds up on the sidewalls and protects them from etching. As aresult, etching aspect ratios of 50 to 1 can be achieved. The process caneasily be used to etch completely through a silicon substrate, and etch ratesare 3-4 times higher than wet etching.
-
7/29/2019 semiconductor device technology overview
28/38
Deep reactive ion etching
a dry etch process, patented by the Robert Bosch Corporation can beused to etch deeply into a silicon wafer while leaving vertical
sidewalls
independent of the crystallographic orientation.
Etching rates in excess of 3 um per min., selectivities to photo masking materials greater than 70:1(at least
twice as much for silicon dioxide), excellent profile control and non-uniformities across the wafer of 5%
or less.
This unique capability has greatly expanded the flexibility andusefulness of bulk micromachining
-
7/29/2019 semiconductor device technology overview
29/38
Passivation step:At the beginning of cycle a CF
based plasma is used to conformally deposit a fewmonolayers of PTFE-like fluorocarbon polymer
across all surfaces exposed to plasma.
Etch Step 1: The plasma gas is switched to SF
to create a plasma chemistry that
isotropically etches silicon. Through theapplication of a d.c. bias to the platen, ions
from the plasma bombard the surface of the
wafer, removing the polymer. Increased ion
energy in the vertical direction results in a
much higher rate of removal of fluorocarbon
polymer from surfaces parallel to wafersurface.
Etch Step 2: Following selective polymer removal, the silicon surface at the base of the
trench is exposed to reactive fluorine-based species that isotropically etch the
unprotected silicon. The remainig fluorocarbon polymer protects the vertical walls of
the trench frometching.
ETCHING
MECHANISM
-
7/29/2019 semiconductor device technology overview
30/38
Sputter etching is essentially RIE without reactive ions. The systems usedare very similar in principle to sputtering deposition systems. The bigdifference is that substrate is now subjected to the ion bombardmentinstead of the material target used in sputter deposition.
Vapor phase etching is another dry etching method, which can be donewith simpler equipment than what RIE requires. In this process the waferto be etched is placed inside a chamber, in which one or more gases areintroduced. The material to be etched is dissolved at the surface in achemical reaction with the gas molecules. The two most common vaporphase etching technologies are silicon dioxide etching using hydrogen
fluoride (HF) and silicon etching using xenon diflouride (XeF2), both ofwhich are isotropic in nature. Usually, care must be taken in the design ofa vapor phase process to not have bi-products form in the chemicalreaction that condense on the surface and interfere with the etchingprocess.
Dry etching is expensive to run compared to wet etching. If you are concerned with featureresolution in thin film structures or you need vertical sidewalls for deep etchings in thesubstrate, you have to consider dry etching. If you are concerned about the price of yourprocess and device, you may want to minimize the use of dry etching. The IC industry haslong since adopted dry etching to achieve small features, but in many cases feature size isnot as critical in MEMS. Dry etching is an enabling technology, which comes at a sometimes
high cost.
-
7/29/2019 semiconductor device technology overview
31/38
High Aspect Ratios
Aspect ratio = 18:1,
SiO2 mask,
etch rate 2.2 mm/min
80 mm deep silicon trenches,
4.5mm space, 2mm line width
Through Wafer Etching
Anisotropy > 0.99,
selectivity >300:1 to SiO2 mask,
etch rate mm/min.
Wafer is 200 mm thick
Underlayer is SiO2.
BULK MICROMACHINING
-
7/29/2019 semiconductor device technology overview
32/38
BULK MICROMACHINING
Bonding
Fusion bonding Wafer to wafer bonding after
face to face intimate contact
Van der Waals forces
Anneal at 1100 oC
Anodic bonding Silicon to glass at 450 oC
Applied field
-
7/29/2019 semiconductor device technology overview
33/38
BULK MICROMACHINING
Etching Isotropic Anisotropic - (100),(110)
etched faster than (111) EDP, KOH
Etch stop Heavy boron doping p-n junction
Porous silicon can be used formaking deep cavities
100 silicon
Silicon oxide coating
Heavily boron-doped region
Open pattern on oxide
(111) Planes
V-Trench
-
7/29/2019 semiconductor device technology overview
34/38
Surface Micromachining
Anchor definition:
(a) after the sacrificial layer is
deposited,
(b) after the anchor region is
defined,
(c) after patterning the structurallayer and
(d) after release
Sacrificial Layer
Anchor region
defined
Structural Layer
-
7/29/2019 semiconductor device technology overview
35/38
A cantilever
A cantilever may have
problems of bending and
stiction
-
7/29/2019 semiconductor device technology overview
36/38
Electrochemical Fabrication
Truly three dimensional structure byelectrochemical deposition
Deposit multiple layers (unlimitednumber) by electrochemical technique -structural and sacrificial
No need for clean room. Self containedsystem. Fully automated.
-
7/29/2019 semiconductor device technology overview
37/38
metallization
Nozzle plate
Active diamond
heater element
Examples of MEMS Applications
Sili MEMS F d F ilit
-
7/29/2019 semiconductor device technology overview
38/38
Wet Etch Station for Bulk Micromachining
Silicon MEMS Foundry Facility
Semiconductors Complex Ltd, Chandigarh
Existing 0.8 m, 6 wafer CMOS
facility augmented
Surface ( SiO2 sacrificial layer),
bulk (front and back, KOH)
DRIE (large aspect ratio )
Silicon-glass anodic bonding
Test at wafer / device level
Test Facility
Facilities also augmented at BEL
Bangalore and CEERI for MEMS
FabricationF t B k Ali