semiconductor memory design. organization of memory systems driven only from outside data flow in...
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Semiconductor Memory Design
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Organization of Memory Systems
Driven only from outside
Data flow in and out
A cell is accessed for reading by selecting its row and column.
Memories may simultaneously select 4, 8, 16 …columns.
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Overall Architecture of Memory Design
n=m=8216=25,536 bits=2Kb
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RAM
• Read-write random access memories (RAM)– Store data in active circuits; information
is lost if the power supply is interrupted
• Common Types– Static RAM (SRAM)– Dynamic RAM (DRAM)
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SRAM
• SRAM– Store value in flip-flop circuits as long as
power is on– High speed memories with clock cycles
in the range of 5 to 50 ns
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DRAM
• DRAM– Store values on capacitors– Prone to noise and leakage problems– Slower than SRAM, clocking at 50 ns to
200 ns.–More dense than SRAM
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RAM Timing Parameters
Write signal is active low
tAC(read access time): presentation of address Until data is out
tAC =(0.5 to 0.8)Tcycle
Tcycle: minimum time neededin order to complete successiveread and write operation
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Organization of Memory Systems
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AND and NOR Decoders
Take an n-bit address.Produce 2n outputs,One of which is activated.
Problem: n=6 implies1. 64 NAND62. 64 inverters
It is difficult to implementNAND6 in standard CMOS
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Predecoder Configurations
Use a 2 stage design to implementNAND6
Use logical effortto determinethe best design
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Structure of Two-Level Decoder
Wire 1: from A0, A1
Wire 2: from A2, A3
Wire 3: from A4, A5
Need 12precoderssince n=6
Each precoder Will drive24 final decoders
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Static RAM Cell Design
• Static Memory Operation
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Basic SRAM and VTC
A wordline is used to select the cellBitlines are used to perform read and write operations on the cell
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Cross Coupled Configuration
The cell can only flip its internal state when one of its internal cross VS.During a read op, we must not disturb its current state.During a write op, we must force the internal voltage to swing past VS to change a state.
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6T SRAM CellCan be replaced byundoped polysiliconto minimize area.
Use high threshold transistors to reduce leakage current.
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Wordline and Double Bitline Configuration
One wordline is enabled.
The decoder must drive: (2 gate cap + wire cap) x # of cells in a row
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Design of Transistor Size for Read Operation
Assume:q=0 and qb=1Initially: b=VDD, bb=VDD
Cbit is discharged through M1.b begins to drop.bb remains high.
Vbb and Vb is added to a sense amplifier and stored ona data buffer.
Upon completion of the read,wl returns to 0 Cbig prechargedTo VDD.
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Bitline capacitance
Bitline capacitance: (S/D cap+ wire cap+S/D contact cap) X # of cells in a column
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Sizing of M3 and M1
Icell could charge the gatecapacitance of M2, thus lowering qb.
Solution: Adjust the sizing of M3 and M1 to minimize changes in q.
W3/W1 can be determined.
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Discharge time is controlled by sizing of M3 and M1
Icell should be large enough to Discharge bitline capacitance within20% to 30% of the cycle time.
Icell=Cbit (dV/dT)
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Write Operation
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Transistor Sizing
VQB=0.4=VTN
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SRAM Cell Layout
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Optional materials
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Column Pull-Up Configurations
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Address Transition Detection Circuit
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Column Decoding and Multiplexing
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Column Selection
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4-bit Column Address
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Write Driver Circuit
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Basic Read Circuitry
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Differential Voltage Sense Amplifier
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Detecting “0” and “1”
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Latch-based Sense Amplifier
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Replica Circuit for Sense Amplifier Clock Enable
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Replica Cell Design
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Basic Memory Architecture
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Divided Wordline Strategy to Reduce Power and Delay
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Bitline Partition to Reduce Delay
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Peripheral Circuits
• Decoders• Sense Amplifiers• Column Precharge• Data Buffers