semiconductor process reliability...semiconductor processing always yield a distribution of...
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Semiconductor Process Reliability
SVTW 2012Esko Mikkola, Ph.D. & Andrew Levy
3580 West Ina Road,| Tucson AZ | 85741 | 520-742-3300 | ridgetopgroup.com
IC Failure Modes Affecting Reliability
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Via/metallization failure mechanismsElectro migrationStress migration
Transistor failure mechanismsTime-dependent dielectric breakdown (TDDB)Hot carrier degradationNBTI and PBTI
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IC Failure Modes Affecting Reliability
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Failure Mode Physics System Effect
NBTI (PMOS) / PBTI (NMOS)
• Negative Vt shift• Slower speed
• Timing Faults in Processors• Resettable – but increasing severity over time
TDDB
Soft Breakdown:• Slower speed• Weakened gate oxide• Increased leakage current
• Increased ESD Vulnerability• Non‐resettable timing faults
Hard Breakdown/Punch‐through • Catastrophic Short
Hot Carrier (NMOS)
• Positive Vt shift• Change in sub‐threshold swing
• Increased Off‐state power• Increased current draw• Decreased data retention time in DRAM
Metal Migration(Stress migration, electromigration)
• Higher resistance in Via connections
• Open circuits
• Catastrophic Open
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Electromigration – Stress Migration
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ElectromigrationTransport of material caused by the gradual movement of the ions in a conductor due to the momentum transfer between conducting electrons and diffusing metal atoms. Known for more than 100 years, but became of practical interest with the advent of Semiconductor technologiesEffects are occurring primarily at the boundaries and material interfacesCu is intrinsically less sensitive to EM than Al but scaling and increasing current densities are pushing the limits
Stress MigrationResults from tensile stress due TCE mismatch of materialsStress relaxation over time through diffusion of vacancies leads to the formation of voids
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Via/Metallization Failure Mechanisms
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Electromigration (physical mechanism)
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Electromigration (temperature dependency)
Reported data from fast Wafer Level Reliability (fWLR) tests shows that every 50 °C increase in the stress temperature will reduce the electromigration testing time by one order of magnitude.
Ki‐Don Lee, et al., “VIA PROCESSING EFFECTS ON ELECTROMIGRATION IN 65 NM TECHNOLOGY”, 44th Annual International Reliability Physics Symposium, San Jose, 2006.
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Transistor Failure Mechanisms
MOS transistor
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Transistor Failure Mechanisms
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Time Dependent Dielectric Breakdown
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Failure mechanism in MOSFETs, when the gate oxide breaks down as a result of long-time application of relatively low electric field (as opposite to immediate breakdown, which is caused by strong electric field). The breakdown is caused by formation of a conducting path through the gate oxide to substrate due to electron tunnelling current, when MOSFETs are operated close to or beyond their specified operating voltages.
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Time‐Dependent Dielectric Breakdown (TDDB)
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TDDB influenced by:Smaller GeometryMore TunnelingThinner Oxides (Tox)Substrate Injection (NMOS)
Effects: Increased NoiseIncreased PowerSwitching characteristicsEventual wear-out and failure
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TDDB (types of breakdown)
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TDDB (types of breakdown)
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TDDB (DC stress vs. AC stress)
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Hot Carrier Injection (HCI) Degradation
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A phenomenon in which an electron or a hole gains sufficient kinetic energy to overcome a potential barrier necessary to break an interface state.
To become “hot” and enter the conduction band of SiO2, an electron must gain a kinetic energy of 3.3 eV. For holes, the valence band offset in this case dictates they must have a kinetic energy of 4.6 eV. The term "hot electron" comes from the effective temperature term used when modelling carrier density and does not refer to the actual temperature of anything. High temperatures caused by the effect are unrelated to the phrase "hot electron effect".
Carrier is injected from channel into gate dielectricEffects include heating of the device and increased leakage current
Heating is caused by hot electrons giving off their excess energy as phonons.
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Hot Carrier Degradation
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Hot Carrier Degradation
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Hot Carrier Degradation
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Hot Carrier Degradation
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NBTI and PBTI
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Negative bias temperature instability (NBTI) is a key reliability issue in MOSFETs. Of immediate concern for pMOS→ operate almost always with negative gate-to-source voltage
The very same mechanism affects also nMOS when biased in the accumulation regime (PBTI)
NBTI manifests as An increase in threshold voltageA decrease in drain current and transconductanceThe degradation has logarithmic dependence on time
Two kinds of trap contribute to NBTI:Interface traps→ cannot be recovered over a reasonable time of operation - permanent traps→ similar to the ones resulting from HCI→ In case of NBTI, the electric field breaks Si-H bonds located at the SiO2 interface. H is
released and migrates in the substrate. The remaining dangling bond Si- (Pb center) contribute to the threshold voltage degradation.
Pre-existing traps located in the bulk of the dielectric (and supposedly nitrogen related), are filled with holes coming from the PMOS channel. Those traps can be emptied when the stress voltage is removed. This Vth degradation can be recovered over time. (Annealing effect)
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NBTI and PBTI
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NBTI and PBTI (SiO2 gate)
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NBTI and PBTI (high‐k gate)
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NBTI and PBTI (SiO2 vs. high‐k)
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NBTI and PBTI (relaxation)
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NBTI and PBTI (relaxation)
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NBTI and PBTI (DC vs. AC stress)
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Mitigation: Process Data
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Semiconductor processing always yield a distribution of parameter values
Minimum geometries have larger fluctuations
Smaller feature size & lower voltages increase the impact of variation of transistor properties on chip performance and yield
Foundry-supplied Process Design Kit (PDK) may not give sufficiently accurate data for critical design parameters
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Mitigation: Addressing Nanoscale Reliability Issues
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Use Additional Design MarginIncreased power consumptionImpacts overall circuit performance
Collect Accurate Process informationLifetime Reliability Monitoring
Real-time operating embedded sensorsActual State of Health for critical pathsEarly warning of impending failure
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ProChek™
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Semiconductor
Reliability
Characterization
System
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Characteristics of ProChek
• Targets bulk CMOS, SOI, SiGe reliability concerns•NBTI / PBTI, TDDB, HC, EM, SM
• Test Coupon•As little as 1 * 1mm chip area•MPW for lower cost•32 – 1024 devices can be tested in parallel for maximum throughput•On‐chip per transistor heaters to 325 °C, greatly reducing test time•Synthesizable (except for on‐chip heaters) to speed deployment
• Bench‐top Tester•Fully programmable test conditions cover DC and AC stress cases•Portable and compact•ATE not needed
• Host Controller•Easy‐to‐use software GUI•Rich suite of built‐in reliability test templates•Data processing capabilities
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Sentinel Silicon™
Die‐Level
Prognostic
Solutions and
Applications
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Calibrated Prognostic Distance
Stress/Accelerate:
T1 = 99% failure in canary
T2 = 1% failure in host
Prognostic Distance = T2 – T1
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Questions?
Ridgetop Group Inc.
Andrew LevyDirector, Semiconductor & Precision
Instruments [email protected] x115 (office)503-320-5466 (mobile)
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Esko Mikkola, Ph.D.Senior Principal [email protected] x141 (office)