seminar on packaging suruchi
TRANSCRIPT
-
8/2/2019 Seminar on Packaging Suruchi
1/39
PACKAGING
-
8/2/2019 Seminar on Packaging Suruchi
2/39
What is Electronic
Packaging? Packaging provides the interconnection
Chip Protection
Environmental, thermal, mechanical
CommunicationMaximize I/O
Power
Heat removal
-
8/2/2019 Seminar on Packaging Suruchi
3/39
WHAT IS PACKAGING?
Packaging refers to The packaging of the interconnected chips
The interconnection for signal transmission,power & ground
The encapsulation for protecting the chips
The heat sinks or the other cooling devices
The housing for electromagnetic interferenceshielding
-
8/2/2019 Seminar on Packaging Suruchi
4/39
Goals of Electronic
PackagingMaximize I/O
Minimize thermal issues
Heat dissipation Thermal stress
Environmental protection and encapsulation
Lowest cost needed to get results
Drive to continuously reduce size and power
Talk by DL Thomas of Endicott
-
8/2/2019 Seminar on Packaging Suruchi
5/39
Performance
Cycle Time
Circuit Delay
Circuit Technology
Chip Power cooling (W/cm2) Package Delay
Circuit Density
I/O (Connections/cm2
) Wireability (Lines/cm)
Interconnection length
Propagation medium(Circuits/ns)
-
8/2/2019 Seminar on Packaging Suruchi
6/39
LEVELS OF PACKAGING
Level 0:bare chip as removed from the finishedsurface
Level 1:bare chip mounted on a chip carrier &
encapsulated as a packaged chip Level 2:printed circuit board with packaged
chips, modules & other components Level 3:motherboard into which PCB are inserted.
Level 4:electronic module Level 5:system formed by electronic module
-
8/2/2019 Seminar on Packaging Suruchi
7/39
-
8/2/2019 Seminar on Packaging Suruchi
8/39
Design Considerations
Hazards to be protected against: mechanicaldamage, exposure to weather and dirt,electromagnetic interference, etc.
Heat dissipation requirements
Tradeoffs between tooling capital cost and per-unit cost
Tradeoffs between time to first delivery andproduction rate
Availability and capability of suppliers
-
8/2/2019 Seminar on Packaging Suruchi
9/39
Design Considerations
(contd)User interface design and convenience
Ease of access to internal parts when required
for maintenance
Product safety, and compliance with regulatorystandards
Esthetics, and other marketing considerationsService life and reliability
-
8/2/2019 Seminar on Packaging Suruchi
10/39
Different variations in
Packaging Conventional Variation: one or more chips areattached to ceramic substrate via soldered joints
Direct Chip Attach Module: The chip is attacheddirectly on the card, called DCAM
Multichip Module Laminate: The chip is attached
via a cardlet,one of many small cards attached toa larger card, resulting in MCML
-
8/2/2019 Seminar on Packaging Suruchi
11/39
Materials andProcessing
Materials properties
Good insulating characters
Low dielectric constant
High thermal conductivity
High strength and toughness
Stability at the processing
temperatures Thermal expansion near attachments
Acceptable cost
-
8/2/2019 Seminar on Packaging Suruchi
12/39
Electronic Connections
Developed in the
1960s
Leads perpendicularto the body of thepackage
DIP = dual-inline-package
-
8/2/2019 Seminar on Packaging Suruchi
13/39
Electronic
Connections(contd)Surface Mount Technology (SMT)
Method for constructingelectronic circuits;components are mounteddirectly onto the surfaceof printed circuit boards
Usually smaller than its
leaded counterpart(because it has no leads orsmaller leads).
-
8/2/2019 Seminar on Packaging Suruchi
14/39
Electronic Connections
(contd)Pin Grid Array (PGA)Integrated circuit is mounted ona ceramic slab
Pins can then be inserted intothe holes in a printed circuit boardand soldered in place.
This type of package occupiesless space than older types such asthe dual in-line package (DIL or
DIP).
-
8/2/2019 Seminar on Packaging Suruchi
15/39
Electronic Connections
(contd)
Ceramic or plastic chip
carrierLeads project downand away all four sidesof a square package
Quad Flat Package (QFP)
-
8/2/2019 Seminar on Packaging Suruchi
16/39
Electronic Connection
Flip Chip- PGA
Allows the
microprocessor tooperate more easily atits optimal temperaturesby designing theprocessor core on the
"flip side" (or backside)of the chip, facing away
from the motherboard
-
8/2/2019 Seminar on Packaging Suruchi
17/39
ElectronicConnections(contd)
Ball Grid Array- BGA
Solution to theproblem of producinga miniature packagefor an integratedcircuit with many
hundreds of pins.
-
8/2/2019 Seminar on Packaging Suruchi
18/39
Electronic Connections(contd)
Land Grid Array- LGA
Used by Intel to moreevenly distribute power
Less expensive than
PGA and BGA
-
8/2/2019 Seminar on Packaging Suruchi
19/39
INTERCONNECTIONS
What are interconnections?
It constitute the communications bottleneck ofelectronic digital system.
-
8/2/2019 Seminar on Packaging Suruchi
20/39
Types ofinterconnections
Electrical: These include Electrical conductorsWires
Cables Connectors
Optical
Fibers
-
8/2/2019 Seminar on Packaging Suruchi
21/39
Uses ofinterconnections
Creating monopoly
Introducing competition
Protecting competition
-
8/2/2019 Seminar on Packaging Suruchi
22/39
What is Connector ?
An electromechanical system that provides aseparable interface b/w 2 electronic subsystemswithout an unacceptable effect on signal integrity
or loss in power
-
8/2/2019 Seminar on Packaging Suruchi
23/39
Connector Types
Three major connector types
Board to Board
Wire to Board
Wire to Wire
-
8/2/2019 Seminar on Packaging Suruchi
24/39
Connector Applications
Signal Application: It span the range of currentfrom microamps to hundred of milliamps.Drivingvoltages for this are generally a few volts.
Power Application:It faces the additionalrequirement of thermal management.
-
8/2/2019 Seminar on Packaging Suruchi
25/39
Consideration forconnectors
Two types of consideration
Electrical Considerations
Mechanical considerations
-
8/2/2019 Seminar on Packaging Suruchi
26/39
ElectricalConsiderations
Electrical consideration in connector selectioninclude:
Contact current ratings
Contact resistance Contact impedance;capacitance &inductance Power ratingShielding and filtering requirements
-
8/2/2019 Seminar on Packaging Suruchi
27/39
Mechanical Considerations
Number of contacts Insertion/extraction forceNumber of expected connect/disconnect cycles
Body style and profile Polarization and keying requirementShock and vibrationArea and height of connectorManual or automatic connector placement
-
8/2/2019 Seminar on Packaging Suruchi
28/39
Connector Problems
Signal Degradation: it is due to the faster clockrates and shorter rise time
Cross Talk:it is caused by inductive andcapacitive coupling b/w contacts
There are mainly 2 types of crosstalk
-
8/2/2019 Seminar on Packaging Suruchi
29/39
Connector
Problems(contd) Backward (Near-end): it is measured at the
driving end of the connector & represents thesum of capacitive and inductive coupling.
Forward (Far-end): is measured at the receivingend of the connector & represents capacitiveminus inductive coupling.
-
8/2/2019 Seminar on Packaging Suruchi
30/39
What are wires &cables ?
Selection of wires for interconnection involvesseveral consideration
Color coding
Temperature rating
Solid or stranded
Individual,multi cable, flat cable
Current carrying capacity
-
8/2/2019 Seminar on Packaging Suruchi
31/39
Wires & Cable(contd)
Temperature rating of wires depends on
Test environment Assembly environment
Use environment
-
8/2/2019 Seminar on Packaging Suruchi
32/39
-
8/2/2019 Seminar on Packaging Suruchi
33/39
Prevention of vibration
The circuit elements should be mounteddirectly to a mechanically stiff substrate ofprinted wiring board.
Employ sufficient hold down techniques tocircuit assemblies & devices by staking throughthe use of adhesive interfaces and screws toreduce relative motion b/w components & theirmounting surfaces.
Leads should be soldered into position with verylittle prestressing. Signal wires RF cables should be clamped
approx. 1-in intervals to prevent fraying duringvibration
-
8/2/2019 Seminar on Packaging Suruchi
34/39
Prevention ofvibration(contd)
Sensitive circuits should be packaged in a housingmade from high-density materials such as steel
or tungsten.
-
8/2/2019 Seminar on Packaging Suruchi
35/39
What is Reliability and Testing in engineering?
Packaging is backbone of electronics
Employs almost every engineering discipline
Easily affected by environmental factors
Evaluate lifetimes of years in weeks
Reliability and Testing
-
8/2/2019 Seminar on Packaging Suruchi
36/39
Testing and Modeling
Air flow
Temperatures
Deformation
Stresses and solderfatigue
Reliability and Testing
-
8/2/2019 Seminar on Packaging Suruchi
37/39
Accelerate Failure Mechanisms
- Temperature/humidity/voltage corrosion& migration
- Thermal Accelerated oxidation,undesirable chemical processes
- Mechanical Joint strength, shipping,cracks, de-lamination,
Reliability and Testing
-
8/2/2019 Seminar on Packaging Suruchi
38/39
Future Trends inElectronic Packaging
Higher I/O, increased density
Reduced voltage (noise sensitivity)
Increased energy dissipation requirements
Multiple voltage levels
Higher operating frequency (RF range)
Environmental constraints (Pb elimination)
-
8/2/2019 Seminar on Packaging Suruchi
39/39
THANK YOU